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An Experimental Demonstration of GaN CMOS Technology

Rongming Chu, Yu Cao, Mary Chen, Ray Li, and Daniel Zehnder

 was demonstrated. Section II describes the process of making

Abstract—This letter reports the first demonstration of the GaN CMOS. Section III discusses measured characteristics
Gallium Nitride (GaN) Complementary Metal-Oxide- of the fabricated GaN NMOS and PMOS devices, as well as
Semiconductor (CMOS) field-effect-transistor (FET) technology. the CMOS inverter IC.
Selective area epitaxy was employed to have both GaN N-channel
MOSFET (NMOS) and P-channel MOSFET (PMOS) structures
on the same wafer. An AlN/SiN dielectric stack grown by Metal- II. DEVICE FABRICATION
Organic Chemical Vapor Deposition (MOCVD) served as the gate
“oxide” for both NMOS and PMOS, yielding enhancement-mode
N- and P-channel with the electron mobility of 300 cm2/V-sec and
hole mobility of 20 cm2/V-sec, respectively. Using the GaN CMOS
technology, a functional inverter Integrated Circuit (IC) was
fabricated and characterized.

Index Terms—GaN, Transistor, CMOS, Gate Insulator,

Selective Area Epitaxy, Inverter, IC

I. INTRODUCTION

R ECENT advances in GaN electronics have demonstrated

superior transistor performance for both power switching
[1,2] and microwave/millimeter wave applications [3,4].
Today’s GaN electronics are mostly based on discrete
transistors. In order to take full advantage of performance
benefits of GaN transistors and to reduce the cost of GaN-
based electronic systems, the IC approach is needed. For
example, GaN discrete power transistors have shown
unprecedented switching speed [5]. However, when used in
power circuits, the fast-switching GaN power transistor has to
be intentionally slowed down [1] to avoid voltage instabilities
[6] caused by chip-to-chip parasitic inductance. Integration of
power switches and their driving circuitry on the same chip is
the ultimate approach to minimize the parasitic inductance. In
addition to performance improvements, the on-chip integration
approach will also offer a large cost advantage due to the
reduced assembly and packaging cost. Fig. 1 Major steps of fabricating GaN NMOS and PMOS on the same wafer.

Difficulty in making P-channel transistor and integrating it
with N-channel transistor has been the major obstacle for
realizing the GaN IC. There have been a few early studies on
GaN P-channel transistors [7-10]. In this letter, we present a
study investigating the integration of GaN NMOS and PMOS.
MOCVD selective area epitaxy was performed to enable both
GaN NMOS and PMOS device structures on the same wafer.
MOCVD-grown AlN/SiN dielectric stack was used as the gate
“oxide” for both NMOS and PMOS. With these two device
fabrication techniques, a functional GaN CMOS inverter IC
Manuscript received xxx xx, 2015.
Rongming Chu, Yu Cao, Mary Chen, Ray Li, and Daniel Zehnder are with
the HRL Laboratories, Malibu, CA 90265 USA (phone: 310-317-5517; e-
mail: rchu@hrl.com).
Fig. 1 shows major steps for fabricating the GaN CMOS.
An AlGaN/GaN N-channel high-electron-mobility-transistor
(HEMT) structure was grown on a sapphire substrate by
MOCVD, and encapsulated with a 50-nm-thick SiN
passivation layer. The AlGaN top barrier layer has an Al
composition of 25% and a thickness of 5 nm. Portion of the
HEMT structure and the SiN passivation layer was then etched
down to the GaN buffer. After that, selective MOCVD
regrowth of the P-channel transistor structure was performed
on the etched portion, using SiO2 as a growth mask. The P-
channel transistor structure consists of a 30-nm-thick AlGaN
back barrier layer with 25% Al composition, a 20-nm-thick
undoped GaN channel layer, and a 50-nm-thick GaN hole
supply layer highly doped with Mg. Device isolation was

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Device Letters
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achieved by ion implantation. Gate trenches were then formed
through the AlGaN top barrier of the N-channel transistor and
the Mg-doped GaN hole supply layer of the P-channel
transistor, by low-power plasma etching. After that, a 10/10-
nm-thick AlN/SiN gate dielectric stack was grown by
MOCVD, lining the etched gate trenches. Similar gate
dielectric stack was used in Ref. 5, 11, and 12. Ti/Al-based
ohmic metal stack annealed in N2 ambient forms the
source/drain electrodes of the NMOS. Ni/Au-based ohmic
stack annealed in O2 ambient forms the source/drain electrodes
of the PMOS. Finally, a Ni/Au metal stack was deposited and
patterned to form gate electrodes and interconnects.
III. DEVICE CHARACTERIZATION AND DISCUSSION
DC-IV and CV characterization were performed on FAT-
FET structures for both NMOS and PMOS. Having a gate
length of 100 µm, the FAT-FET ensures that the measured on-
resistance is dominated by the intrinsic channel resistance, and
the measured gate capacitance is dominated by the intrinsic
gate-to-channel capacitance. From the IV measurement, on-
resistance (dominated by channel resistance) as a function gate
bias can be calculated. Integration of measured gate
capacitance over gate voltage yields channel carrier density as
a function of gate bias. Knowing channel resistance and
channel carrier density, drift mobility of channel carriers as a
function of gate bias can then be extracted. Dependences of
channel carrier density and mobility for both NMOS and
PMOS are shown in Fig. 2.
Fig. 2 Channel carrier density and mobility of an NMOS (a) and a PMOS (b)
extracted from DC-IV and CV measurement of FAT-FET structures.
Both the NMOS and the PMOS channels exhibited
enhancement-mode operation. The NMOS exhibited a channel
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electron mobility of around 300 cm2/V-sec. Using the same
gate dielectric stack and with a process optimized for discrete
NMOS, we were able to achieve channel electron mobility of
more than 1000 cm2/V-sec [12]. Further improvement of the
GaN CMOS process is needed to improve the NMOS mobility
to what was achievable with a discrete device process. PMOS
exhibited a channel hole mobility of up to 20 cm2/V-sec. This
value is higher than typical bulk mobility of 10 cm2/V-sec in
P-type GaN [13], and is lower than the reported 2-dimentional-
hole-gas (2DHG) mobility of 40 cm2/V-sec [14, 15]. Further
improvement of PMOS channel mobility could be achieved by
optimizing epitaxial regrowth, gate trench etch, and gate
dielectric deposition process.
Fig. 3 shows DC-IV output and transfer characteristics of
NMOS and PMOS transistors with the gate length of 0.5 µm
and gate width of 75 µm. The gate-to-source and gate-to-drain
spacing were kept at 2 µm. The NMOS showed a threshold
voltage of around 0V, and an on-resistance of 10 ohm-mm at a
gate bias of 5V. The PMOS showed a threshold voltage of
around 0 V, and an on-resistance of 1314 ohm-mm at a gate
bias of -5V. The PMOS showed noticeable buffer leakage
when the drain bias was greater than 2V. Possible cause of the
buffer leakage is the parallel conduction at the MOCVD
regrowth interface between the PMOS epi-structure and the
GaN buffer.
Fig. 3 DC-IV output (ID vs. VDS) and transfer (ID vs. VGS) characteristics of an
NMOS ((a) and (b)) and a PMOS ((c) and (d)). Gate length was 0.5 µm; gate-
to-source and gate-to-drain spacing were 2 µm; gate width was 75 µm.
Using the 0.5-µm-gate-length NMOS and PMOS transistors,
a CMOS inverter IC was constructed. Fig. 4 shows microscopy
top view photograph of a fabricated inverter IC. The NMOS
and PMOS transistors have a gate width of 50 µm and 500 µm,
respectively. Fig. 4 also shows measured voltage transfer curve
of the fabricated GaN CMOS inverter under a DC bias (Vdd)
of 5 V. Voltage gain of 9.6 was obtained when the input
voltage (Vin) was at 1.2 V. The DC current drew by the
inverter (Idd) peaked up at a Vin of 1.5 V, when the inverter
underwent switching. Thanks to the CMOS configuration, the
Idd was considerably lower when the Vin was at 0 and 5 V,
suggesting low static power consumption. The static power
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consumption could be further decreased by reducing the off-
state leakage of the NMOS and PMOS.
Fig. 4 Microscopy top view photograph and measured voltage transfer curve
of a fabricated GaN CMOS inverter IC. The NMOS and PMOS have a gate
width of 50 µm and 500 µm, respectively.
Dynamic switching characterization was performed by
connecting the inverter input to a pulse generator, and the
output to the high impedance port of an oscilloscope. The Vdd
was kept at 5 V. The input pulse was 0 V to 5 V with 10 ns
rise/fall time. Measured waveforms showing the edges of the
input and the output signal are plotted in Fig. 5. The output
signal showed a voltage swing of close to 0~5V. The fall time
was 90 ns; and rise time was 670 ns. Slower rise time is due to
higher on-resistance of the PMOS. Although the performance
is yet to be improved, the functional inverter IC proves the
feasibility of the GaN CMOS technology.
Fig. 5 Waveforms showing the fall (a) and rise edge (b) of the output signal
from the inverter IC. The DC bias was 5 V. The rise/fall time of the input
signal was 10 ns.
IV. SUMMARY
We have developed a GaN CMOS technology integrating
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enhancement-mode GaN NMOS and PMOS on the same
wafer. The GaN CMOS technology was based on two process
techniques: (1) selective area epitaxial regrowth; (2) MOCVD-
grown gate dielectrics. Enhancement-mode NMOS and PMOS
with channel mobility of 300 cm2/V-sec and 20 cm2/V-sec
were achieved. Using the GaN CMOS technology, we
fabricated an inverter IC, showing 0~5 V switching with
voltage gain of 9.6, fall time of 90 ns and rise time of 670 ns.
REFERENCES
[1] Hughes, B.; Lazar, J.; Hulsey, S.; Musni, M.; Zehnder, D.; Garrido, A.;
Khanna, R.; Chu, R.; Khalil, S.; Boutros, K., "Normally-off GaN-on-Si
multi-chip module boost converter with 96% efficiency and low gate
and drain overshoot," in Applied Power Electronics Conference and
Exposition (APEC), 2014 Twenty-Ninth Annual IEEE , vol., no.,
pp.484-487, 16-20 March 2014. DOI: 10.1109/APEC.2014.6803352
[2] Wu, Y.-F.; Gritters, J.; Shen, L.; Smith, R.P.; Swenson, B., "kV-Class
GaN-on-Si HEMTs Enabling 99% Efficiency Converter at 800 V and
100 kHz," in Power Electronics, IEEE Transactions on, vol.29, no.6,
pp.2634-2637, June 2014. DOI: 10.1109/TPEL.2013.2284248
[3] Rongming Chu; Shen, L.; Fichtenbaum, N.; Brown, D.; Zhen Chen;
Keller, Stacia; DenBaars, Steven P.; Mishra, Umesh K., "V-Gate GaN
HEMTs for X-Band Power Applications," in Electron Device Letters,
IEEE , vol.29, no.9, pp.974-976, Sept. 2008. DOI:
10.1109/LED.2008.2001639
[4] Shinohara, K.; Regan, D.C.; Yan Tang; Corrion, A.L.; Brown, D.F.;
Wong, J.C.; Robinson, J.F.; Fung, H.H.; Schmitz, A.; Oh, T.C.; Kim,
S.J.; Chen, P.S.; Nagele, R.G.; Margomenos, A.D.; Micovic, M.,
"Scaling of GaN HEMTs and Schottky Diodes for Submillimeter-Wave
MMIC Applications," in Electron Devices, IEEE Transactions on ,
vol.60, no.10, pp.2982-2996, Oct. 2013. DOI:
10.1109/TED.2013.2268160
[5] Rongming Chu; Hughes, B.; Chen, M.; Brown, D.; Li, R.; Khalil, S.;
Zehnder, D.; Chen, S.; Williams, A.; Garrido, A.; Musni, M.; Boutros,
K., "Normally-Off GaN-on-Si transistors enabling nanosecond power
switching at one kilowatt," in Device Research Conference (DRC), 2013
71st Annual , vol., no., pp.199-200, 23-26 June 2013. DOI:
10.1109/DRC.2013.6633862
[6] Fang Luo; Zheng Chen; Lingxiao Xue; Mattavelli, P.; Boroyevich, D.;
Hughes, B., "Design considerations for GaN HEMT multichip
halfbridge module for high-frequency power converters," in Applied
Power Electronics Conference and Exposition (APEC), 2014 Twenty-
Ninth Annual IEEE , vol., no., pp.537-544, 16-20 March 2014. DOI:
10.1109/APEC.2014.6803361
[7] Shatalov, Maxim; Simin, G.; Jianping Zhang; Adivarahan, Vinod;
Koudymov, A.; Pachipulusu, R.; Asif Khan, M., "GaN/AlGaN p-
channel inverted heterostructure JFET," in Electron Device Letters,
IEEE , vol.23, no.8, pp.452-454, Aug. 2002. DOI:
10.1109/LED.2002.801295
[8] Zimmermann, T., M. Neuburger, M. Kunze, I. Daumiller, A. Denisenko,
A. Dadgar, A. Krost, and E. Kohn. "P-channel InGaN-HFET structure
based on polarization doping." Electron Device Letters, IEEE, vol. 25,
no. 7 pp.450-452, Jul. 2004. DOI: 10.1109/LED.2004.830285
[9] Guowang Li; Ronghua Wang; Bo Song; Verma, J.; Yu Cao; Ganguly,
S.; Verma, A.; Jia Guo; Xing, H.G.; Jena, D., "Polarization-Induced
GaN-on-Insulator E/D Mode p-Channel Heterostructure FETs," in
Electron Device Letters, IEEE , vol.34, no.7, pp.852-854, July 2013.
DOI: 10.1109/LED.2013.2264311
[10] Hahn, Herwig, Benjamin Reuters, Alexander Pooth, Achim Noculak,
Holger Kalisch, and Andrei Vescan, "First small-signal data of GaN-
based p-channel heterostructure field effect transistors," Japanese
Journal of Applied Physics, vol. 52, no. 12R, art no. 128001, Nov.
2013. DOI: 10.7567/JJAP.52.128001 .
[11] Rongming Chu; Brown, D.; Zehnder, D.; Xu Chen; Williams, A.; Li, R.;
Chen, M.; Newell, S.; Boutros, K., "Normally-off GaN-on-Si metal-
insulator-semiconductor field-effect transistor with 600-V blocking
capability at 200 °C," in Power Semiconductor Devices and ICs
(ISPSD), 2012 24th International Symposium on , vol., no., pp.237-240,
3-7 June 2012. DOI: 10.1109/ISPSD.2012.6229067
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/LED.2016.2515103, IEEE Electron
Device Letters
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[12] Hughes B.; Chu, R.; Lazar J.; and Boutros, K., “Increasing the
switching frequency of GaN HFET converters,” To be published in the
Digest 2015 International Electron Device Meeting, Dec. 2015.
[13] Nakamura, Shuji, Takashi Mukai, Masayuki Senoh, and Naruhito
Iwasa, "Thermal annealing effects on p-type Mg-doped GaN films,"
Japanese Journal of Applied Physics, vo. 31, no. 2B, art no. L136, Feb.
1992. DOI: 10.1143/JJAP.31.L139.
[14] Reuters, B., H. Hahn, A. Pooth, B. Holländer, U. Breuer, M. Heuken, H.
Kalisch, and A. Vescan, "Fabrication of p-channel heterostructure field
effect transistors with polarization-induced two-dimensional hole gases
at metal–polar GaN/AlInGaN interfaces," Journal of Physics D: Applied
Physics, vol. 47, no. 17, art no. 175103, Apr. 2014. DOI: 10.1088/0022-
3727/47/17/175103
[15] Nakajima, Akira, Yasunobu Sumida, Mahesh H. Dhyani, Hiroji Kawai,
and EM Sankara Narayanan. "High density two-dimensional hole gas
induced by negative polarization at GaN/AlGaN heterointerface."
Applied physics express 3, no. 12, art no. 121004, Dec. 2010. DOI:
10.1143/APEX.3.121004

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