21-07-2017

SYLLABUS
Computer Organization
(Autonomous) • Input-Output Organization: Peripheral Devices – ASCII Alphanumeric Characters,
Input-Output Interface – I/O Bus and Interface Modules, I/O vs Memory Bus, Isolated
vs Memory Mapped I/O, Example of I/O Interface, Asynchronous data transfer – Strobe
UNIT V
Control, Handshaking, Asynchronous Serial Transfer, Modes of Transfer – Example of
Sections - A & D Programmed I/O, Interrupt Initiated I/O, Priority Interrupts – Daisy Chaining Priority,
Parallel Priority Interrupt, Priority Encoder, Interrupt Cycle, Direct memory Access –
DMA Controller, DMA Transfer.

Prepared by
Anil Kumar Prathipati, Asst. Prof., Dept. of CSE.

11-4

INDEX
 Peripheral Devices  11-1 Peripheral Devices
 I/O Subsystem
 Input Output Interface
 Provides an efficient mode of communication between the central system and the outside environment
 Asynchronous Data Transfer  Peripheral (or I/O Device)

 Modes of Transfer  Input or Output devices attached to the computer

» Monitor (Visual Output Device) : CRT, LCD
 Priority Interrupts » KBD (Input Device) : light pen, mouse, touch screen, joy stick, digitizer
» Printer (Hard Copy Device) : Dot matrix (impact), thermal, ink jet, laser (non-impact)
 Direct Memory Access » Storage Device : Magnetic tape, magnetic disk, optical disk
 ASCII (American Standard Code for Information Interchange) Alphanumeric Characters
 I/O communications are usually involved in the transfer of ASCII information
 ASCII Code :
» 7 bit : 00 - 7F ( 0 - 127 )
 80 - FF ( 128 - 255 ) : Greek, Italic, Graphics

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Chap. 11 Input-Output Organization

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11-5 11-6
ASCII CODES

Chap. 11 Input-Output Organization Chap. 11 Input-Output Organization

11-7 11-8

 11-2 Input-Output Interface  I/O command :

 Interface » Control Command
 1) A conversion of signal values may be required » Status Command
 2) A synchronization mechanism may be needed » Input Command
» The data transfer rate of peripherals is usually slower than the transfer rate of the CPU » Output Command
 3) Data codes and formats in peripherals differ from the word format in the CPU and Memory  I/O Bus versus Memory Bus
 4) The operating modes of peripherals are different from each other  Computer buses can be used to communicate with memory and I/O
» Each peripherals must be controlled so as not to disturb the operation of other peripherals connected to the CPU » 1) Use two separate buses, one for memory and the other for I/O
 Interface  I/O Processor

 Special hardware components between the CPU and peripherals

» 2) Use one common bus for both memory and I/O but have separate control lines for each : Isolated I/O or I/O Mapped I/O
 IN, OUT : I/O Instruction
 Supervise and Synchronize all input and output transfers I/O bus  MOV or LD : Memory read/write Instruction
Data
 I/O Bus and Interface Modules : Processor Address

 I/O Bus Control * Control Lines

» Data lines I/O Request, Mem Request, Read/Write
» Address lines » 3) Use one common bus for memory and I/O with common control lines : Memory Mapped I/O
 MOV or LD : I/O and Memory read/write Instruction
» Control lines Interface Interface Interface Interface

 Interface Modules
Keyboard * Control Lines
and Magnetic Magnetic
display
Printer
disk tape
Read/Write
terminal

Chap. 11 Input-Output Organization Chap. 11 Input-Output Organization

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11-9 11-10

 Example of I/O Interface : Fig. 11-2  Strobe : Control signal to indicate the time at which data is being transmitted
I/O data
 4 I/O port : Data port A, Data port B, Control, Status Port A  1) Source-initiated strobe :
Bidirectional register
Bus
 Address Decode : CS, RS1, RS0 data bus buffers  2) Destination-initiated strobe :

 11-3 Asynchronous Data Transfer Data bus Data bus

I/O data
Port B Source Destination Source Destination
 Synchronous Data Transfer Chip select register
unit Strobe unit unit Strobe unit
CS
 All data transfers occur simultaneously during the occurrence of a RS
Register select 1
clock pulse RS
Timing
(a) Block diagram (a) Block diagram
0 Control Control
and
 Registers in the interface share a common clock with CPU registers I/O read Control register
RD
 

Internal bus
 Asynchronous Data Transfer
I/O write
 Internal timing in each unit (CPU and Interface) is independent WR Valid data Valid data
Status
Data Data
Status
 Each unit uses its own private clock for internal registers register

To CPU To I/O device

 
CS RS RS Register selected
1 0
0 × × None : data bus in high-impedance Strobe Strobe
1 0 0 Port A register
(b) Timing diagram (b) Timing diagram
1 0 1 Port B register
1 1 0 Control register Fig. 11-3 Source-initiated strobe Fig. 11-4 Destination-initiated strobe
1 1 1 Status register
 Disadvantage of strobe method

Chap. 11 Input-Output Organization Chap. 11 Input-Output Organization

11-11 11-12

 Handshake : Agreement between two independent units  Asynchronous Serial Transfer

Data bus Data bus  Synchronous transmission :
Source
unit
Data valid Destination
unit
Source
unit
Data valid Destination
unit
» The two unit share a common clock frequency
Data accepted Ready for data
» Bits are transmitted continuously at the rate dictated by the clock pulses
(a) Block diagram
(a) Block diagram
 Asynchronous transmission :
» Special bits are inserted at both ends of the character code
Valid data
Data

 Ready for data


» Each character consists of three parts :
 1) start bit : always “0”, indicate the beginning of a character

 
Data valid
Data valid
 2) character bits : data
 3) stop bit : always “1”
Data accepted
 Data bus  Valid data
 Asynchronous transmission rules :
(b) Timing diagram
(b) Timing diagram
»  When a character is not being sent, the line is kept in the 1-state
Source unit Destination unit »  The initiation of a character transmission is detected from the start bit, which is always “0”
Source unit Destination unit
Place data on bus
Enable data valid. Accept data from bus Ready to accept
»  The character bits always follow the start bit
Enable data accepted
Place data on bus
data.
Enable ready for data »  After the last bit of the character is transmitted, a stop bit is detected when the line returns to the 1-state for at least one
Enable data valid.
bit time
Disable data valid
Invalidate data on bus Disable data accepted Accept data from bus
Ready to accept data Disable reday for data
   
Disable data valid
(initial state) Invalidate data on bus
(initial state)
(c) Sequence of events
(c) Sequence of events
1 1 0 0 0 1 0 1
Fig. 11-5 Source-initiated handshake Fig. 11-6 Destination-initiated handshake
Start Stop
 Timeout bit
Character bits
bit

Chap. 11 Input-Output Organization Chap. 11 Input-Output Organization

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11-13 11-14

 Baud Rate : Data transfer rate in bits per second  11-4 Modes of Transfer
» 10 character per second with 11 bit format = 110 bit per second
 Data transfer to and from peripherals Read status register
 UART (Universal Asynchronous Receiver Transmitter) : 8250
 1) Programmed I/O : in this section
 UART (Universal Synchronous/Asynchronous Receiver Transmitter) : 8251
 2) Interrupt-initiated I/O : in this section and sec. 11-5 Check flag bit

 Asynchronous Communication Interface : Transmit

 3) Direct Memory Access (DMA) : sec. 11-6
Transmitter Shift data
» 80 : Data Write/Read (Transmit/Receive) Bidirectional Bus
register register
= 0
data bus buffers  4) I/O Processor (IOP) : sec. 11-7 Flag
» 81 : Control Write/ Status Read
 A0 = RS (register select) Transmitter
Transmitter
clock
 Example of Programmed I/O : Fig. 11-10, 11-11 = 1
Control
control
Chip select register Read data register
 Double Buffered (in transmit register) CS and clock

Internal bus
Data bus Interface I/O bus
» New character can be loaded as soon as Register select
RS Receiver
Timing Receiver
Transfer data to memory
Status clock
the previous one starts transmission I/O read
and
Control register
control
Address bus Data register
RD and clock

 3 possible errors (in status register) CPU

Data valid I/O
device
I/O write I/O read Operation no
WR
» 1) parity error Receiver Shift
Receiver
data
complete ?
register register Status
 Even or Odd parity error I/O write F
register Data accepted yes
» 2) framing error Continue
 right number of stop bits is not detected CS RS Operation Register selected
F = Flag bit
with
program
0 × × None : data bus in high-impedance
at the end of the received character
1 0 WR Transmitter register
1 1 WR Control register
 Interrupt-initiated I/O
» 3) overrun error 1 0 RD Receiver register
1 1 RD Status register  1) Non-vectored : fixed branch address
 CPU does not read the character from  2) Vectored : interrupt source supplies the branch address (interrupt vector)
the receiver register before the next one is available
Chap. 11 Input-Output Organization Chap. 11 Input-Output Organization

11-15 11-16

 Software Considerations  Polling

 I/O routines  Identify the highest-priority source by software means
» software routines for controlling peripherals and for transfer of data between the processor and peripherals » One common branch address is used for all interrupts
 I/O routines for standard peripherals are provided by the manufacturer (Device driver, OS or BIOS) » Program polls the interrupt sources in sequence
 I/O routines are usually included within the operating system » The highest-priority source is tested first
 I/O routines are usually available as operating system procedures ( OS or BIOS function call)  Polling priority interrupt If there are many interrupt sources, the time required to poll them can exceed the time
available to service the I/O device
 11-5 Priority Interrupt » Hardware priority interrupt
 Priority Interrupt Daisy-Chaining : Fig. 11-12
 Identify the source of the interrupt when several sources will request service simultaneously
 Determine which condition is to be serviced first when two or more requests arrive simultaneously Processor data bus

» 1) Software : Polling VAD 1 VAD 2 VAD 3

» 2) Hardware : Daisy chain, Parallel priority

Device 2
“1” Device 1
PI PO
“1” Device 2
PI PO
“0” Device 3
PI PO
To next
Device
Interrupt Request

Interrupt request
INT
CPU
Interrupt acknowledge
INTACK

Chap. 11 Input-Output Organization Chap. 11 Input-Output Organization

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11-17 11-18

 Parallel Priority  11-6 Direct Memory Access (DMA)

Interrupt
 Priority Encoder – register  DMA
VAD
 Parallel Priority : Fig. 11-14 disk 0 to CPU  DMA controller takes over the buses to manage the transfer directly between the I/O device and memory (Bus
I0
» Interrupt Enable F/F (IEN) : set or cleared by the program y
Request/Grant)
x
» Interrupt Status F/F (IST) : set or cleared by the encoder output Printer 1
I1
Priority 0
 Priority Encoder Truth Table : Tab. 11-2 encoder
0
Reade 2
I2
r 0 DBUS Address bus
0
 Interrupt Cycle Keyboard 3
I3
0
BR BR
ABUS Data bus
High-impedance
DMA Bus request (disable)
 At the end of each instruction cycle, CPU checks IEN and IST 0 CPU when BG is
Controller
RD Read
 if both IEN and IST equal to “1” Enable
enabled
BG BG
IEN IST
 CPU goes to an Instruction Cycle Bus grant WR Write
» Sequence of microoperation during Instruction Cycle
0

Interrupt
1 to CPU

SP  SP  1 : Decrement stack point

2 INTACK
M [ SP ]  PC : Push PC into stack
Branch to ISR from CPU
INTACK  1 : Enable INTACK 3
PC  VAD : Transfer VAD to PC
Mask
IEN  0 : Disable further interrupts register

Go to Fetch next instructio n

Chap. 11 Input-Output Organization Chap. 11 Input-Output Organization

11-19 11-20

 Transfer Modes  DMA Transfer ( I/O to Memory)

 1) Burst transfer : Block  1) I/O Device sends a DMA request
Interrupt
 2) Cycle stealing transfer : Byte  2) DMAC activates the BR line
BG Random access
CPU
 DMA Controller ( Intel 8237 DMAC ) : Fig. 11-17  3) CPU responds with BG line BR
memory (RAM)

 DMA Initialization Process Address bus  4) DMAC sends a DMA acknowledge

RD WR Address Data RD WR Address Data
» 1) Set Address register : to the I/O device Read control
 memory address for read/write
 5) I/O device puts a word in the data Write control
» 2) Set Word count register : Data bus Address bus
Data bus Data bus
buffers buffers bus (for memory write)
 the number of words to transfer Address bus
» 3) Set transfer mode :  6) DMAC write a data to the address

 read/write, specified by Address register

Internal bus

Address
 burst/cycle stealing, DMA select CS Address register  7) Decrement Word count register select
 I/O to I/O,
Register select RS  8) Word count register
 I/O to Memory,
Read RD Word count register RD WR Address Data
 Memory to Memory EOT interrupt CPU DMA acknowledge
DS
 Memory search Write WR
Control  9) Word count register RS Direct memory I/O
 I/O search Bus request BR logic Control register access (DAM) Peripheral
DMAC checks the DMA request from BR controller device
» 4) DMA transfer start : next section Bus grant BG BG
DMA request

» 5) EOT (End of Transfer) : Interrupt Interrupt

DMA request I/O device Interrupt

 Interrupt to I/O device

DMA Acknowledge

Chap. 11 Input-Output Organization Chap. 11 Input-Output Organization