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2 FEBRUARY 2000
1
In the past, low power consumption usually was less and charge conservation of the MOSFETs has infinite
critically considered among key design specifications. order of continuity for all operation regions. In addi-
But today, both increased circuit density of current fine- tion to its computer-implemented version [9], it is also
line CMOS technology and battery-operated portable extremely useful for analog circuit design by hand cal-
equipment necessitate low voltage low power system culations. The details of this model are beyond the
design. For CMOS analog circuits, when the transis- scope of this paper. What we are interested in here is
tors operate in weak inversion region, gm /ID reaches how it can be used to optimize the circuit performance
the maximum, hence the minimum power consumption in terms of power consumption and speed. A useful set
can be achieved due to the small quiescent current at of design equations for a saturated MOSFET using this
the expense of large silicon area and slow speed. When model is given by:
MOS transistors operate in strong inversion, however,
φt ngm 2
although good frequency response and small area are = (1a)
obtained, non-optimum larger power is consumed, and ID 1 + 1 + if
VDS(sat) is high. For most analog circuits, the best ID
tradeoff among area, power and speed can be achieved if = (1b)
IS
when the transistors work in moderate inversion region φ2 W
[3]. But conventional MOS transistor models provide IS = µnCox t (1c)
2 L
different sets of equations for weak and strong inver-
∼ µφt
sion regions [6], even in computer simulation tools [7]. fT = 2
2( 1 + if − 1) (1d)
Although some complex bridging equations are used in 2πL
VDS(sat) ∼
the intermediate region, large errors or discontinuities = ( 1 + if − 1) + 4 (1e)
of the transistor small signal parameters are often un- φt
avoidable. Moreover, it is impossible for circuit design- W gm 1
= (1f)
ers to predict circuit performance in moderate inversion L µCox φt 1 + if − 1
with simple hand calculations. Most designers often as-
sume conservative ways to make the MOS transistors where, ID — the drain current of the MOS transis-
work in strong inversion, with power consumption and tor, gm — the transconductance in saturation, n — the
speed higher than needed, thus avoiding an optimal de- slope factor, φt — thermal voltage, and if = ID /IS —
sign. In recent years, some attempts of MOS modeling the inversion level of the MOS transistor.
have been made to have one-equation model for all the MOS transistors work in weak inversion for if < 1,
operation regions [1, Chapter 2] [2], [8]. strong inversion for if > 100, in between is the mod-
A current based model with one-equation for all erate inversion. Small if requires large aspect ratio
regions including weak, moderate, and strong inversion W/L and area, and large if means small area and high
with good accuracy was proposed in [1, Chapter 2], [2], speed but large current and power consumption [2], as
which has been successfully applied in low power ana- depicted in Fig. 1 for different tradeoffs between area,
log circuit design [1]–[3]. This physically based model fT and power consumption. A general expression for
which preserves the structural source-drain symmetry VGS , if the MOSFET is saturated and VSB = 0, can be
YAN and SANCHEZ-SINENCIO: LOW VOLTAGE ANALOG CIRCUIT DESIGN TECHNIQUES: A TUTORIAL
3
written as
VB1 M4
VGS = VT + nφt [ 1 + if − 2 + ln( 1 + if − 1)] (1g) VB M2
VB2 M3
Eq. (1g) shows that, for strong inversion, VGS Vx IL Vx IL
reduces
to the well-known approximation (VT + RL RL
VB3 M2
2nID /[µCox (W/L)]. For deep weak inversion VGS Mc Ms
becomes (VT + nφt [ln(if /2)− 1]). Note that for a MOS- vIN M1 M1
vIN
FET working in strong inversion, VGS = VT + a few
hundred of mV; for weak inversion, VGS is below VT ,
typically by some tens of mV; and in moderate inver- (a) (b)
times larger than the GBW or the highest frequency at Power Supply Voltage
(N) well CMOS process, only N (P) channel bulk-driven Metal Poly II
CFGD
Poly I
MOSFETs are available. This may limit its applica- VG1 CG1
VG1 VG1
tions. iii) The equivalent input referred noise of a bulk- VG2 VG2 CG2
driven MOS amplifier is larger than a conventional gate- VG2
VG3
CGn
driven MOS amplifier because of its smaller transcon- VGn VGn
ductance. iv) Prone to turn on the parasitic bipolar S
CFGS
D
transistors, which may result in a latch-up problem. (b) Schematic Symbol
CFGB
N Diffusion
(c) Equivalent Circuit
(a) Layout
3.3 Floating-Gate MOSFETs
Fig. 4 Multi-input floating-gate MOSFET, (a) layout, (b)
Another technique to reduce the supply requirement schematic symbol, (c) equivalent circuit
of low voltage analog circuit is the floating-gate tech-
nique. Floating-gate MOS transistors have been used
in digital EPROM or EEPROM for decades, but they vD
are not so widely used in analog circuits. A number of
papers have been published for applications of floating- vG M2
gate technique in analog circuits, such as floating-gate
CMOS analog trimming circuit [22], neural network M1
components, multipliers [23], D/A converters[24] and
vS
amplifiers [25]–[27].
Fig. 5 Self-cascode MOSFET
The layout and circuit symbol of a multi-input
floating-gate MOSFET is depicted in Fig. 4. The
floating-gate MOSFET is similar to a conventional
MOSFET in the sense that the floating-gate is equiv- away. Programming using hot-electron injection can
alent to the gate of a conventional transistor, except be easily controlled, but need a large current. FN tun-
that the voltage of floating-gate VF G is not controlled neling requires small current, however, a high voltage
directly but by the control gates through capacitance from 14 to 30V, depending primarily on the oxide thick-
coupling. The floating-gate voltage can be expressed ness of the process, is required. By these programming
as techniques, we can change the equivalent VT seen from
the control gates to have a low VT MOSFET, but the
VF G = (QF G + CF G,D VD + CF G,S VS + CF G,B VB relatively complex programming circuits and/or higher
n
programming voltage limit its low voltage applications.
+ CGi VGi )/CΣ (2) Note that for MOSFETs with the same aspect
i=1
ratio and bias drain current, bulk-driven and multi-
where QF G is the static charge on the floating-gate, and input floating-gate transistors have the same drain cur-
n
rent noise [28] as the conventional MOSFETs, however,
CΣ = CF G,D + CF G,S + CF G,B + CGi is the total
smaller equivalent transconductance of the former two
i=1
capacitance seen at the floating-gate. results in a higher input referred noise voltage.
The drain current ID v.s. VGS characteristic is sim-
ilar to that of conventional MOSFET if we treat VF G,S 3.4 Self-Cascode MOSFETs
of the floating-gate MOSFET as VGS of a conventional
MOSFET. Note that because VF G is dependent on VD Self-cascode configuration [29] shown in Fig. 5 provides
due to the parasitic CF G,D , the output impedance is a high output impedance with larger voltage headroom
considerably degraded and is lower than that of the than the conventional cascode structures. The lower
conventional MOSFET [1]. (upper) transistor M1 (M2) operates in non-saturation
An exciting property of floating-gate MOSFET is (saturation) region. For (W/L)2 >> (W/L)1 , the cir-
that the electric isolation from the floating-gate to other cuit behaves like a single M1 operating in saturation
nodes is so ideal that the electric charge can stay there region but without severe channel-length modulation
for several years with the variation of less than 2% in effects. The output resistance is roughly proportional
room temperature [1, Chapter 5]. We can change the to (W/L)2 /(W/L)1 and VDS(sat) = VGS − VT the same
equivalent threshold voltage seen from the control gates as in a single MOSFET. Note that it is not necessary
by varying the amount of static charge on the floating- to have different VT 1 and VT 2 for the circuit to operate
gate. The static charge QF G can be changed in three properly. However, it could help to improve the output
ways[1, Chapter 5]: 1) ultra-violet light shining, 2) hot- impedance [30], [31] to have VT 1 > VT 2 .
electron injection, and 3) Fowler-Nordheim (FN) tun- A number of excellent discussions from various as-
neling. In ultra-violet light, the Si O2 layer becomes pects on low voltage low power analog and mixed-signal
temporarily conductive, and the static charge can leak circuit and system design could be found in [1], [32].
IEICE TRANS. ANALOG INTEGRATED CIRCUITS AND SYSTEMS, VOL. E00–A, NO. 2 FEBRUARY 2000
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Table 3 Summary of some constant gm techniques for N-P complementary input stage
Principle ∆gm † Slew Rate Comments
1 keep IN + IP constant [43], [44] 6% for weak inver- Constant Work well in weak inversion, not suitable
sion, 40% for strong for high speed application
inversion
√ √ √
2 keep
IP + IN [45], [46] About 10% 2 times Depends on quadratic characteristic of
or KP,N ( W ) I + K ( W
) I measured[47]. variation MOSFETs, which is not accurately fol-
L N N P,P L P P
lowed by short channel transistors, and
[47] constant also has some error introduced by weak
inversion operation in takeover.
3 4 times IN or IP when only one pair +15% systematic vari- 2 times 1) Same with case 2, but we can change 4
operates [45] ation at the 2 takeover variation to other numbers for short channel tran-
regions sistors. 2) +15% systematic gm variation.
4 Back up pair with current switches [48] +20% systematic vari- Constant Constant slew rate but +20% systematic
or 6-pair structure [49] ation at the 2 takeover gm variation.
regions
5 Maximum/minimum current selection 5% (strong in- Constant Small gm variation (for strong inversion)
[50] version) and 20% (weak and constant slew rate.
inversion)
6 Electronic zener [51] 8% Constant Same with case 2.
7 Level shift [52] ±4% after tuning, 13% Constant gm variation is sensitive to VT and supply
before tuning voltage changes.
Mb3
Mb4 Vdd ing. Constant transconductance (gm ) rail-to-rail input
VDS(sat),Mb4 stage is necessary to have an optimized frequency com-
To subsequent stages
Current Summation
operates
pairs operates
mally Vio variation could be several mV even when very
2 70
gm P
careful circuit design and layout have been performed.
gm N
-Vss Vdd 0 60 Assuming the input offset voltage variation is as low as
Vio
Common Mode Input Voltage ( v I,CM )
2mV, and signal amplitude is 2.8Vp-p, the THD caused
-1.0 -0.5 0 0.5 1.0 VI,CM(V)
(c) (e) by the Vio variation could be as high as about -54dB,
which is not sufficient for some high precision applica-
Fig. 9 N-P complementary CMOS rail-to-rail input stage, (a) tions. The direct consequence caused by CM dependent
basic configuration, (b) CM swings of N and P pairs (CM RP and Vio is the degraded CMRR, especially at the takeover
CM RN ), (c) gmT variations with input CM voltage, (d) the ef-
region between N and P input pairs (Fig. 9(e)). A tech-
fect of CM dependent input offset voltage, (e) Vi,cm and CMRR
v.s. VI,CM of (d). nique to minimize the CMRR degradation is by reduc-
ing the variation slope of the input offset voltage with
the input CM level [53]. This can be achieved by mak-
the CM swing, both of N and P pairs operate, ren- ing the takeover region as large as possible. However,
dering a total transconductance (gmT ) which is about this is limited by the available headroom voltage which
twice of that when the CM voltage is close to either becomes a serious problem for LV applications.
of the supply rails and only the P or N pair is operat- For very low voltage supply (say 1.5V), to main-
YAN and SANCHEZ-SINENCIO: LOW VOLTAGE ANALOG CIRCUIT DESIGN TECHNIQUES: A TUTORIAL
9
Io+ VB Io-
VB
Io+ Io- Io+ Io- strong inversion), the minimum voltage supply is given
VB
C2 C2'
Vi+ Vi- Vi+ Vi- Vi- 0.7
M1 M2 VSUP,min = (V )
C1
ViFG+ ViFG- C ' Vi+
1
M1 M2
1 − kin
IB IB IB
(a) (b) (c) Unfortunately, altering VQ often requires complicated
circuits and/or high programming voltages [1, Chapter
Fig. 10 Floating-gate and bulk-driven MOS input stages, (a) 5].
floating-gate MOS input stage, (b) equivalent circuit of (a), (c) Low voltage rail-to-rail CM input swing can also be
bulk-driven MOS input stage. achieved using bulk-driven differential pair (Fig. 10(c))
[21]. This type of input stage requires very low volt-
tain a rail-to-rail CM input voltage swing is extremely age supply, about (VGS + VDS(sat) ). Its shortcoming is
difficult, because of the VGS requirement of MOSFET, that the transconductance changes dramatically (about
which usually consumes a large portion of the supply 2 times) with the CM input voltage.
voltage. For inverting configuration (single-ended), in- Another technique to realize near rail-to-rail CM
put CM swing is nearly zero. Although the input CM input swing is using resistive dynamic level shift [54],
voltage need to be close to VDD (for N input pair) or [55], as depicted in Fig. 11. When supply voltage drops
VSS (for P input pair) to make the input stage oper- to below (2VT + 4VDS(sat) ), the N-P complementary in-
ate in very low voltage environment, it is not a severe put stage (Fig. 9(a)) does not provide a rail-to-rail CM
problem as judicious voltage shifter [42] in the input input range, as illustrated in Fig. 11(a). The problem
stage can be devised, especially for sampled data cir- can be solved if four level shifters are inserted between
cuits [15], [16]. For non-inverting configuration, espe- the direct inputs and the gates of the input stage tran-
cially for voltage buffer, wide CM input swing is neces- sistors Fig. 11(b). Because active components cease to
sary. operate under small voltage headroom, we have to re-
Floating-gate MOSFET differential pair can be sort to passive components, i.e. resistors, to realize the
used to obtain a rail-to-rail input CM range [27], as level shifters. The bipolar version of this concept was
illustrated in Fig. 10(a) with the equivalent circuit in proposed in [54], and a 1-V near rail-to-rail input and
Fig. 10(b). VB can be directly wired to VDD for simplic- output bipolar Op Amp was successfully implemented.
ity and the widest CM range. The rail-to-rail input CM Without level shift, the minimum supply voltage for
range is intrinsically obtained by attenuating the input a bipolar N-P complementary input stage to render a
voltage. Define kin as kin = C1 /CΣ (Fig. 10(b)), the rail-to-rail input CM range is about 1.5V. Thanks to
input voltage attenuation factor. Where C1 is the ca- the dynamic level shift, the amplifier [54] could still op-
pacitance of the input control gate, and CΣ is the total erate with near rail-to-rail CM input range when the
capacitance seen from the floating-gate. Note that supply voltage reaches 1V. As illustrated in Fig. 11(c),
√ the
input referred noise is increased by the factor of 1/ kin , the input voltage is applied to the P and N differential
compared with that of non-attenuated conventional dif- pairs through voltage level shift resistors RL1 ∼ RL4 .
ferential pair, assuming the same gm is achieved. With The level shift currents, as well as the level shift volt-
floating-gate static electric charge QF G and VB = VDD , ages (VSHIF T ), which are shaped through a feedback
to obtain an rail-to-rail swing, we need to satisfy network (not in the figure), change with the CM input
voltage, as shown in Fig. 11(d). Fig. 11(d) also illus-
VF GS,M1 − QF G /CΣ + VDS(sat),IB
VSUP >
=
trates the curves of the base voltages of the input tran-
1 − kin sistors v.s. CM input voltage vICM . The input stage
VT − VQ + VDS(sat),M1 + VDS(sat),IB has a constant gm over the whole CM range by con-
= (3)
1 − kin trolling the tail currents of the NPN and PNP input
for VQ < VT − VSUP,D pairs to have a constant total current. When vICM is
close to the positive (negative) supply, N (P) pair op-
where VQ = QF G /CΣ , which is the equivalent voltage erates with VSHIF T = 0, when vICM shifts towards the
shift introduced by QF G , and VSUP,D is the voltage central part of the supply voltage, the level shift cur-
drop between VDD to the drains of the M1 and M2. rents as well as VSHIF T start to increase, rendering a
The lower supply voltage rail-to-rail operation requires relatively constant CM voltage at the N (P) pair bases
a smaller attenuation factor kin . By altering VQ , the which keeps the N (P) pair operative. VSHIF T comes
circuit may yield a better low voltage performance. If to its maximum, when vICM reaches the central point
VQ = VT − VSUP,D , we can obtain of the supply voltage.
VSUP,D + VDS(sat),M1 + VDS(sat),IB A 1-V rail-to-rail input Op Amp of CMOS version
VSUP >
= (Fig. 11(e)) was implemented by Duque-Carrillo et al
1 − kin
[55] following the idea of [54]. The working principle
Usually, VSUP,D is around 0.2 to 0.4V if folded-cascode of the level shift current generator is illustrated in Fig.
structure is used. Assuming all VDS(sat) ’s are 0.2V (for 11(f). The level shift current v.s. vICM characteristic is
IEICE TRANS. ANALOG INTEGRATED CIRCUITS AND SYSTEMS, VOL. E00–A, NO. 2 FEBRUARY 2000
10
VCMR,N
VDS(sat),Mb4 IL1 IL2 ML2 ML3 M11
R10 R11
CM voltage
IL M1 M10
VGS,M1,2 Dead zone, neither M12
Q1 VB2
To next stage
VGS,M3,4 N pair nor P pair V1 Q2 V3 Q RL1 RL2
To next stage
M2
Level-Shift Current
10
operates RL1 RL2
VCMR,P
Generator
VGS,M3,4
vI+ vI- RL3 RL4
-Vss -Vss -Vss P pair operates RL3 RL4
(a) P Pair N Pair
Q3 Q8 Q9 M4 M6 M8
V2 Q4 V4 ML5 M3
M1 ML7 M7
V1 M2 V3 IL3 IL4 ML6 ML8 M5
vSHIFT R8 R9 -Vss
vSHIFT
vI+ vI- (c) (e) N-P complementary input stage Current summation
vSHIFT with dynamic level shift
vSHIFT N-P complementary input stage Current summation
V2 with dynamic level shift
M4 V4 Vdd
(b) M3 IMAX ML1 ML4
To next stage
ML2 ML3
IB IN
IL RL1
vI+ vI-
IL=IMAX -(IP+IN)
ITAIL IB IB
1.0
Level-Shift Current
vI+ M14
V 1 ~V 4 and M12
M13 IL vI+ vI-
Generator
V SHIFT (V) M1 M2 M6 M8
0.8 vI- M11
IB ML5
IP
V 1 and V 3
V I,CM
(f) ML6 ML7
ML8 M5
M7
0.6 -Vss
IL=IMAX -(IP+IN)
IN
(h) IL
IP
0.4 V 2 and V 4
0.2
V SHIFT V I,CM (V)
(i)
VI,CM (V)
0.2 0.4 0.6 0.8 1.0 0.2 0.4 0.6 0.8 1.0 V I,CM (V)
(d) (g) 0.2 0.4 0.6 0.8 1.0
Fig. 11 Rail-to-rail input stage with dynamic level shift, (a) the N-P complemen-
tary input stage (Fig. 9(a)) has a dead zone in the central part of the CM swing when
VSU P < 2VT + 4VDS(sat) , (b) the problem can be solved by four level shifters, (c) 1-V
bipolar rail-to-rail input stage [54], (d) V1 ∼ V4 and VSHIF T v.s. CM input voltage, (e)
1-V CMOS rail-to-rail N-P complementary input stage [55], (f) the working principle of
level-shift current generator in (e), (g) IP , IN , and IL v.s. vICM , (h) rail-to-rail P-channel
input stage [55], (i) level-shift current v.s. vICM in (h).
shown in Fig. 11(g). The transconductance of this am- A output stage is a good choice. Simple non-cascode
plifier is not constant due to its simple design. Another common-source amplifier can be used, as well as the
Op Amp with a rail-to-rail CMR for a 1-V operation cascode and regulated cascode structures (Fig. 6(b)-
was implemented in the same paper [55] only with a P (d)) to obtain a large voltage gain at the expense of
differential pair. Figs. 11(h) and (i) show the circuit reduced output swing [10]. For other applications, es-
schematic and level-shift current characteristics, respec- pecially when the amplifier needs to drive off chip low
tively. The distortion performance is much better than resistive or high capacitive load, like earphone, class B
in the previous case of Fig. 11(e), as a consequence of or class AB output stage has to be utilized to have a
only using one differential pair, and therefore, no prob- large driving capability, and at the same time, a small
lem with the offset voltage variation exists. However, quiescent current to save power especially in battery op-
the price paid is a more difficult design, high input off- erated equipment. The output stage usually consumes
set current, and low input impedance. The problem of most of the power of the amplifier in such cases. For low
the resistor area is more critical in the approach rep- voltage designs, a rail-to-rail output swing is desirable
resented in Fig. 11(e) compared with Fig. 11(h), 4 re- to efficiently utilize the power supply voltage.
sistors are used instead of 2. Note that the input CM Common-drain voltage follower output stage (Fig.
range is reduced within the supply rails by the compli- 12(a)) is rarely used in low voltage design due to its
ance voltages of the level current sources, usually, one small output voltage swing as a result of stacking of
VDS(sat) if simple non-cascode structures are used. VGS,P and VGS,N . Instead, we have to use common-
source class AB configurations (Fig. 12(b)). Compared
4.3 Low Voltage Output Stages with the common-drain voltage follower, this kind of
output stage has a higher output impedance, and usu-
ally a higher voltage gain. For Fig. 12(b), some re-
According to the types of loads, the driving capability
quired or preferred characteristics are: i) a large enough
of the output stages differs. For switched capacitor cir-
transconductance to satisfy the stability condition [4];
cuits which have high impedance capacitive loads, class
YAN and SANCHEZ-SINENCIO: LOW VOLTAGE ANALOG CIRCUIT DESIGN TECHNIQUES: A TUTORIAL
11
IP, IN , Vdd
V B =|V GSP |+V GSN Vdd IP Mb M3 M4 Vdd
and |I O | IB M3 IB
Vdd v I,P IN
Mp i I1 Mp
v I,N Mn |I O |
IP IO to i I1
VB v O |I O |
vO IN M4 M5
v I,P I MIN vO
Mp v I,N I Q quiescent current IB
Mn to i I2
-Vss -Vss
(a) (b) (c) V IN M2 M6
vI
i I2
Mn
Fig. 12 Class AB output stage, (a) common-drain voltage M1 M2 -Vss
M1 IB IB
follower (can not be used in low voltage amplifiers), (b) common- -Vss (b)
source structure which features a rail-to-rail swing, (c) ideal (a)
input-output transfer characteristic for class AB output stage. MbA M3A M4A Vdd
Mb M3 M4 Mp1 Vdd
Mp
ii) small quiescent current IQ and large output current V BP
M4A V BP 1: m
MbB Mp2
when driving heavy load (i.e. small resistance or large M3A to i I1 A vO
IB
capacitance) to fully utilize the power from the volt- IB B
age supply; iii) rail-to-rail output swing as discussed M1B to i I2 V BN
Mn2
1: m
vI
before; iv) the output stage should have a fast switch- V BN
M2B Mn
ing speed or a small switching delay between the N and vI
M1 M2 Mn1 -Vss
P transistors, in order to minimize crossover distortion (d)
(c)
at high frequencies. The switching delay is introduced M1A M2A -Vss
gmf2 Av,DM,cl = = 2
=
vi+ − vi− Av,DM,ol R1R+R
1
2
+ 1 R1
gmf1 (e) (7)
v' O- g mf1D
A CMFB v O-
v i+ v o+ g mf2
Fully v I+ V REF CM Output
(v o+ +v o-)/2
g mf3
Differential Voltage
System Extraction
v i- v o- v I- v O,CM g m1D g m2 g m3 g m4 CL
v O+
(a) CMFB loop v O+ -v I,DM
C m3
Main Amplifier v' O+ C m2
(c) g m1C C m1
R2 v O,CM =(v O+ +v O-)/2
v i+ R1 v o- g mf1C
v' O,CM
A
=(v' O+ +v' O-)/2 v ERR
A CMFB (v O+ +v O- )/2- V REF
v i- R1 v o+ V REF g mf1C V REF
R2 (d)
DM first stage g m1C
(b) v I,DM
C p rp C m1
v O- C m2
(v O+ +v O- )/2 v I,DM C m3
v I+ v O- v O-
V REF V REF g m3 g m4 CL
(v o+ +v o-)/2
Output CM g m1D g m2
Voltage CM first stage
A' CMFB
v O+
v O,CM Extraction -v I,DM C p rp g mf3
v I- v O+
Gain stages shared g mf2 (g)
(e) (f) DM first stage by DM and CM g mf1D
Fig. 16 Fully differential and fully-balanced systems, (a) fully-differential system, (b)
a conceptual fully-differential amplifier, (c) conceptual common-mode feedback (CMFB)
working principle, (d) simplified diagram of CMFB circuit, (e) CMFB implementation prin-
ciple, (f) transform single-ended amplifiers to fully-differential one by simple modification,
(g) an example: a fully-balanced NGCC amplifier.
The output CM voltage is attenuated by (ACMF B + 1), (but with two parallel channels) CMFB amplifier.
where ACMF B is the gain of the CMFB amplifier. Note Motivated by the above analysis, the NGCC am-
that Fig. 16(c) can never be used in a practical design, plifier was extended from single-ended version to fully-
except for one-stage amplifiers. For multi-stage ampli- differential version [63], by copying the input stage of
fiers, because of the CM voltage deviations at the in- the single-ended NGCC amplifier to the CMFB chan-
ternal (high impedance) nodes, the voltage gain stages nel, i.e., we add input transconductor gm1C and gmf 1C
may be saturated or cut off by the CM voltage offset. for the CMFB amplifier. Good symmetry between DM
We have to apply a CM correction signal (current) to and CM channels results, as they have the same NGCC
suitable internal nodes of the amplifier, as shown in Fig. topology. A general design methodology was indepen-
16(e∼f). In this way, all the stages of the amplifier will dently proposed by Czarnul et al [64] to extend single-
be working properly, even if there is a large CM offset ended amplifier to fully-balanced version.
from the first stage of the DM amplifier. To make the CMFB amplifier and the main dif-
Fig. 16(d) indicates that the CM amplifier works ferential amplifier to yield the same frequency response
in unity-gain feedback configuration, the stability of the (i.e., the same GBW), it is imposed that
CM loop must be ensured. The stability condition is gm1
similar to that of the main DM amplifier, as long as gm1D = (9a)
2
the main DM amplifier is unity gain stable. In prac- gmf 1
gmf 1D = (9b)
tice, it is very desirable to achieve similar performance 2
in DM and CM loops. For that reason, both loops and
should share most of the circuitry (Fig. 16(e-f)). How-
ever, care should be taken since the CM loop always gm1C = gm1 (9c)
has some extra poles or zeros introduced by the CM gmf 1C = gmf 1 (9d)
extractor circuitry, especially for high frequency appli- where gm1 and gmf 1 are the first stage transconduc-
cations. Fig. 16(f) shows that except for the first stage, tances of the main and feedforward branches of single-
all other stages are shared by the CM and DM chan- ended NGCC amplifier, as depicted in Fig. 15.
nels. Thus, we just need to copy the input stage from The output CM voltage extractor can be imple-
the fully-differential main amplifier to the single-ended mented via an RC voltage divider for Op Amps, as
YAN and SANCHEZ-SINENCIO: LOW VOLTAGE ANALOG CIRCUIT DESIGN TECHNIQUES: A TUTORIAL
15
Vdd 7. Conclusions
v O+ R R v O- v v O-
O+
M1 M2
R R
C
v O,CM C
A number of topics concerning low voltage analog cir-
(a) cuit design were reviewed. The one-equation MOSFET
C v O,CM C model for all operation regions is an excellent tool to op-
Vdd IB IB
V B,CM =aV O,CM +b timize circuit performance between different tradeoffs,
(b) -Vss
M5 M6
such as power consumption, silicon area and speed, for
i ERR =I 1 -I 2
LV LP analog design. Although there are some perfor-
I1 I1
v O+ v O- v O+ mance degradations for the bulk-driven and floating-
M1 M2 M3 M4
v O- V REF gate MOSFET transistors, they are very useful com-
V REF M1 M2
IB IB ponents in specific LV applications. Self-cascode struc-
IB
-Vss (c) -Vss (d) ture is a viable way to increase the output impedance of
short channel transistors. We also reviewed a number
Fig. 17 Common-mode voltage detector schemes, (a) RC volt- of key building blocks for LV analog circuits. Then, we
age divider, (b) common-drain voltage follower and RC volt- reformulated the NGCC equations for designing LV LP
age divider, (c) balanced double-differential-pair structure, (d) multi-stage amplifiers. Fully differential and balanced
floating-gate common-mode voltage detector.
systems are revisited in the last part of this paper.
Acknowledgment
shown in Fig. 17(a). But it is not suitable for OTAs
because the high output impedance is degraded by the
loading effect of the RC components. Several high in- The authors want to express their sincere thanks to
put impedance CM extractor have been proposed [65] Prof. Takahiro Inoue and his group for the technical,
(Fig. 17(b-c)) at the expense of limited DM and/or CM moral and financial supports for this invited paper.
swing and nonlinearity. In fact, for very low voltage We also wish to thank Drs. Schneider, Galup-Montoro,
applications, the conventional high-output impedance Duque-Carrillo, Çilingiroğlu and Ramírez-Angulo for
CM extractors are not able to operate properly since the their valuable comments and suggestions.
amplifier output signals are not large enough to turn-on
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