16DEC002 Digital design through VERILOG (Elective–I) 3104

Course Outcomes
1. Illustrate the importance of EDA tools and VLSI designs
2. Design and implement the fundamental digital logic circuits using Verilog HDL
3. Explain the system level design and related concepts.
4. Design and Implement the digital designs against timing parameters
5. Apply knowledge of drawing SM charts
6. Create the basic awareness on FPGA and CPLD architectures.
Unit I
Introduction to Verilog, Language Constructs & Conventions and Gate Level Modeling Verilog as
HDL, Levels of Design Description, Concurrency, Simulation and Synthesis, Functional
Verification, System Tasks, Programming Language Interface (PLI), Module, Simulation and
Synthesis Tools, Test Benches. Introduction, Keywords, Identifiers, White Space Characters,
Comments, Numbers, Strings, Logic Values, Strengths, Data Types, Scalars and Vectors,
Parameters, Memory, Operators, System Tasks, Exercises. Introduction, AND Gate Primitive,
Module Structure, Other Gate Primitives, Illustrative Examples, Tri-State Gates, Array of
Instances of Primitives, Additional Examples, Design of Flip flops with Gate Primitives, Delays,
Strengths and Contention Resolution, Net Types, Design of Basic Circuits, Exercises. VLSI Design,
ASIC Design Flow 12+4 Hours
Unit II
Behavioral Modeling, Modeling at Data Flow Level and Switch Level Modeling Introduction,
Operations and Assignments, Functional Bifurcation, Initial Construct, Always Construct,
Examples, Assignments with Delays, Wait construct, Multiple Always Blocks, Designs at
Behavioral Level, Blocking and Non blocking Assignments, The case statement, Simulation Flow.
iƒ and iƒ-else constructs, assign-deassign construct, repeat construct, for loop, the disable
construct, while loop, forever loop, parallel blocks, force-release construct, Event. Introduction,
Continuous Assignment Structures, Delays and Continuous Assignments, Assignment to Vectors,
Operators. Introduction, Basic Transistor Switches, CMOS Switch, Bi-directional Gates, Time
Delays with Switch Primitives, Instantiations with Strengths and Delays, Strength Contention
with Trireg Nets, Exercises. Fork-Join construct 11+3 Hours
Unit III
System Tasks, Functions, Compiler Directives, Functions & Tasks, User-Defined Primitives and
Digital Design with SM Charts Introduction, Parameters, Path Delays, Module Parameters,
System Tasks and Functions, File-Based Tasks and Functions, Compiler Directives, Hierarchical
Access, General Observations, Exercises, Introduction, Function, Tasks, User- Defined Primitives
(UDP), FSM Design (Moore and Mealy Machines) State Machine Charts, Derivation of SM Charts,
Realization of SM Charts, Implementation of the Dice Game, Alternative realizations for SM
Charts using Microprogramming, Linked State Machines.
Design of Finite State Machines 11+4 Hours
Unit IV
Designing with Programmable Gate Arrays and Complex Programmable Logic Devices, Verilog
Models Xilinx 3000 Series FPGAs, Designing with FPGAs, Using a One-Hot State Assignment,
Altera Complex Programmable Logic Devices (CPLDs), Altera FLEX 10K Series CPLDs. Static
RAM Memory, A simplified 486 Bus Model, Interfacing Memory to a Microprocessor Bus, UART
Design, Design of Microcontroller CPU. Xilinx 4000 Series 11+4 Hours
Total: 45+15 Hours
 16DEC106 HDL Programming Laboratory 0032
Course Outcomes
1. Design and implement the fundamental digital logic circuits using Verilog HDL.
2. Make use of system level design.
3. Create the technology schematics based on the design.
4. Illustrate t design rule checks and timing parameters.
5. Explain the resources consumed by the design on FPGA.
6. Illusrtae the Interconnections during place and route.
List of Experiments
1. Digital Circuits Design (Sub-System Level) Description using Verilog and VHDL.
2. Verification of the Functionality of Designed Circuits using functional Simulator.
3. Timing simulation for critical path time calculation.
4. Synthesis Reports of top-order designed Digital circuits.
5. Place and Route techniques for major FPGA vendors such as Xilinx, Altera and Actel etc.
6. Implementation of Designed Digital Circuits using FPGA and CPLD devices
List of Mini-Projects1
1. Signed and Unsigned Multiplier Design
2. ALU Design
3. MAC Design
Reading Material(s)
1. T.R. Padmanabhan and B. Bala Tripura Sundari, Design through Verilog HDL, WSE, 2004.
2. Stephen. Brown and ZvonkoVranesic, Fundamentals of Logic Design with Verilog, TMH, 2005.
3. Michael D. Ciletti,Advanced Digital Design with Verilog HDL, PHI, 2005.
4. J. Bhaskar, A Verilog Primier, BSP, 2003.