VLSI Lab Mannual

JSS Mahavidyapeetha, Mysuru
JSS Academy of Technical Education

JSS Campus, Dr. Vishnuvardhana Road, Bengaluru-560060
Department of Electronics & Communication Engineering
VLSI-LAB MANUAL
15ECL77
BY
Mrs. SAROJA S BHUSARE, M.Tech. Asst.Prof.
Mrs. ANURADHA M G, M.Tech. Asst.Prof.
Mr. SRIKANTASWAMY S C, BE. Instructor

Command line for Linux.
cd Change Directory
clear Clear terminal screen
date Display or change the date & time
dc Desk Calculator
dir Briefly list directory contents
eject Eject removable media
exit Exit the shell
file Determine file type
logout Exit a login shell
lprint Print a file
lprintd Abort a print job
ls List information about file(s)
lsof List open files
mkdir Create new folder(s)
open Open a file in its default application
pwd Print Working Directory
reboot Reboot the system
rmdir Remove folder(s)
shutdown Shutdown or restart linux
vi Text Editor
who Print all usernames currently logged in
whoami Print the current user id and name
### Comment / Remark
DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 1

Procedure for digital experiments
1.In Linux prompt, type the command

csh
2.Change directory to Cadence_database/
3.type the command source cshrc
4. Change directory to NCO
5. Change directory to rclabs
6. Change directory to Simulation
7.Create a new directory to store all the program using the command
mkdir (name)
9.Change the directory to the new directory created above using the command
cd (name)
10.Open the text editor using the command
vi name.v
vi testbench.v
11.Type the program in the text editor and to save perform the following procedure
i. Press esc key first and then
1.shift : wq! to save and quit
2.shift :q! to quit without saving
12. compile both main program and test bench code using the following command
ncvlog name.v –mess
13. elaborate both main program and test bench code using the following command
ncelab -access +rwc module_name -mess
14.To simulate in Simvision
ncsim -gui testbench_name
15. A new window opens called design browser window. Here select the signal and send to the waveform
window by clicking the icon.
16.A waveform window appears. In the waveform window, in the menu bar click simulation->create force
to give a value to the signal
17.Click run simulation in the waveform window to observe the waveform

EXPERIMENT 1: Inverter
Aim: To Write The Verilog Code For CMOS Inverter And Write The Test-Bench For The Same To
Verify And Observe The Waveform And Synthesize The Code.
Circuit Diagram:
Procedure:
1.In Linux prompt, type the command
csh
2.Change directory to Cadence_database/
3.type the command source cshrc
4. Change directory to NCO
5. Change directory to rclabs
6. Change directory to Simulation
7.Create a new directory to store all the program using the command
mkdir expriments
9.Change the directory to the new directory created above using the command
cd expriments
10.Open the text editor using the command
vi invereter.v
vi invereter_test.v
11.Type the program in the text editor and to save perform the following procedure
i. Press esc key first and then
1.shift : wq! to save and quit

2.shift :q! to quit without saving
14.To simulate in Simvision

ncsim -gui invereter_test
15. A new window opens called design browser window. Here select the signal and send to the waveform
window by clicking the icon.
16.A waveform window appears. In the waveform window, in the menu bar click simulatation->create force
to give a value to the signal
17.Click run simulation in the waveform window to observe the waveform
18. compile both main program and test bench code using the following command
ncvlog invereter.v –mess
[jss4@vlsiclient4 anu]$ ncvlog inverter.v -mess
ncvlog: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems,
Inc.
file: inverter.v
module worklib.inverter
errors: 0, warnings: 0
The compiler places the inverter and inverter_test description in ncvlog.log
jss4@vlsiclient4 anu]$ ncvlog inverter_test.v -mess

ncvlog: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems,
Inc.
file: inverter_test.v
module worklib.inverter_test
errors: 0, warnings: 0
8.Elaborate the inverter and inverter_test design using the command

ncelab -access +rwc inverter –mess
[jss4@vlsiclient4 anu]$ ncelab -access +rwc inverter -mess

ncelab: 05.83-p003: (c) Copyright 1995-2006 Cadence Design
Systems, Inc.
Elaborating the design hierarchy:
Building instance overlay tables: ....................
Done
Loading native compiled code: ....................
Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 1 1
Primitives: 2 2
Scalar wires: 4 -
Writing initial simulation snapshot: worklib.inverter:module

[jss4@vlsiclient4 anu]$ ncelab -access +rwc inverter_test -mess
ncelab: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems,
Inc.
Elaborating the design hierarchy:
Caching library 'worklib' ....... Done
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.inverter_test:module <0x3f310f73>
streams: 2, words: 1105
Loading native compiled code: .................... Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 2 2
Primitives: 2 2
Registers: 1 1
Scalar wires: 4 -
Initial blocks: 1 1
Pseudo assignments: 1 1
Writing initial simulation snapshot:
worklib.inverter_test:module
The elaborator places the inverter testbench description in ncelab.log

11. To simulate the testbench in Simvision
ncsim -gui inverter_test
This opens a new window called design browser window. Here select the signals and send the
signals to waveform window by clicking the waveform icon
12. Click the run icon in the waveform window to view the waveform as shown below

Verilog code of inverter
module inverter (vout,vin);
output vout;
input vin;
supply1 vdd;
supply0 gnd;
pmos (vout,vdd,vin);
nmos (vout,gnd,vin);
endmodule
Verilog code for inverter testbench
module inverter_test;
reg vin;
wire vout;
inverter i1(vout,vin);
initial
begin
vin=1'b0;
#10 vin=1'b1;
#20 vin=1'b0;
#20 vin=1'b1;
#20 $finish;
end
endmodule
Note: Follow the same steps shown above for all the experiments of PART-A

EXPERIMENT 2
Aim: To write the verilog code for buffer and write the test-bench for the same to verify and observe
the waveform and synthesize the code
Circuit Diagram:
Verilog code for basic gates
module buffer(a,f);
input a;
output f;
wire i;
inverter i1 (i,a);
inverter i2( f,i);
endmodule
Verilog code for basic gates testbench
module buffer_test;
reg a;
wire f;
buffer b1(a,f);
initial
begin
a=1'b0;
#10 a=1'b1;
#20 a= 1'b0;
#20 a=1'b1;

#20 $finish;
end
endmodule
Expected waveform

EXPERIMENT 3
Aim: To write the verilog code for transmission gate and write the test-bench for the same to verify
and observe the waveform and synthesize the code
Circuit Diagram:
module tg(ncontrol,pcontrol,in,out);
input ncontrol,pcontrol;
inout in,out;
cmos y(out,in,ncontrol,pcontrol);
endmodule
module tg_test;
reg in,ncontrol,pcontrol;
wire out;
tg i1(out,in,ncontrol,pcontrol);
initial
begin
in=1’b0;
ncontrol=1'b1;
pcontrol=1'b0;
#10 in=1'b1;
#20 in=1'b0;
#20 in=1'b1;
#20 $finish;
end
endmodule
Expected waveform

EXPERIMENT 4
Aim: To write the verilog code for basic gates and writes the test-bench for the same to verify and
observe the waveform and synthesize the code
Circuit Diagram:
Truth table:
module basic ( a,b,andf,orf,xorf,nandf,norf,notf);

input a,b;
output andf,orf,xorf,nandf,norf,notf;
assign andf = a & b;
assign orf = a | b;
assign xorf = a^b;
assign nandf = ~( a & b);
assign norf = ~(a | b);
assign notf = ~a;
endmodule

module basic_test;
reg a,b;
wire andf,orf,xorf,nandf,norf,notf;
basic b1 ( a,b,andf,orf,xorf,nandf,norf,notf);
initial
begin
a=1'b0;
b=1'b0;
#15 b=1'b1;
#15 a=1'b1;
b=1'b0;
#15 a=1'b1;
b=1'b1;
#50 $stop;
end
endmodule
Expected waveform

EXPERIMENT 5
Aim: To write the verilog code for flip-flops and write the test-bench for the same to verify and
observe the waveform and synthesize the code
A. SR-Flip flop
Circuit Diagram:
Truth table:
Verilog code for SR-Flip flop

module srff(clk,s,r,reset,q,qb);
input s,r,clk,reset;
output q,qb;
reg[1:0] sr;
reg q,qb;
always@(posedge clk)
begin
sr={s,r};
if(reset)
begin
q=1'b0;
qb=1'b1;
end
else
case(sr)
2'b00:q=q;
2'b01:q=1'b0;

2'b10:q=1'b1;
2'b11:q=1'bx;
endcase
qb=~q;
end
endmodule
Verilog code for SR-Flip flop testbench
module basic_test;
reg a,b;
wire andf,orf,xorf,nandf,norf,notf;
basic b1 ( a,b,andf,orf,xorf,nandf,norf,notf);
initial
begin
a=1'b0;
b=1'b0;
#15 b=1'b1;
#15 a=1'b1;
b=1'b0;
#15 a=1'b1;
b=1'b1;
#50 $stop;
end
endmodule
Expected waveform
B. D-Flip flop
Circuit Diagram:

Truth table:
Verilog code for D-Flip flop

module dff(clk,d,q,qb);
input clk,d;
output q,qb;
reg q,qb;
begin
q<=d;
qb<=~(d);
end
endmodule
Verilog code for D-Flip flop testbench
module dff_test;
reg clk,d;
wire q,qb;
dff d1(clk,d,q,qb);
initial
begin
clk=1'b0;
end
always
#5 clk = ~clk;
initial
begin

d=1'b0;
#10 d=1'b1;
#20 d=1'b1;
#20 d=1'b0;
#20 $finish;
end
endmodule
Expected waveform
C. JK-Flip flop
Circuit Diagram:

Truth table:
Verilog code for JK-Flip flop

module jkff(clk,j,k,reset,q,qb);
input j,k,clk,reset;
output q,qb;
reg[1:0] jk;
reg q,qb;
begin
jk={j,k};
if(reset)
begin
q=1'b0;
qb=1'b1;
end
else
case(jk)
2'b00:q=q;
2'b01:q=1'b0;
2'b10:q=1'b1;
2'b11:q=~q;
endcase
qb=~q;
end
endmodule
Verilog code for JK-Flip flop testbench
module jkff_test;
reg clk,j,k,reset;
wire q,qb;
jkff d1(clk,j,k,reset,q,qb);
initial
begin
clk=1'b0;
reset=1'b0;
end
always
#5 clk = ~clk;
initial
begin
j=1'b0;
k=1'b0;
reset=1'b1;
j=1'b0;
k=1'b0;
#10 reset=1'b0;
j=1'b0;
k=1'b1;
#5j=1'b0;
#5k=1'b1;
#5 j=1'b1;
#5 k=1'b0;
#5 j=1'b1;
#5 k=1'b1;
#5 reset=1'b1;
#5 reset=1'b0;
#20 $finish;
end
endmodule
Expected waveform

D. T-Flip flop
Circuit Diagram:

Truth table:
Verilog code for T-Flip flop
module tff(clk,t,reset,q,qb);
input t,clk,reset;
output q,qb;
reg q,qb;
begin
if(reset)
begin
q=1'b0;
qb=1'b1;
end
else
if(t==0)
q=q;
else
q=~q;
qb=~q;
end
endmodule
Verilog code for T-Flip flop testbench
module tff_test;
reg clk,t,reset;
wire q,qb;

tff d1(clk,t,reset,q,qb);
initial
begin
clk=1'b0;
reset=1'b0;
end
always
#5 clk = ~clk;
initial
begin
t=1'b0;
#5 reset=1'b1;
#5 reset=1'b0;
#10 t=1'b0;
#20 t=1'b1;
#20 t=1'b0;
#20 $finish;
end
endmodule
Expected waveform

EXPERIMENT 6
Aim: To write the verilog code for serial and parallel adders and write the test-bench for the same to verify
and observe the waveform and synthesize the code
1. Full adder
Circuit Diagram:
Truth table:
Verilog code for Full adder

module fa(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign sum = (a^b) ^cin;
assign cout= ((a & b) | (b & cin) | (cin & a));
endmodule
2. Parallel adder

Circuit Diagram:
Example:
Verilog code for Parallel adder

module parallel_adder(a,b,cin,sum,cout);
input [3:0] a,b;
input cin;
output cout;
output[3:0] sum;
wire [2:0] c;
fa f1 (a[0],b[0],cin,sum[0],c[0]);
fa f2 (a[1],b[1],c[0],sum[1],c[1]);
fa f3 (a[2],b[2],c[1],sum[2],c[2]);
fa f4 (a[3],b[3],c[2],sum[3],cout);
endmodule
Verilog code for Parallel adder testbench

module parallel_test;
reg [3:0] a,b;

reg cin;
wire cout;
wire[3:0] sum;
parallel_adder a1(a,b,cin,sum,cout);
initial
begin
cin=1'b0;
a=4'b0;
b=4'b0;
#5 a=4'd1;
#5 b=4'd1;
#5 a=4'd4;
#5 b=4'd5;
#5 a=4'd7;
#5 b=4'd9;
end
endmodule
Expected waveform
serial adder:
module serial_adder
(clk,rst,pload,adata,bdata,enable,pout);
input clk,rst,pload,enable;
input [7:0]adata,bdata;

output[7:0]pout;
reg shiftrega_lsb,shiftregb_lsb;
reg [7:0]shiftrega,shiftregb,shiftregc;
wire sum,cout;
reg holdc;
always @(posedge clk)
begin
shiftrega=adata;
shiftgerb=bdata;
shiftregc=8’bo;
end
else if(enable)
begin
shiftrega_lsb=shitrega[0]
shiftrega=shiftrega>>1;
shiftrega[7]=shiftrega_lsb;
shiftregb_lsb=shiftregb[a]
shiftregb=shiftregb>>1;
shiftregb[7]=shiftregb_lsb;
end
shiftregc=shiftregc>>1;
shiftregc[7]=sum;
end
assign pout=shiftregc;
f1 s1(shiftrega[0],shiftregb[0],holdc,sum,cout);
always @(posedge clk,rst)
begin
if(rst)
holdc=1’b0;
else if(enable)
holdc=cout;
else
foldc=holdc;
end
endmodule

Test bench
module serial_adder_test;
reg clk,rst,pload,enable;
reg [7:0]adata,bdata;
wire [7:0]pout;
serial_adder s1(clk,rst,pload,adata,bdata,enable,pout);
initial
begin
clk=1’b0;
rst-1’b0;
pload=1’b0;
#10 rst=1’b0;
pload=1’b1;
#5 adata=8’b00000001;
bdata=8’b00000010;
#5 pload=1’b0;
enable=1’b1;
#200 $stop;
end
always
#5 clk=~clk;
endmodule
Waveform:

EXPERIMENT 7
Aim: To write the verilog code for four bit asynchronous and synchronous counters and write the test-bench
for the same to verify and observe the waveform and synthesize the code
1. Asynchronous Counter
Circuit Diagram:
Verilog code for Asynchronous counter

module async_counter( clk, count );
input clk;
output[3:0] count;
reg[3:0] count;
wire clk;
initial
count = 4'b0;
always @( negedge clk )
count[0] <= ~count[0];
always @( negedge count[0] )
endmodule
Verilog code for Asynchronous counter testbench

module test_count;

reg clk;
wire [3:0]q;
async_counter c1 (clk,q);
initial
begin
clk=1'b1;
#200 $stop;
end
always
#5 clk =~clk;
endmodule
Expected waveform
1. Synchronous counter

Circuit Diagram:
Verilog code for Synchronous Counter

module up_counter_load (
out , // Output of the counter
data , // Parallel load for the counter
load , // Parallel load enable
enable , // Enable counting
clk , // clock input
reset // reset input
);
//----------Output Ports--------------
output [3:0] out;
//------------Input Ports--------------
input [3:0] data;
input load, enable, clk, reset;
//------------Internal Variables--------
reg [3:0] out;
//-------------Code Starts Here-------
always @(posedge clk)
if (reset)
begin
out <= 4'b0 ;
end
else if (load)
begin
out <= data;
end
else if (enable)
begin
out <= out + 1;
end

endmodule
Verilog code for Synchronous counter testbench

module test_count_load;
reg clk;
wire [3:0]out;
reg [3:0]data;
reg load,enable;
reg reset;
up_counter_load c1 (out,data,load,enable,clk,reset);
initial
begin
clk=1'b1;
data=4'b0100;
#250 $stop;
end
always
#5 clk =~clk;
initial
begin
reset=1'b1;
#10 reset =1'b0;
load=1'b1;
#15 load =1'b0;
enable =1'b1;
end
endmodule
Expected waveform

EXPERIMENT 8
Aim: To write the verilog code for successive approximation register and write the test-bench for the same
to verify and observe the waveform and synthesize the code
Verilog code
module approximation (clk,rst,d0,d1,d2,d3);
input clk,rst;
output reg d0,d1,d2,d3;
integer
begin
i=3;
d0=1’b0
d1=1’b0
d2=1’b0
d3=1’b0
end
always @(posedgeclk)
begin
if(i==3)
begin

if(rst==0)
d3=1’b0;
else
d3=1’b1;
i=i-1;
end
else if (i==2)
begin
if(rst==0)
d2=1’b0;
else
d2=1’b1;
i=i-1;
end
else if(i==1)
begin
if(rst==0)
d1=1’b0;
else
d1=1’b1;
i=i-1;
end
else
begin
if(rst==0)
d0=1’b0;
else
d0=1’b1;
i=3;
end
end
endmodule

Testbench
module sar_test;
reg clk.test
Wire d0,d1,d2,d3:
Approximation s1(clk,rst,d0,d1,d2,d3);
Initial
Begin
Clk=1’b0;
Rst=1’b1;
#20 rst=1’b0;
#40 $stop;
End
Always
#5 clk=~clk;
endmodule
OUTPUT WAVEFORM

Procedure for analog experiments
1.In Linux prompt,type the command

csh
2.Change directory to cd Cadence_database
3. type the command source cshrc
4. Change directory to cd Cadence_ms_labs_614
5.In the same terminal window, enter
virtuoso &
6. Keep opened CIW window for the labs
EXPERIMENT 1: Inverter
Aim: Design an Inverter with given specifications, completing the design flow mentioned below:
a. Draw the schematic and verify the following
i) DC Analysis
ii) Transient Analysis
b. Draw the Layout and verify the DRC, ERC
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design
e. Verify & Optimize for Time, Power and Area to the given constraint
Schematic Entry
STEP 1: Creating a new library
 In CIW , execute File-New-Library. The new library form appears as shown below

 In the “New-library” form, type Lab-Experiments in the name section and click OK.
 In the “Technology File for New library” form, select option Attach to an existing techfile and
click OK.
 In the “Attach Design Library to Technology File” form select gpdk180 from the cyclic field and
click OK.
STEP 2: Creating a Schematic cellview
 In CIW , execute File-New-Cellview.

 Setup the create new file form as follows

 Click OK when done the above settings. A blank schematic window for the Inverter design
appears.
STEP 3: Adding Components to schematic
 In the Inverter schematic window, click the Instance fixed menu icon to display the Add
Instance form (or press i)
 Click on the Browse button. This opens up a library browser from which you can select
components and the symbol view.
 After you completer the add instance form, move your cursor to the schematic window and click
left to place a component. The table showing the components for building the inverter schematic
is as shown below.
Library Name Cell Name Properties
gpdk180 pmos For M0: Model name=pmos1, W=2u, L=180n
gpdk180 nmos For M1: Model name=nmos1, W=2u, L=180n
 After entering components, click cancel in the Add Instance from or press Esc with your
cursor in the schematic window
Note: You can use the Edit-Properties-Objects command the properties of component. You can also
move and rotate the components using commands Edit-Move and Edit-Rotate respectively.
STEP 4: Adding Pins to schematic
 Execute Add-Pin or press p. The add pin form appears.

 Type the following in the Add pin form as shown in the table
Pin Names Direction
Vin Input
Vout Output
Vdd Vss InputOutput
 Select cancel form the Add-pin form after placing the pins
STEP 5: Adding Wires to schematic
 Click the Wire(narrow) icon in the schematic or press w or execute Add-Wire(narrow).

 In the schematic window, click on a pin of one of your components as the first point for your
wiring. A diamond shape appears over the starting point of this wire.
 Follow the prompts at the bottom of the design window and click left on the destination point
for your wire. A wire is routed between the source and the destination points.
 Complete the wiring to obtain the schematic as shown below. When done wiring press Esc
key in the schematic window to cancel wiring.

STEP 6: Saving the design
 Click the check and save icon in the schematic editor window
Symbol Creation
STEP 1: Creating a symbol
 In the inverter schematic window execute Design-Create Cellview - From Cellview.

The cellview from cellview form appears as shown below and click ok.
 The symbol generation form appears as shown. Modify the pin specifications and click ok
 A new window displays an automatically created Inverter symbol.
STEP 2: Editing a symbol
 Move the cursor over the automatically generated symbol until the green rectangle is
highlighted and click left to select it.
 Click Delete icon in the symbol window. Similary select the red rectangle and delete that.
 Execute Add-shape-Polygon and draw a shape similar to triangle and press escape.
 Execute Add-shape-Circle at the end of triangle to appear like an inverter symbol.
 Execute Add-Selection Box, click Automatic
 After creating symbol, clik on save icon and execute window-close

Building the Inverter_test Design
STEP 1: Creating a Inverter_test Cellview

 Click OK when done the above settings. A blank schematic window for the Inverter_test design
appears.
STEP 2: Building the inverter_test schematic
Instance form (or press i
 After you complete the add instance form, move your cursor to the schematic window and click
left to place a component. The table showing the components for building the inverter_test
schematic is as shown below.
Lab_Experiments Inverter Symbol
analogLib Vpulse V1=0,v2=1.8,td=0,tr=tf=1ns,ton=10n, T=20n
analogLib Vdc,gnd Vdc=1.8
 After entering components, click cancel in the Add Instance fomm or press Esc with your
 Add the wire and complete the schematic as shown below
 Click check and save
Analog Simulation with Spectre
STEP 1: Starting the simulation environment

 In the Inverter_test schematic window execute Tools-Analog Environment and the window
appears as shown
 From the analog Design environment window, execute Setup-Model Libraries and the setup
form appears as follows
 Use the browse button to select the path ./models/spectre/gpdkstat.scs and click add,apply
and ok.
STEP 2: Choosing Analyses
 In the simulation window execute Analysis-Choose. The choosing analysis form appears as
shown

 To setup transient analysis
 In the Analysis section, select tran
 Set the stop time as 200n
 Click moderate and enable botton and click apply.
 In the Analysis section, select dc
 In the dc analysis section, turn on save DC Operating Point
 Turn on the component parameter
 Double click the select component, which takes you to the schematic window.
 Select input signal Vpulse for dc analysis.
 In the analysis form, select start and stop voltages as 0 to 2 respectively
 Check the enable button and click apply and Ok.

STEP 3: Setting Design Variables
 In the simulation window, click the edit variables icon.

 In the Design variable window, click copy from at the bottom of the form. The design is
scanned and all variables found in the design are listed.
 The wp variable appears and set its value to be 2u as shown

 Click change and ok.
STEP 4: Selecting outputs for plotting
 Execute Outputs-to be plotted – Select on Schematic in the simulation window.

 Click on the output terminal vout and input terminal vin of the inverter and press esc.
STEP 5: Running the simulation
 Execute Simulation-Netlist and run in the simulation window to start the simulation.
 When simulation finishes, the transient, DC plots will automatically will be popped up as shown
STEP 6: Saving the simulator state
 In the simualation window, execute Session-Save State .

 Set the save as field to state1 and click ok.
STEP 7: Loading the simulator state
 From the ADE window execute Session-Load State. Here set the state name to state 1 and click
ok.
Parametric Analysis
 In the simulation window, execute Tools –Parametric Analysis and the form appears as shown

 In the parmetric anaylsis form execute, Setup-Pick Name for Variable – Sweep 1;
 In the selection window, dowuble click left on wp.
 Change the range tye and step control fields in the parametric analysis form as shown below
Range Type From/To From 1u to 10u
Step Control Auto Total Steps 10
 Execute Analysis-Start
 Once the runs are completed, the wavescan window comesup with the plots for different runs as
shown

Creating Layout View of Inverter
STEP 1: Starting the layout editor
 Fron the inverter schematic window menu, execute Tools-Design Synthesis –LayoutXL.(Make
suer that the value of the wp is set to 2u)
 Seclect Create New option. This gives a new cell view form.
 Check the cellname(Inverter),viewname(layout) and tool(Virtuoso) and then click ok. The blank
layout window appears
STEP 2: Adding components to the layout
 Execute Design –Gen From Source in the layout editor window which imports the basic
components into the layout window automatically.
 Press Shift-f to view the geometry of the design
 Re-arrange the components within PR boundary
 To rotate and move the components execute Edit-Properties and Edit-Mpve commands.
STEP 3: Making Interconnection
 Execute connectivity-Show Incomplete Nets in the Layout window

 Click the select all option
 Click ok in the connectivity form, which shows the guidelines for the interconnection of the
components.
 From the layout window, execute Create-Rectange and select the appropriate layers and vias for
making the interconnection

 Execute create-Contact to apply contacts where ever required.
 Save the design by executing Design-Save.
 The Inverter layout is as shown below
Physical Verification
STEP 1: Running Assura DRC
 Select Assura –Run DRC from layout window. The DRC form appears as shown. Select the
technology as gpdk180. This automatically loads the rule file.

Click OK to start DRC.
 When DRC finishes, a dialog box appears, asking you if you want to view your DRC results and then
click yes.
 If there are any DRC error in the design, view layer vindow(VLW) and error layer window(ELW)
apppers.
 Click view –summary in the ELW to find the details of errors.
 If there are no errors in the layout, then an dialog box appears with no DRC errors. Click close.
STEP 2: Running Assura LVS
 Select Assura-Run LVS form the layout window and the window appears as shown.
 Change the following in the form and click ok as shown and the LVS begins

 If the schematic and layout match, a form informs that the LVS completed successfully and asks if
you want to see the results of this run. Click yes in the form.
 If the schematic and layout do not match, a LVS debug form appears and you are directed into LVS
debug environment.
STEP 3: Running Assura RCX
 Select Assura-Run RCX form the layout window and the window appears as shown.
 Change the following in the form and click ok as shown
Fig
 In the filtering tab of the form, enter the power nets as vdd!,vss! And then click ok.
 A form informs that the RCX completed successfully
 You can open av_extracted view form CIW window and view the parasitics.
EXPERIMENT 2a: Common source amplifier
Aim: Design the following circuits with given specifications, completing the design flow mentioned below:

i) DC Analysis
ii) AC Analysis
iii) Transient Analysis
c. Check for LVS
d. Extract RC and back annotate the same and verify the Design.
Schematic Entry

appears.
 In the Common_source schematic window, click the Instance fixed menu icon to display the Add
is as shown below.

gpdk180 Pmos For M0: Model name=pmos1, W=50u, L=1u
gpdk180 Nmos For M1: Model name=nmos1, W=10u, L=1u
 After entering components, click cancel in the Add Instance fom or press Esc with your

Pin Names Direction
Vin Vbias Input
Vout Output
Vdd Vss InputOutput


Symbol Creation
 In the common_source schematic window execute Design-Create Cellview - From

Cellview. The cellview from cellview form appears as shown below and click ok.
 Modify the pin specifications as follows and click ok
 A new window displays an automatically created common_source symbol as shown
below

Building the common_source_test Design
STEP 1: Creating a common_source_test Cellview

 Click OK when done the above settings. A blank schematic window for the Inverter_test design
appears.

STEP 2: Building the inverter_test schematic
left to place a component. The table showing the components for building the inverter_test
Lab_Experiments Common_source Symbol
analogLib Vsin AC Magnitude =1 , DC voltage
=0;Offset=0;Amplitude=5m;Frequency=1K
analogLib Vdc,Vbias,gnd,vss Vdc=vbias=2.5; vss=-2.5

appears as shown
 From the analog Design environment window, execute Setup-Model Libraries
and ok.
 In the simulation window execute Analyses-Choose. The choosing analysis form appears as
shown

 To setup dc analysis
 Select input signal Vsin for dc analysis.
 In the analysis form, select start and stop voltages as -5 to 5 respectively
 Check the enable button and click apply

 To setup ac analysis
 In the analyses section, select ac.
 In the ac analyses section, turn on frequency
 In the sweep range section, select start and stop frequencies as 100 to 100M
 Select points per decade as 20
 Check the enable button and then click apply and ok.




Creating Layout View of Common Source
 Fron the Common_source schematic window menu, execute Tools-Design Synthesis –

LayoutXL
 Check the cellname(Common_source),viewname(layout) and tool(Virtuoso) and then click ok.
The blank layout window appears


components.
 The Inverter layout is as shown below
 Click OK to start DRC.
click yes.
apppers.

 Select Assura-Run LVS form the layout window and the window appears.
debug environment.
 Select Assura-Run RCX form the layout window and the window appears.
You can open av_extracted view form CIW window and view the parasitics.
EXPERIMENT 2b: Common Drain amplifier
i) DC Analysis
ii) AC Analysis
c. Check for LVS
Schematic Entry


appears.
 In the Common_source schematic window, click the Instance fixed menu icon to display the Add
is as shown below.

Pin Names Direction
Vin Vbias Input
Vout Output
Vdd Vss InputOutput


Symbol Creation
 In the common_drain schematic window execute Design-Create Cellview - From

 A new window displays an automatically created common_drain symbol as shown below

Building the common_drain test Design

 Click OK when done the above settings. A blank schematic window for the Common_drain_test
design appears.
STEP 2: Building the common_drain_test schematic

left to place a component. The table showing the components for building the
common_drain_test schematic is as shown below.
Lab_Experiments Common_drain Symbol

appears as shown
and ok.
 In the simulation window execute Analyses-Choose. The choosing analysis form appears.





Creating Layout View of Common Drain
 Fron the Common_source schematic window menu, execute Tools-Design Synthesis –

LayoutXL
 Check the cellname(Common_source),viewname(layout) and tool(Virtuoso) and then click ok.
The blank layout window appears


components.
 The common drain layout is as shown below
click yes.
appears.

debug environment.
EXPERIMENT 2c: Differential Amplifier
i) DC Analysis
ii) AC Analysis
c. Check for LVS
Schematic Entry


appears.
 In the differential_amplifier schematic window, click the Instance fixed menu icon to display the
Add Instance form (or press i)
Differential_amplifier schematic is as shown below.
gpdk180 nmos For M0,M1: Model name=nmos1, W=3u, L=1u
gpdk180 nmos For M2,M3: Model name=nmos1, W=4.5u, L=1u
gpdk180 pmos For M0,M1: Model name=pmos1, W=15u, L=1u

Pin Names Direction
Idc V1 V2 Input
Vout Output
Vdd Vss Vbias InputOutput


Symbol Creation
 In the Differential_amplifier schematic window execute Design-Create Cellview - From

 A new window displays an automatically created Differential_amplifier symbol as shown
below

Building the Differential_amplifier test Design


 Click OK when done the above settings. A blank schematic window for the Common_drain_test
design appears.
STEP 2: Building the Differential_amp_test schematic
differential_amp_test schematic is as shown below.
Lab_Experiment Differntial_amplifie Symbol
s r
=0;Offset=0;Amplitude=5m;Frequency=1
analogLib Idc Dc current=30u

 In the Differential_amp_test schematic window execute Tools-Analog Environment and the

window appears as shown
and ok.






Creating Layout View of Differential Amplifier
 Fron the Differential_amplifier schematic window menu, execute Tools-Design Synthesis –

LayoutXL
 Check the cellname(Differential_amplifier),viewname(layout) and tool(Virtuoso) and then click
ok. The blank layout window appears


components.
 The Differential_amplifier layout is as shown below
click yes.
apppers.

debug environment.
EXPERIMENT 3: Operational Amplifier
Aim: Design an op-amp with given specification using given differential amplifier Common source and
Common Drain amplifier in library and completing the design flow mentioned below:
i) DC Analysis
ii). AC Analysis
c. Check for LVS
Schematic Entry


 Click OK when done the above settings. A blank schematic window for the
Operational_amplifier design appears.
 In the operational_amplifier schematic window, click the Instance fixed menu icon to display the
Add Instance form (or press i)
Operational_amplifier schematic is as shown below.
Lab_experiment Common_source Symbol
Lab_experiment Differntial_amplifier Symbol

Pin Names Direction
Idc Vnon Vinv Input
Vout Output
Vdd Vss InputOutput

Symbol Creation

 In the Operational_amplifier schematic window execute Design-Create Cellview - From
 A new window displays an automatically created operational_amplifier symbol as shown
below
Building the Differential_amplifier test Design


 Click OK when done the above settings. A blank schematic window for the Op_amplifier_test
design appears.
STEP 2: Building the Op_amplifier_test schematic
 In the Op_amplifier_test schematic window, click the Instance fixed menu icon to display the
Add Instance form (or press i
left to place a component. The table showing the components for building the op_amplifier_test
Lab_Experiments Operational_amplifier Symbol
analogLib Vdc,gnd,vss Vdc =2.5; vss=-2.5
analogLib Idc Dc current=30u

 In the Op_amplifier_test schematic window execute Tools-Analog Environment and the

and ok.
 Set the stop time as 5m






Creating Layout View of Operational Amplifier
 From the Operational_amplifier schematic window menu, execute Tools-Design Synthesis –

LayoutXL
 Select Create New option. This gives a new cell view form.
 Check the cellname(Operational _amplifier), viewname (layout) and tool (Virtuoso) and then
click ok. The blank layout window appears


components.
 The Operational_amplifier layout is as shown below
click yes.
apppers.

debug environment.
CMRR Measurement:
EXPERIMENT 4: R-2R DAC
Aim: Design a 4 bit R-2R based DAC for the given specification and completing the design flow
mentioned using given op-amp in the library.
i) DC Analysis
ii) AC Analysis
c. Check for LVS
Schematic Entry


 Click OK when done the above settings. A blank schematic window for the R-2R design appears.
 In the R-2R schematic window, click the Instance fixed menu icon to display the Add Instance
form (or press i)
left to place a component. The table showing the components for building the R-2R schematic is
as shown below.
Gpdk180 Polyres R=2K
Gpdk180 Polyres R=1K
Lab_experiment Operational_amplifier Symbol
AnalogLib Idc Vdc gnd Idc=30u,Vdc=2.5


Pin Names Direction
D0 D1 D2 D3 Input
Vout Output

Symbol Creation

 In the R-2R schematic window execute Design-Create Cellview - From Cellview. The
cellview from cellview form appears as shown below and click ok.
 A new window displays an automatically created R-2R symbol as shown below

Building the R-2R_DAC test Design
STEP 1: Creating a R-2R_DAC _test Cellview

 Click OK when done the above settings. A blank schematic window for the R-2R_DAC_test
design appears.
STEP 2: Building the R-2R_DAC _test schematic
 In the R-2R_DAC _test schematic window, click the Instance fixed menu icon to display the
Add Instance form (or press i
left to place a component. The table showing the components for building the R-2R_DAC _test
Library Name Cell Properties
Name
Lab_Experiments R- Symbol
2R_DAC
analogLib Vpulse For v0:v1=0 v2=2 pulse width=5n period=10n
For v1:v1=0 v2=2 pulse width=10n period=20n
analogLib gnd Symbol
Analog Simulation
 In the R-2R_DAC _test schematic window execute Tools-Analog Environment and the


Creating Layout View of R-2R DAC
 From the R-2R_DAC schematic window menu, execute Tools-Design Synthesis –LayoutXL
 Select Create New option. This gives a new cell view form.
 Check the cellname(R-2R_DAC), viewname (layout) and tool (Virtuoso) and then click ok. The
blank layout window appears

components.
 The R-2R_DAC layout is as shown below
click yes.
apppers.
debug environment.
VLSI LAB VIVA QUESTION:
1. What do you mean by simulation?
2. What is synthesis?
3. What is a test bench?
4. What is the need for test bench?
5. Which is the simulator used ?
6. Explain ASIC flow.
7. What do u mean by ncelab?
8. What is the significance of initial statement?
9. What is the function of $display, $stop, $finish.
10. What if the $finish is not used in test bench? Justify
11. What do you mean by mirror circuits?
12. What do you mean by threshold voltage?
13. What do you mean by DAC? Is there difference between DAC and R2R-DAC. Justify.
14. What do you mean by transient analysis?
15. What do you mean by DC analysis?
16. What do you mean by AC analysis?
17. How do you convert a XOR gate into a buffer and a inverter (Use only one XOR gate foreach)
18. What is a ring counter?
19. Compare and Contrast Synchronous and Asynchronous reset.
20. What is a Johnson counter?
21. How can you convert a JK flip-flop to a D flip-flop?
22. What is the difference between Mealy and Moore FSM?
23. Define Clock Skew , Negative Clock Skew, Positive Clock Skew.
24. Design a Transmission Gate based XOR.
25. Define Metastability.
26. What are set up time and hold time constraints?
27. Explain different types of adder circuits
28. Give the excitation table of a JK flip-flop.
29. Expand the following: PLA, PAL, CPLD, FPGA.
30. What are PLA and PAL? Give the differences between them
31. What is LUT?
32. . What is the significance of FPGAs in modern day electronics?
33. What are the differences between CPLD and FPGA.
34. Compare and contrast FPGA and ASIC digital designing.
35. What is DeMorgans theorem?

VLSI Lab Mannual

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JSS Mahavidyapeetha, Mysuru

JSS Academy of Technical Education

Mrs. SAROJA S BHUSARE, M.Tech. Asst.Prof.

Mrs. ANURADHA M G, M.Tech. Asst.Prof.

Mr. SRIKANTASWAMY S C, BE. Instructor

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 1

1.In Linux prompt, type the command

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 2

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 3

14.To simulate in Simvision

The compiler places the inverter and inverter_test description in ncvlog.log

jss4@vlsiclient4 anu]$ ncvlog inverter_test.v -mess

8.Elaborate the inverter and inverter_test design using the command

[jss4@vlsiclient4 anu]$ ncelab -access +rwc inverter -mess

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 4

The elaborator places the inverter testbench description in ncelab.log

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 5

module inverter (vout,vin);

Verilog code for inverter testbench

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 6

Verilog code for basic gates

Verilog code for basic gates testbench

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 7

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 8

Verilog code for basic gates

Verilog code for basic gates testbench

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 9

Verilog code for basic gates

module basic ( a,b,andf,orf,xorf,nandf,norf,notf);

Verilog code for basic gates testbench

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 11

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 12

Verilog code for SR-Flip flop

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 13

Verilog code for SR-Flip flop testbench

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 14

Verilog code for D-Flip flop

Verilog code for D-Flip flop testbench

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 15

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 16

Verilog code for JK-Flip flop

Verilog code for JK-Flip flop testbench

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 18

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 19

Verilog code for T-Flip flop

Verilog code for T-Flip flop testbench

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 20

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 21

Verilog code for Full adder

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 22

Verilog code for Parallel adder

Verilog code for Parallel adder testbench

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 23

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 24

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 25

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 26

Verilog code for Asynchronous counter

Verilog code for Asynchronous counter testbench

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 28

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 29

Verilog code for Synchronous Counter

DEPT.OF ECE, JSSATE, BENGALURU-60 VLSI LAB MANUAL (15ECL77) Page 30

Verilog code for Synchronous counter testbench