Instrucciones de Salto

Pedro David Jiménez Corrales

Sistemas Microprocesados, Departamento de Ingeniería Electrónica y Control, Escuela Politécnica Nacional

Quito, Ecuador

davidldu34@gmail.com

Abstract- As known, a microprocessor is a computer II. CONTENT DEVELOPMENT

processor on a microchip. The microprocessor contains
all, or most of, the central processing unit, functions. It As said before, a jump is the process of repeating a
is like the engine of the computer that goes into motion sequence of instructions or an operation a certain number
when the computer is on. In addition, the of times.
microprocessor is designed to perform arithmetic and
logic operations that make use of small areas called There are many jump instructions that are classified by
registers. Typical microprocessor operations include unconditional jump and conditional jump.
adding, subtracting, comparing two numbers, and
A. Unconditional jump:
fetching numbers from one area to another. These
This is performed by the JMP instruction. Conditional
operations are the result of a set of instructions that are
execution often involves a transfer of control to the
part of the microprocessor design. When the computer
address of an instruction that does not follow the
is turned on, the microprocessor gets the first
currently executing instruction. These are executed
instruction from the basic input/output system BIOS
whenever it is in the program
that comes with the computer as part of its. After that,
either the BIOS, or the operating system that BIOS
B. Conditional jump:
loads into computer memory, or an application
This is performed by a set of jump instructions
program is driving to the microprocessor, giving it
j<condition> depending upon the condition. The
instructions to perform.
microcontroller first evaluates the condition that is
specified in the instruction and then if the answer is
true, it jumps. Otherwise it does not jump and continue
I. INTRODUCTION in the normal sequence of the program.

A branch is an instruction in a computer program that Some jump instruction are showed next:
can cause a computer to begin executing a different
instruction sequence and thus deviate from its default Jumps directly and unconditionally:
behavior of executing instructions in order. Branch may  JMP – Jump
also refer to the act of switching execution to a different Jump to an address within the entire 4Megas.
instruction sequence because of executing a branch Syntax: JMP k
instruction. A branch instruction can be either an Program Counter: PC  k
unconditional branch, which always results in branching, 32 – bit Opcode:
or a conditional branch, which may or may not cause 1001 010k kkkk 110k
branching, depending on some condition. Branch kkkk kkkk kkkk kkkk
instructions are used to implement control flow in program
loops and conditional.  RJMP – Relative Jump
Relative jump to an address within PC – 2k+1 and
PC + 2k (-2048….2047). This instruction can
address the entire memory from every address
.
location.
Syntax: RJMP k
 Program Counter: PC  PC + k + 1 Program Counter:
16 – bit Opcode: PC  PC + 1, condition false – no skip
1100 kkkk kkkk kkkk PC  PC + 2, skip a one word instruction
PC  PC + 3, skip a two word instruction
Jumps indirectly and unconditionally: 16 – bit Opcode:
 IJMP – Indirect Jump 0001 00rd dddd rrrr
Indirect jump to the address pointed to by the Z
(16 bits) Pointer Register in the Register File. The
Z-pointer Register is 16 bits wide and allows jump
You can look it up in the next flow diagram how CPSE
within the lowest 64k words (128K bytes) section
works:
of Program Memory.
Syntax: IJMP
Program Counter: PC  Z
16 – bit Opcode:
1001 0100 0000 1001 Rd = Rr YES

Compares the content of a register:

 CPI – Compare with Immediate
This instruction performs a compare between NO
register Rd and a constant. The register is not
changed. All conditional branches can be used Next instruction
after this instruction.
Syntax: CPI Rd, k
Program Counter: PC  PC + 1
16 – bit Opcode:
0011 KKKK dddd KKKK Fig. 1 CPSE Flow diagram

 CP – Compare Omit according to the register bit:

This instruction performs a compare between two  SBRC – Skip if Bit in Register is cleared
register Rd and Rr. None of the registers are This instruction tests a single bit in a Register and
changed. skips the next instruction if the bit is cleared.
Syntax: CP Rd, Rr Syntax: SBRC Rr, b
Program Counter: PC  PC + 1 Program Counter:
16 – bit Opcode: PC  PC + 1, condition false – no skip
0001 01rd dddd rrrr PC  PC + 2, skip a one word instruction
PC  PC + 3, skip a two word instruction
 CPC – Compare with Carry 16 – bit Opcode:
This instruction performs a compare between two 1111 110r rrrr 0bbb
registers Rd and Rr and also takes into account the
previous carry.
Syntax: CPC Rd, Rr
Program Counter: PC  PC + 1 Rr(b) = 0 YES
16 – bit Opcode:
0000 01rd dddd rrrr

NO
Compare and omit if they are the same: Next instruction
 CPSE – Compare skip if Equal
This instruction performs a compare between two
register Rd and Rr, and skips the next instruction
if Rd = Rr.
Syntax: CPSE Rd, Rr
Fig. 2 SBRC Flow diagram
 SBRS – Skip if bit in Register is Set
This instruction tests a single bit in a Register and
skip the next instruction if the bit is set.
Syntax: SBRS Rr, b
Program Counter:
PC  PC + 1, condition false – no skip
PC  PC + 2, skip a one word instruction
PC  PC + 3, skip a two word instruction
16 – bit Opcode:
1111 111r rrrr 0bbb
 SBIS – Skip if bit in I/O Register is Set
This instruction tests a single bit in an I/O
Register and skip the next instruction if the bit is
set.
Syntax: SBIS A, b
Program Counter:
PC  PC + 1, condition false – no skip
PC  PC + 2, skip a one word instruction
PC  PC + 3, skip a two word instruction
16 – bit Opcode:
1001 1011 AAAA Abbb

Rr(b) = 1 YES
A(b) = 1 YES

NO
NO
Next instruction
Next instruction

Fig. 3 SBRS Flow diagram

Fig. 5 SBIS Flow diagram

Omit according to the input/output register bit:

 SBIC – Skip if Bit in I/O is cleared Branch according to the status register bit:
This instruction tests a single bit in an I/O  BRBC – Branch if Bit in SREG is Cleared.
Register and skips the next instruction if the bit is Tests a single bit in SREG and branches relatively
cleared. to PC if the bit is cleared.
Syntax: SBIC A,b Syntax: BRBC s, k
Program Counter: Program Counter:
PC  PC + 1, condition false – no skip PC  PC + k + 1
PC  PC + 2, skip a one word instruction PC  PC + 1, if condition is false
PC  PC + 3, skip a two word instruction 16 – bit Opcode:
16 – bit Opcode: 1111 01KK KKKK Ksss
1001 1001 AAAA Abbb

SREG(s) = 0 YES
A(b) = 0 YES

Jump
NO destination
NO
Next instruction
Next instruction

Fig. 6 BRBC Flow diagram

Fig. 4 SBIC Flow diagram
 BRBS – Branch if Bit in SREG is Set. SUB or SUBI, the branch will occur if and only if
Tests a single bit in SREG and branches relatively the unsigned or signed binary number represented
to PC if the bit is set. in Rd was not equal to the unsigned or signed
Syntax: BRBS s, k binary number represented in Rr.
Program Counter: Syntax: BRNE k
PC  PC + k + 1 Program Counter:
PC  PC + 1, if condition is false PC  PC + k + 1
16 – bit Opcode: PC  PC + 1, if condition is false
1111 00KK KKKK Ksss 16 – bit Opcode:
1111 01KK KKKK K001

 BREQ – Branch if Equal.

Tests the Zero Flag (Z) and branches relatively to
PC if Z is set. If the instruction is executed
SREG(s) = 1 YES
immediately after any of instruction CP, CPI,
SUB or SUBI, the branch will occur if and only if
the unsigned or signed binary number represented
Jump
NO in Rd was equal to the unsigned or signed binary
destination number represented in Rr.
Syntax: BREQ k
Next instruction
Program Counter:
PC  PC + k + 1
PC  PC + 1, if condition is false
Fig. 7 BRBS Flow diagram 16 – bit Opcode:
1111 00KK KKKK K001

Branch according to carry flag:

 BRCC – Branch if Carry Cleared. Branch according to negative flag:
Tests the Carry Flag (C) and branches relatively
 BRPL – Branch if Plus.
to PC if C is cleared. Tests the Negative Flag (N) and branches
Syntax: BRCC k relatively to PC if C is cleared.
Program Counter: Syntax: BRPL k
PC  PC + k + 1
Program Counter:
PC  PC + 1, if condition is false PC  PC + k + 1
16 – bit Opcode: PC  PC + 1, if condition is false
1111 01KK KKKK K000
16 – bit Opcode:
1111 01KK KKKK K010
 BRCS – Branch if Carry Set.
Tests the Carry Flag (C) and branches relatively
 BRMI – Branch if Minus.
to PC if C is set. Tests the Negative Flag (N) and branches
Syntax: BRCS k relatively to PC if N is set.
Program Counter: Syntax: BRMI k
PC  PC + k + 1
Program Counter:
PC  PC + 1, if condition is false PC  PC + k + 1
16 – bit Opcode: PC  PC + 1, if condition is false
1111 00KK KKKK K000
16 – bit Opcode:
1111 00KK KKKK K010

Branch according to zero flag:

 BRNE – Branch if Not Equal.
Tests the Zero Flag (Z) and branches relatively to
PC if Z is cleared. If the instruction is executed
immediately after any of instructions CP, CPI,
Branch according to the overflow flag:
 BRVC – Branch if Overflow Cleared.
Tests the Overflow Flag (V) and branches
relatively to PC if V is cleared.
 Syntax: BRVC k  BRCS – Branch if Half Carry Flag is Set.
Program Counter: Tests the Half Carry Flag (H) and branches
PC  PC + k + 1 relatively to PC if H is set.
PC  PC + 1, if condition is false Syntax: BRHS k
16 – bit Opcode: Program Counter:
1111 01KK KKKK K011 PC  PC + k + 1
PC  PC + 1, if condition is false
 BRCS – Branch if Overflow Set. 16 – bit Opcode:
Tests the Overflow Flag (V) and branches 1111 00KK KKKK K101
relatively to PC if V is set.
Syntax: BRVS k
Program Counter:
Branch according to T flag:
PC  PC + k + 1
 BRTC – Branch if the T flag is Cleared.
PC  PC + 1, if condition is false
Tests the T Flag and branches relatively to PC if
16 – bit Opcode:
T is cleared.
1111 00KK KKKK K011
Syntax: BRTC k
Program Counter:
PC  PC + k + 1
Branch according to signed flag: PC  PC + 1, if condition is false
 BRGE – Branch if Greater or Equal (Signed). 16 – bit Opcode:
Tests the Signed Flag (S) and branches relatively 1111 01KK KKKK K110
to PC if S is cleared.
Syntax: BRGE k  BRTS – Branch if the T flag is Set.
Program Counter: Tests the T Flag and branches relatively to PC if
PC  PC + k + 1 T is set.
PC  PC + 1, if condition is false Syntax: BRTS k
16 – bit Opcode: Program Counter:
1111 01KK KKKK K100 PC  PC + k + 1
PC  PC + 1, if condition is false
 BRLT – Branch if Less Than (Signed). 16 – bit Opcode:
Tests the Signed Flag (S) and branches relatively 1111 00KK KKKK K110
to PC if S is set.
Syntax: BRLT k Branch according to global interrupt flag:
Program Counter:  BRID – Branch if Global Interrupt is Disabled.
PC  PC + k + 1 Tests the Global Interrupt Flag (I) and branches
PC  PC + 1, if condition is false relatively to PC if I is cleared.
16 – bit Opcode: Syntax: BRID k
1111 00KK KKKK K100 Program Counter:
PC  PC + k + 1
PC  PC + 1, if condition is false
16 – bit Opcode:
Branch according to Half Carry flag:
1111 01KK KKKK K111
 BRHC – Branch if Half Carry Flag is Cleared.
Tests the Half Carry Flag (H) and branches
 BRIE – Branch if Global Interrupt is Enable.
relatively to PC if H is cleared.
Tests the Global Interrupt Flag (I) and branches
Syntax: BRHC k
relatively to PC if I is set.
Program Counter:
Syntax: BRIE k
PC  PC + k + 1
Program Counter:
PC  PC + 1, if condition is false
PC  PC + k + 1
16 – bit Opcode:
PC  PC + 1, if condition is false
1111 01KK KKKK K101
16 – bit Opcode:
1111 00KK KKKK K111
Branch according to carry flag (unsigned number): Return to subroutine and:
 BRSH– Branch if Same or Higher (unsigned).  RET – Return from Subroutine.
Tests the Carry Flag (C) and branches relatively Returns form subroutine. The return address is
to PC if C is cleared. loaded from the STACK. The Stack Pointer uses
Syntax: BRSH k a pre-increment scheme during RET.
Program Counter: Syntax: CALL
PC  PC + k + 1 16 – bit Opcode:
PC  PC + 1, if condition is false 1001 0101 0000 1000
16 – bit Opcode:
1111 01KK KKKK K000  RETI – Return from Interrupt.
Returns form interrupt. The return address is
 BRLO – Branch if Lower (unsigned). loaded from the STACK and the Global Interrupt
Tests the Carry Flag (C) and branches relatively Flag is set.
to PC if C is set. Syntax: RETI
Syntax: BRLO k 16 – bit Opcode:
Program Counter: 1001 0101 0001 1000
PC  PC + k + 1
PC  PC + 1, if condition is false
16 – bit Opcode: III. CONCLUSIONS
1111 00KK KKKK K000
Within the microprocessor, there are directives, which
can be instructions or pseudo-instructions. The instructions
Call subroutine directly: indicate to the microcontroller the actions to be performed,
 CALL – Long Call to a Subroutine. while the pseudo-instructions send commands or the
Calls to a subroutine within the entire Program addresses to the assembler.
memory. The return address (to the instruction
after the CALL) will be stored onto the Stack. When working with the different instructions of the
Syntax: CALL k microprocessor, they must be labeled. It should be noted
Program Counter: PC  k by that the name of the tags must be unique. It does not
32 – bit Opcode: difference with normal or capital letter at the time of
1001 010K KKKK 111k labeling, and you can use digits and special characters.
kkkk kkkk kkkk kkkk Keep in mind that the start of the label must be a letter and
you cannot use labels with similar names to instructions.
 RCALL – Relative Call to a Subroutine.
Relative call to an address within PC – 2K + 1 and The computer has an oscillating crystal that provides a
PC + 2K (words). The return address (the synchronization signal. This signal coordinates all the
Instruction after the RCALL) is stored onto the activities of the microprocessor and is better known as
Stack. clock signal. The clock speed is measured in MHz,
Syntax: RCALL k throughout the history of the microprocessors will continue
Program Counter: PC  PC + k + 1 as the speed of this signal increases and allows us to
16 – bit Opcode: execute millions of instructions per second.
1101 KKKK KKKK KKKK
The microprocessor is in charge of running the
Call subroutine indirectly: programs, from the operating system to the user
 ICALL – Indirect Call to Subroutine. applications; Only executes instructions programmed in
Calls to a subroutine within the entire 4M (words) low-level language, performing simple arithmetic and
Program memory. The return address (to the logic operations, such as adding, subtracting, multiplying,
instruction after the CALL) will be stored onto the dividing, binary logics and memory access.
Stack.
Syntax: ICALL
16 – bit Opcode:
1001 0101 0000 1001
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