Vivado_tool_flow:

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Vivado_Tool_Flow

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TABLE OF CONTENTS
1.Folder_Template_Managment:...............................................................................................................3
2. Getting Started With Vivado :..............................................................................................................4
3. Vivado_Project_Manager_Flow..........................................................................................................7
4. Vivado_Synthesis Flow.......................................................................................................................8
5. Vivado_implementation Flow..............................................................................................................8
6. REFERENCES...............................................................................................................................................9

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1.Folder_Template_Managment:
Maintain following folder structure before creating any project in vivado:

1.1 BIT:
Bit files corresponding to design should be maintained in bit folder after design
bitstream generation.
1.2 PROJECT:
Vivado design project should be created in Project folder of specific design .
1.3 SRC_SIM:
1.3.1 All coefficient files related to project should be maintained in COE folder.

1.3.2 All testbenches for the project should be maintained in Testbench folder.

1.4 SRC_DESIGN:
Source Design comprises of 3 parts:

1.4.1 IP
All ip instantiations related to project should be maintained in IP folder.

1.4.2 RTL
All source design files related to project should be maintained in RTL folder specific
to project.

1.4.3 XDC
XDC for targeted device for project should be maintained in XDC folder.

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2. Getting Started With Vivado :

2.1 Creating Vivado Project:
2.1.1 Open Vivado 2018.3.
2.1.2 Click on create project to create a new vivado project .

2.1.3 Specify respective Project Name and Location and Click on Next Button.

2.1.4 :

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Depending on the type of project you are creating, continue with the
instructions in one of the following sections. The remaining pages of the
wizard guide you through adding appropriate sources to the project.
° Creating an RTL Project
° Creating a Post-Synthesis Project
° Creating an I/O Planning Project
° Importing an External Project

Note: Project type allows to add or create source files during or after project creation.

2.1.5 Add or create Project related Source files, you can also add ip core to the
project and click on NEXT Button.

2.1.6 Add Constraints files for the specific targeted device for project.

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2.1.7 Add respective device number for the targeted device .

2.1.8 Click on create project to create vivado project .

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3. Vivado_Project_Manager_Flow
Once we have created vivado project the next step is to simulate the design for its
functional validation .
3.1 In Vivado sources right click on Design Sources and select add sources for adding or
creating testbench in vivado .

3.2 Select Add or Create Simulation Sources and to add or create testbench for the
specific design validation.

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3.2 After Creating testbench the next step is to simulate the design for its functional
correctness,for that right click on simulation and select Run Behavioural Simulation
from vivado flow navigator .

4. Vivado_Synthesis Flow
Once the design has been functionally validated the next step is to add Xilinx Design
Constraints file for the targeted device and synthesize the design for specific timing
requirements.
Click on Synthesis option from vivado flow navigator .
Once the design is synthesized the next step is to validate the design for meeting
specific timing requirements.
Remove timing violations if present.

5. Vivado_implementation Flow
Implement the synthsesized design.
Check for the timing violations for the implemented design .
If any violations are present remove it and Click on generate bitstream to generate Bit
file for the design and validate on the targeted device.

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6. References

1. Xilinx.com

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