Lecture Notes in Microelectronics

Torsten Lehmann
March 7, 2006

1 MOS design equations

D S
iDS − −
+ vGS − vBS
vDS + + B
G + + B G
− + v DS
vGS vBS
− − iDS
S (A) D (B)

Figure 1: MOS transistor symbol, voltage and current definitions; (A) NMOS transistor
(B) PMOS transistor.

NMOS PMOS
full symbol

bulk implicit

switch

depletion

high-voltage

Figure 2: MOS transistor varieties.

1
1.1 Support equations
p p 
threshold voltage Vth = Vth0 + γ |2φF − vBS | − |2φF | (1)

x for n-channel γ
n/p sign function |x|p ≡ ; |x|p = x (2)
−x for p-channel |γ|
γ
sub-threshold slope n = p + |1|p (3)
2 |2φF − vBS |
gate-overdrive voltage vEff = vGS − Vth (4)
µ0
velocity saturation µ = (5)
1 + vDS /(ECrit L)
W 0 W
drain current factor β = K = µCox ; K 0 = µCox (6)
L L
kλ vDS kλ
channel-length modulation α = 1 + λvDS = 1 + ; λ= (7)
L L
thermal voltage VT = kT /q (8)
sub-threshold scale current I0 = 21 µCox (2nVT )2 (9)
W
weak-strong transition IWST = I0 ln2 (2) (10)
L

1.2 Current equations

> |2nVT ln(10)|p , or |IDS,sat |p  |IWST |p ):
Strong inversion (|vEff |p ∼

W 2
vEff vDS − 21 vDS


iDS = µCox α, |vEff |p > |vDS |p (triode) (11)
L
W 2
iDS = IDS,sat = 12 µCox vEff α, |vEff |p ≤ |vDS |p (saturation) (12)
L
< −|2nVT ln(10)|p , or |IDS,sat |p  |IWST |p ):
Weak inversion (|vEff |p ∼

W vEff /(nVT )
1 − e−|vDS |p /VT α


iDS = I0 e (13)
L
W
iDS = IDS,sat = I0 evEff /(nVT ) α, |nVT |p  |vDS |p (saturation) (14)
L
Moderate inversion saturation (|vDS |p  |nVT |p , and |vDS |p > |vEff |p ):

W
iDS = IDS,sat = 21 µCox (2nVT )2 ln2 1 + evEff /(2nVT ) α


(15)
L

2
 1000
current expression
(log(1+exp(x/2))/log(2))**2
100 x**2/(log(2)*2)**2
exp(x)/log(2)**2
10
iDS /Iwst

0.1

0.01

0.001
-4 -2 0 2 4
veff /nVT

Figure 3: Normalised saturation current

1.3 Sample MOST parameters

Typical parameters for some CMOS processes (preliminary):
Process 0.35 µm 0.18 µm
Parameter n-channel p-channel n-channel p-channel
VDD,max 2.5 V 2.5 V 1.8 V 1.8 V
Vth0 0.6 V
√ −0.6 V√ 0.5 V
√ −0.5 V√
γ 0.5 V −0.5 V 0.6 V −0.4 V
2φF 0.7 V −0.7 V 0.8 V −0.8 V
n (zero bias) 1.3 −1.3 1.4 −1.3
Lmin 0.35 µm 0.35 µm 0.18 µm 0.18 µm
kλ 0.1 µm/V −0.1 µm/V 0.12 µm/V −0.08 µm/V
µ0 Cox 120 µA/V2 −40 µA/V2 260 µA/V2 −65 µA/V2
Cox 4 fF/µm2 4 fF/µm2 8 fF/µm2 8 fF/µm2
Cj0 0.8 fF/µm2 1.2 fF/µm2 2 fF/µm2 2 fF/µm2
Cj0sw 0.3 fF/µm 0.4 fF/µm 0.6 fF/µm 0.6 fF/µm
Cov 0.2 fF/µm 0.2 fF/µm 0.1 fF/µm 0.1 fF/µm
xj 0.1 µm 0.1 µm 0.05 µm 0.05 µm
lsd 1 µm 1 µm 0.5 µm 0.5 µm
λ (DRC) 0.2 µm 0.2 µm 0.1 µm 0.1 µm
ECrit ∞ −∞ 2.2 V/µm 5 V/µm

3
2 Noise
Calculating total input referred noise is often impossible, as the integral typically diverges
for both high frequencies (white noise) and low frequencies (1/f noise). The total output
referred noise is easier, as any circuit has an upper band-width — typically, this doesn’t
solve the 1/f divergence problem, however. My suggestion is to equate the lower frequency
bound to 1/Tobs , where Tobs is the observation time of the system (e.g., the time it is turned
on — say a day or so):
Z ∞ X
2
Vno,tot = Vni2 (f )|Hi (f )|2 df
1/Tobs i

3 Matching
To a first order approximation, the relative variance of drain current in MOS transistor
biased in strong inversion saturation can be expressed as:
2
σD BW BL BK BV
2
= + + + 4 (16)
ID LW 2 W L2 W L(µCox )2 W L(VGS − Vth )2

where ID is the average (nominal) drain current, and the Bs are constants. For relatively
large transistors and a given gate bias voltage, this simplifies to:
2
σD BI
2
' (17)
ID WL

4
4 Problems
4.1 Problem 1
VDD

IB
vOUT

vIN

VSS

Figure 4: Common source amplifier

The common source amplifier in figure 4 is biased with a DC drain current of IB = 1 µA.
It is to be implemented in the 0.35 µm process, where the smallest transistor dimensions
allowed (for this amplifier) is 0.7 µm.
• Find W and L such that the transistor is biased in weak inversion. Find for this
transistor all the small-signal parameters (gm , rds , Cgs , Cgd , Csb , and Cdb ) and the
low-frequency voltage gain, Av . Find also fT for the transistor.
• Now find W and L such that the transistor is biased in strong inversion, and again
find gm , rds , Av and fT . For this amplifier, what must the DC bias value, VIN , of in
the input voltage be? What must VIN be if the source voltage is 1 V rather than 0 V
as on the figure?
• Finally, find W and L such that the transistor is biased in strong inversion, but has
the same gate area as the weak-inversion amplifier, and find gm , rds , Av and fT .

4.2 Problem 2
For the circuit in figure 5, prove that
W
i1 − i2 = µCox v1 v2 ,
L
when all transistors are identical and operate in the triode region (the bulk affect can be
ignored).

4.3 Problem 3
For the CMOS nand-gate in figure 6, find all transistors widths, W and lengths, L such
that the gate can drive a load capacitance of CL = 1 pF in less than 5 ns.

5
 v1
i1

v2 0V by feedback

i2

Figure 5: Cross-coupled transistor pairs

VDD

P P
param N P unit
z
µCox 92 −30 µA/V2
a N CL Vth 0.8 −0.9 V
Lmin 0.8 µm
b N
VDD 2 V
(a) (b)

Figure 6: Static CMOS nand-gate (a) and circuit and transistor parameters (b)

4.4 Problem 4

VDD

VB P

z
a SN
CL
b SN
N

Figure 7: CSL nand-gate

For the Current Steering Logic (CSL) nand-gate in figure 7, find all transistors widths,
W and lengths, L, and the bias voltage, VB such that the gate can drive a load capacitance
of CL = 1 pF in less than 5 ns; use the same circuit and transistor parameters as in problem
3.

6
4.5 Problem 5

param val unit

MS Cox 5 fF/µm2
word line
Lmin 0.35 µm
Cj (sb, sd) 1.5 fF · W
VB
MC
VDD 3 V
bit line (a) (b)

Figure 8: DRAM cell (a) and transistor parameters

The dynamic RAM cell in figure 8 is arranged in a square, 1 cm2 matrix. Estimate the
largest number of bits in the matrix when the sense amplifier can detect a 50 mV voltage
difference and relevant transistor parameters are given in the figure. Transistor ms is a
switch transistor while transistor MC act as a storage capacitor. The bias voltage, V B is
chosen > VDD + Vth , and the word-line is like-wise clock-boosted to a voltage > VDD + Vth
when high. Find also the widths, W and lengths, L for the transistors.

4.6 Problem 6

iin iout

Figure 9: Current mirror

For a given vGS , the relative drain current variation (in saturation) is given by
σ2 BI
2
= , BI = 5 · 10−4 µm2 ,
ID WL
where ID is the average drain current and σ 2 is the variance of the drain current. The
drain current is assumed to be normally distributed. For the current mirror in figure 9
with W/L = 5µm/2µm for both transistors, what is the probability that |iout − iin | < 1 %?

4.7 Problem 7
A wafer has a defect density of D = 0.01 cm−2 . Chips on the wafer are 2 cm2 in size,
each having 1000 sub-components that perform outside specifications with a probability of
0.002 % each. Find the fraction of chips which function within specifications after manu-
facturing.