Habib University

Dhanani School of Science and Engineering

Digital Logic Design

(EE-172L / CS-130L)

Lab Manual
Table of Contents
ABOUT THE LAB MANUAL .................................................................................................................................... 1
ABOUT THE LAB EXERCISES ............................................................................................................................... 3
CONVENTIONS .......................................................................................................................................................... 5
LAB 5A – HANDS ON FPGA ..................................................................................................................................... 7

Objectives ................................................................................................................................................................. 7
Introduction .............................................................................................................................................................. 8
i. Procedural Statements .................................................................................................................................. 8
ii. Clock Signal .................................................................................................................................................. 8
iii. Design Task................................................................................................................................................... 9
iv. Testbench ...................................................................................................................................................... 9
Concept Check .................................................................................................................................................. 10
a. Setting up ISE Project Navigator ...................................................................................................................... 11
b. I/O Pin Planning in PlanAhead ......................................................................................................................... 14
c. Clock Divider .................................................................................................................................................... 17
d. Synthesis and Implementation........................................................................................................................... 20
e. Device Configuration ........................................................................................................................................ 21
LAB 5B – INTERACTIVE TESTING USING EXTERNAL SOFTWARE ........................................................ 24

Objectives ............................................................................................................................................................... 24
a. Introduction ....................................................................................................................................................... 25
i. Concatenation operator .............................................................................................................................. 25
b. Setting up the Hardware .................................................................................................................................... 26
i. Integration of UART and counter modules ................................................................................................. 26
ii. Synthesis and Implementation .................................................................................................................... 27
iii. Chip-Desktop Connection ........................................................................................................................... 27
c. Testing hardware with HU-DLDLabs-FPGA App ........................................................................................... 28
Exercise .................................................................................................................................................................. 30
REFERENCES ........................................................................................................................................................... 31
About the lab manual
This lab manual has been created with the help of practical experiments, several supporting
documents and presentations listed in the Bibliography section.

The creation process of this manual was started during the summer 2019 by Dr. Hasan Baig, and
it is continuously being updated during the Fall 2019. The Research Assistants, Hassan Shah,
Hafsa Amanullah, and Saad Rashid, are involved in the continuous improvement of its contents.

For questions, comments, suggestions, advices or corrections in this lab manual, please contact
Dr. Hasan Baig at the following email address: hasan.baig@sse.habib.edu.pk.

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2
About the lab exercises
A brief overview of each lab will go here.

In Lab 1, you will be practicing the conversion of a signed number in decimal, binary, octal and
hexadecimal formats.

In Lab 2, you will verify the behavior of Logic Gates using Truth Table (AND, OR, NOT and NOR)
and familiarization with Digital Integrated Circuits by reading its datasheet and the internal IC gate
level structure of the respective IC.

In Lab 2(b), you will verify the behavior of Logic Gates using Truth Table (XOR) and
familiarization with Digital Integrated Circuits by reading the datasheet and the internal IC gate
level structure of the respective IC, you will also implement XOR and XNOR Logic using AND
OR and NOT Gates.

In Lab 3, you will be introduced to the programmable logic and the Verilog HDL. Furthermore, you will
learn how to design a simple hardware and verify its functional behavior using a professional simulation
tool, named ModelSim®.

In Lab 4, you will implement a 2-bit adder using combinational gates and display its result on 7-segment
display.

Lab 5 is divided into two parts. In part (a), a hardware synthesis flow is discussed targeting the Xilinx
FPGA technology. Furthermore, you will get to run your designed hardware on actual FPGA chip. In part
(b), you will learn how to integrate the ready-made UART module with your custom design for
communication with external devices. Also, in this session, you will use a desktop-based software, designed
specifically for this course, to observe the output of on-chip hardware. The lab has been developed with a
help of several different references which are listed down at the end of this manual.

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4
Conventions
The following conventions appear in this lab manual.

This icon denotes a “pre-lab exercise”, which a student should complete

before coming into the respective lab.
This icon denotes a “lab exercise”, which a student should complete
during the lab hours.
This icon denotes a “post-lab exercise”, which a student should complete
outside the lab hours.

This icon indicates the expected time (in minutes) to complete the specific
exercise.

This icon denotes a tip, which notifies you to advisory information.

This icon denotes an alert, which notifies you to important information.

Bold or
Italic The text written in this font is used specifically for the syntax of HDL.
Bold text denotes items that you must select or click or enter the value in
the software, such as open file option or running the simulation button or
bold entering the command in the transcript window. The bold text is also used
to refer to the specific options in the software tools.

italic Italic text denotes the name of a folder or a file path.

bold and italic Bold and italic text denotes the name of a file.

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6
 Lab 5a – Hands on FPGA
Objectives

In this lab, you will learn how to synthesize and implement the HDL code into the Xilinx-Specific
Technology FPGAs, and then configure the FPGA device with a bitstream. Xilinx Spartan-6 LX9
microboard is used in the labs. The FPGA mounted on this board is XC6SLX9-2CSG324C.

Section
Introduction
The basic concepts are introduced which will be required to complete this lab.
Furthermore, you are required to design a module of a 4-bit counter before coming 20
to a lab which will help you to complete the lab on time.

a) Setting up ISE project Navigator

In this section, you will learn how to setup the Xilinx ISE project navigator for
your design of counter module which you have already developed in pre-lab 10
exercise.

b) I/O Pin Planning in PlanAhead

Here, you will learn to use the PlanAhead tool to connect the input/output ports 20
with the physical pins of FPGA.

c) Clock Divider
In this section, you will learn how to slow down the clock speed and why do we 25
need to do this.

d) Synthesis and Implementation

After doing all above steps, you will synthesize and implement your design using 05
ISE tool in this section.

e) Device Configuration
Finally, you will use the iMPACT tool for downloading the bitstream file into an 05
FPGA.

7
Lab 5a – Hands on FPGA
Introduction

Introduction
In lab 03, you learnt how to develop Verilog HDL modules of basic logic gates using a continuous
assignment (assign) statement to define the behavior of a circuit. The assign statement runs
continuously without passing through any procedure.

i. Procedural Statements
In order to design a circuit which should execute for specific scenarios, there are other behavioral
statements, categorized in Verilog as the structured procedural statements, called initial block
and always block. These statements are the two most basic statements in behavioral modeling.
All other behavioral statements can appear only inside these structured procedural blocks. We have
previously used the initial block to declare predefined input sequences in testbench. As
opposed to the initial block which runs only once at the beginning of simulation, always
block runs continuously in a looping fashion. The following code exemplifies the behavioral
modeling in Verilog.

always @ (posedge clock or negedge reset);

begin
if (reset == 0)
begin
a = 0;
b = 0;
end

else
begin
// This block will be executed only when the clock signal
// is high (logic-1) and reset is also high (logic-1).

a = i0 & i1; // AND operation between i0 and i1, and

// assign the output to a.

b = a | i3; // OR operation between i3 and a, and

// assign the output to b.
end
end

The code written inside the always block will run only when either the clock signal transitions
from 0 to 1 (positive edge) or when the reset signal transitions from 1 to 0 (negative edge). Once
the always block is activated, the if-else structure execute either if or else branch
depending on the value of reset signal. The statements enclosed inside the begin and end
keywords run in the order they are specified.

ii. Clock Signal

A clock signal, shown in the figure below, is a particular type of signal that oscillates between a
high and a low state and is used to coordinate actions of digital circuits. The period between the

8
Lab 5a – Hands on FPGA
Introduction

two consecutive positive edges or two consecutive negative edges is called a Time Period and is
denoted with T. Therefore, the frequency at which the digital circuit operates is defined by f = 1/T.

iii. Design Task

You are required to develop a 4-bit counter module, named counter, which should have the
following features:

1. Inputs: 1-bit clk and reset signals

2. Outputs: 4-bit count signal
3. Increment the counter output (count) at every positive edge of clock signal (clk), when
the reset signal is not HIGH.
4. If reset signal is HIGH, reset the counter output (count) to 0.

iv. Testbench
Use the following testbench to verify the functionality of your designed counter module. Try to
understand it completely.

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Lab 5a – Hands on FPGA
Introduction

Concept Check
Assuming that a time unit, in above mentioned testbench, is defined in nano seconds; what is the
frequency at which the designed counter module would operate?

Answer: ______________________________________________.

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Lab 5a – Hands on FPGA
Setting up ISE Project Navigator

a. Setting up ISE Project Navigator

Xilinx ISE Project Navigator is an Integrated Development Environment for digital logic design
projects with Xilinx FPGAs and CPLDs. Project Navigator provides a simple way to centrally
manage the files in your project as well as automatically invoking all of the other CAD tools.
Follow the steps given below to create a project in the Xilinx ISE navigator.

1. Launch ISE Project Navigator

Launch Xilinx ISE by double clicking on the following ISE Design Suite 14.7 icon on your
desktop, as shown in the image below.

2. Create a Project
Go to File > New Project and enter the details as shown in the figure below and press Next.

Spaces are not allowed in the project name in Xilinx ISE.

11
Lab 5a – Hands on FPGA
Setting up ISE Project Navigator

3. Project Settings
Match the project settings with those shown in the figure below:

Figure 5.1. Project settings window.

Press Next and then Finish.

4. Loading Design Files in ISE Project Navigator

Since you have already designed the HDL code of 4-bit counter, we just need to add that file
(top level module) into the existing project.

Make sure the Design tab is selected (shown in red circle), in the following figure. Right click
on the project name, counter, and select Add Source…, as shown in the image below.

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Lab 5a – Hands on FPGA
Setting up ISE Project Navigator

You can also click on the icon (shown in green circle) to add your existing
source HDL.

Now browse to C:\DLD_Labs\Lab05\design and add counter.v file. After adding, the project
navigator window will now look like the figure shown below.

Also, the Design tab display several different Processes available for the counter module, as
shown in the image below.

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Lab 5a – Hands on FPGA
I/O Pin Planning in PlanAhead

b. I/O Pin Planning in PlanAhead

Before synthesis, we need to specify the pins of FPGA to which the input/output ports of the
counter module have to be connected.

In the Design tab, drop down the User Constraints menu and double click on I/O Pin Planning
(PlanAhead) – Pre-Synthesis, as shown in the figure below:

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Lab 5a – Hands on FPGA
I/O Pin Planning in PlanAhead

Press Yes button if the following message appears.

The process will initialize the Xilinx PlanAhead tool and the following window will appear
showing the floorplan of XC6SLX9-2CSG324C FPGA.

We can now connect the I/O ports of the counter module with the physical pins of FPGA. There
are 6 I/O ports in our design of counter – 4-ports for 4-bit output count, 1 input port for clk and
1 for reset.

The motivation of this lab is to let the student observe the counter running on board. There are four
user LEDs available on LX9 Microboard, which we can use to observe the counter output.

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Lab 5a – Hands on FPGA
I/O Pin Planning in PlanAhead

Furthermore, we have to connect the reset port either to one of the push buttons or to any of the
DIP switches available on the board.

In this experiment, we will connect the output port count with the four user LEDs and the reset
port with one of the DIP switches. The four user LEDs and the DIP switches are shown in the
image below.

DIP Switch User LEDs

The pin information can be obtained from the user guide of LX9 Microboard [1]. Table I describes
the connections between the I/O ports of our design, counter, and the specific FPGA pins which
are connected to the user LEDs and DIP switches.

Table I. I/O Pin Assignment Plan.

I/O port of Name of on-board
Physical FPGA Pin
ripple_carry_counter component
count [3] LED D10 C2
count [2] LED D9 F5
count [1] LED D3 L6
count [0] LED D2 P4
clk 40 MHz clock V10
reset DIP 1 B3

Several options are available for clock in LX9 Microboard [1], among which we will use the 40
MHz clock.

In the I/O Ports tab in PlanAhead tool, drop down count and Scalar ports and specify pin names
(shown in Table 1) in the Site column for each specific pin. After assigning pin names, the I/O
Ports tab should look like the following image.

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Lab 5a – Hands on FPGA
Clock Divider

When you assign the pin name to each port, you will notice that it is marked fixed automatically.
You can also right-click on selected port and click Place I/O Ports in an I/O Bank option. Now
you can zoom-in the Package window and click on the FPGA pin you wish to connect to the
selected port. This is shown in the figure below for the port count[0].

When all the ports are connected to FPGA pins, we should now export this I/O Ports file, called
user constraints file (UCF), to use with the ISE project navigator.

Go to File > Export I/O Ports… > Check UCF > Click .

Browse to the following directory C:\DLD_Labs\Lab05\synthesis\counter\ and double click on the

counter.ucf file. Click OK to overwrite it. Click OK if prompted with the message to overwrite
the counter.ucf file again.
Close PlanAhead tool and go back to the ISE Project navigator.

c. Clock Divider

We are using a 40 MHz clock (Time period = 1/(40x10^6) = 25ns) and the counter output is
supposed to be updated at every positive edge of clock. Therefore, it is impossible for us to observe

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Lab 5a – Hands on FPGA
Clock Divider

the output on user LEDs because the output will be updated every 25ns. We therefore need to slow
down the process by dividing the clock. In order to observe the output, we will run the counter at
0.5 Hz (2 seconds). The high-level diagram for this scenario is shown below:

Write down the clock divider module shown in the following figure. This module has two inputs
clock_n and reset_p, and one output div_clk. In this experiment, the clock_n input will
take the original clock (of 40 MHz).

Verilog allows a user to define a constant value with a help of a keyword parameter, as shown
in line 7. A 32-bit register is defined with the name counter, which counts to a value of
max_count = 40000000. The value of one-bit output div_clk is toggled every time when
the counter becomes equal to max_count. It will take exactly one second to count a value of
40x10^6 by a clock of 40x10^6 Hz. Therefore, the output div_clk signal will toggle after every

Page | 18
Lab 5a – Hands on FPGA
Clock Divider

one second and the time period of div_clk becomes 2 seconds. Now, running counter module
at this frequency will help us to observe the output on FPGA board. Save the clock_divider.v file
in C:\DLD_Labs\Lab05\design\.

Now create a top module named top_counter.v having inputs clk and reset, and a 4-bit
output count. Now instantiate the clock_divider and counter modules in it. Make the
internal connections as shown in the figure below. That is, connect the output, div_clk, of the
clock_divider module with the input clock signal, clk, of the counter module i.e. with a
help of a wire clk_count (line 6, 12, and 17).

Add top_counter.v file in the project as same as we did before for adding the counter.v file.
You may notice that an instantiated clock_divider module appears to be missing in the ISE Project
navigator, as shown in the image below.

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Lab 5a – Hands on FPGA
Synthesis and Implementation

Right click on clk_divider - clock_divider (), Add Source… and provide the clock_divider.v
file from the location C:\DLD_Labs\Lab05\design\.

d. Synthesis and Implementation

At this point, we are now ready to synthesize our design and generate its implementation files.

1. Synthesis
Synthesis is the process of constructing a gate level netlist from a register-transfer level model
of a circuit described in Verilog HDL. Xilinx Synthesis Technology (XST) is a Xilinx®
application that synthesizes Hardware Description Language (HDL) designs to create Xilinx
specific netlist files called NGC files. The NGC file is a netlist that contains both logical design
data and constraints.

Double Click on Synthesize – XST in the Processes: top_counter window to synthesize the
top module design, top_counter.

2. Implementation
Implementation process comprises of the following sub-processes

• Translate – The Translate process merges all of the input netlists and design constraint
information and generates a Xilinx® Native Generic Database (NGD) file. The output
NGD file can then be mapped to the targeted device family.

• Map – This process takes the Xilinx® Native Generic Database (NGD) file created during
translation, runs a design rule check, and maps the logic design to a Xilinx FPGA. It
generates a Native Circuit Description (NCD) file, which is used for placing and routing.

• Place and route – This step take a mapped NCD file, places and routes the design, and
produces an NCD file to be used by the programming file generator, BitGen.

Double Click on Implement Design in the Processes: top_counter window to implement the
top module design, top_counter. After implementing the design, we can generate the
programming (.bit) file, that will be used to configure the targeted FPGA device.

Double Click on Generate Programming File in the Processes: top_counter window to

generate the programming file of top_counter.

When you are done successfully with all of the previous processes, you will see the green
checked marks in front of each of the process options as shown in the image below.

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Lab 5a – Hands on FPGA
Device Configuration

e. Device Configuration

To Configure the target device, double click on the option, Manage Configuration Project
(iMPACT), shown high-lighted in the figure above. This will initialize another standalone tool
named iMPACT, which will look like the following image.

Page | 21
Lab 5a – Hands on FPGA
Device Configuration

iMPACT, a tool featuring batch and GUI operations, allows you to perform Device Configuration
and File Generation. Operating in Boundary-Scan mode, iMPACT can configure or program
Xilinx FPGAs, CPLDs, and PROMs.

Boundary scan is a method for testing interconnects (wire lines) on printed circuit boards or sub-
blocks inside an integrated circuit. It is the most popular configuration mode due to its
standardization and ability to program FPGAs, CPLDs, and PROMs through the same four JTAG
pins. Boundary-Scan (IEEE Std 1149.1, JTAG) configuration mode enables you to perform
Boundary-Scan-based configuration operations on any chain of IEEE standard 1149.1 compliant
devices. The chain can consist of both Xilinx® and non-Xilinx devices, but only the BYPASS and
HIGHZ operations are available for non-Xilinx devices.

Double click on Boundary Scan in “iMPACT Flows” window. Right click in the white area
inside the Boundary Scan tab and click on “Initialize Chain” option as shown below:

Before executing the “initializing chain” operation, make sure that the FPGA
board is connected to your computer.

Once the boundary scan is completed, all the devices present on board will be displayed. The LX9
Microboard contains only an FPGA so you will see the following image containing only a single
device (xc6slx9) detected., with a display message “Identify Succeeded”.

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Lab 5a – Hands on FPGA
Device Configuration

Right Click on the device icon (shown in green in above image), select Assign New
Configuration File…, and assign top_counter.bit file from the following location:
C:\DLD_Labs\Lab05\synthesis\counter\.

If prompted with the following message, select No.

Right Click on the device icon again and select Program. A new window will appear, press OK,
and it will begin downloading the .bit file on FPGA. The counter will begin executing on FPGA
board, when you see the message “Program Succeeded” in the Boundary Scan window.

Observe the counter behavior. Reset the circuit and see if it follows the designed functionality.

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 Lab 5b – Interactive Testing
using External Software
Objectives

In this lab, we will use a desktop-based application, named HU-DLDLabs-FPGA, to observe the
counter output more intuitively. To do this, we will create a setup in hardware to transmit the on-
chip counter data to a desktop computer using a serial interface.

Section
a) Introduction
In this section, you will get an idea of how we are going to enhance our 10
experimental setup to make it user-friendly.

b) Setting up the hardware

You will include some ready-made hardware modules on chip and integrate it with
your custom design module – top_counter. Then you will synthesize the new 30
hardware and generate the bitstream.

c) Testing Hardware with HU-DLDLabs-FPGA App

In this section, you will integrate hardware with HU-DLDLabs-FPGA software 05
to observe the output of your custom design in an appropriate manner.

Exercise
Small exercise to practice either at home or in the lab. However, you will need to test 30
the functionality on FPGA board which requires you to be in lab.

24
Lab 5b – Interactive Testing using External Software
Introduction

a. Introduction
In previous lab, it was a little difficult to observe the counter output due to unavailability of enough
resources, for example 7-segment display. In this lab, we will be using a desktop-based application,
named HU-DLDLabs-FPGA, which is developed to help students in testing on-chip hardware in
a user-friendly manner.

The following figure shows the conceptual diagram for testing the counter module. Instead of
observing the counter output on on-board LEDs, the following setup transmits the counter data to
a computer via UART (Universal Asynchronous Receiver Transmitter) interface [6]. This data is
then received by HU-DLDLabs-FPGA application which then displays the integer value of a
counter.

Figure 5b.1. Conceptual diagram showing the integrated experimental setup with HU-DLDLabs-FPGA App.

Studying UART protocols is out of the scope of this lab. If interested, you can
study more about UART from the reference [6].

In order to complete this lab, you will be required to use the assignment (assign) statement and
the concatenation ({}) operators. You have already studied and used the assign operator in Lab
03 before. The concatenation operation is ({}) briefly described below.

i. Concatenation operator

The concatenation operator ({ , }) provides a mechanism to append multiple operands. The

operands must be sized. Un-sized operands are not allowed because the size of each operand must
be known for computation of the size of the result.

Concatenations are expressed as operands within braces, with commas separating the operands.
Operands can be scalar nets or registers, vector nets or registers, bit-select, part-select, or sized
constants. Following examples shows the usage of concatenation operator.

25
Lab 5b – Interactive Testing using External Software
Setting up the Hardware

// A = 1'b1, B = 2'b00, C = 2'b10, D = 3'b110 line 1.

Y = {B, C} // Result Y is 4'b00_10 or 4’b0010
Y = {A, B, C, D, 3'b001} // Result Y is 11'b1_00_10_110_001
Y = {A, B[0], C[1]} // Result Y is 3'b1_0_1

b. Setting up the Hardware

The on-chip hardware of a UART Tx/Rx interface is already developed and is provided under the
folder Lab5b shared on Workplace. Download the folder Lab 5b and place it under C:\DLD_Labs\
directory.

Also, copy the design files clock_divider.v, counter.v, and top_counter.v from the location
C:\DLD_Labs\Lab05\design\ into C:\DLD_Labs\Lab5b\design\counter\ directory.

All we need to do now is to tie up the UART’s interface with our top design module i.e.
top_counter.

i. Integration of UART and counter modules

Create a top.v file under C:\DLD_Labs\Lab5b\design\ directory and create a top module to
instantiate uart_top and top_counter modules in it. Make the connections as shown in the
following figure.

Figure 5b.2. The internal connections inside the top module containing the uart_top and top_counter
modules.

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Lab 5b – Interactive Testing using External Software
Setting up the Hardware

The figure shown above tells us that the top module should have three input and 2 output ports,
named clk, reset, rx, and count, and tx, respectively. The 4-bit output count of
top_counter module is not only connected to the 4-bit output port, count, of the top module
but it is also connected to the 8-bit input port, data_to_tx, of uart_top module through an
8-bit internal wire, counter_data.

Once the connections are made, we can proceed to the next step of synthesizing the complete
hardware (top.v) of counter integrated with UART.

ii. Synthesis and Implementation

Follow all the steps described in section a, b, and d in the lab session 5a, with the following
information:

1. Project Name: Integrated_Counter_UART

2. Project Location: C:\DLD_Labs\Lab5b\synthesis
3. Keep the Project Settings same as shown in Figure 5.1.

While making the I/O port connections using PlanAhead (as described in section b of lab session
5a), follow the port connections as shown in Table I. There are two additional ports i.e. tx and
rx, which should be connected to the pins as shown in Table II below.

Table II. I/O pin assignment for RX and TX ports of UART.

I/O port of
On-board Net Name Physical FPGA Pin
ripple_carry_counter
tx USB_RS232_TXD T7
rx USB_RS232_RXD R7

Once the I/O connections are made (the .ucf file is generated), proceed ahead to execute the
processes of Synthesize – XST, Implement Design, and Generate Programming File.

You may see a warning sign appeared after running the processes of
Synthesize and Implement Design. Ignore it.

iii. Chip-Desktop Connection

Connect the LX9 microboard to your computer and program the FPGA by following the steps
shown in section e. Device Configuration of lab session 5a. Once the program (top.bit) file is
downloaded, you will notice that the counter output is appearing on LEDs as same as it was in the
Lab5a.

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Lab 5b – Interactive Testing using External Software
Testing hardware with HU-DLDLabs-FPGA App

Now connect the FPGA board with your PC using the micro-USB cable (black in color). Check if
the serial connection with FPGA board is established with your PC by Right Clicking on My
Computer → Manage → Device Manager → Ports (COM & LPT) and verify if the Silicon
Labs CP210x USB to UART Bridge (COMx) is listed as shown in the Figure below:

Figure 5b.3. Device manager showing the Silicon Labs USB to UART bridge is assigned a COM3 port.

The Silicon Labs CP210x Windows drivers must be installed on your

computer. These drivers create virtual COM port for the serial devices
connected to your PC via USB port. It is already installed on HU DLD Labs
systems. You should have these drivers on your PC if you want to carry out the
experimentation on it.

c. Testing hardware with HU-DLDLabs-FPGA App

We are now ready to test our counter in a user-friendly manner on HU-DLDLabs-FPGA software
application. Follow the steps below:

1. Launch HU-DLDLabs-FPGA
Launch HU-DLDLabs-FPGA application by double clicking on the following HU-DLDLabs-
FPGA icon on your desktop, as shown in the image below.

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Lab 5b – Interactive Testing using External Software
Testing hardware with HU-DLDLabs-FPGA App

If the icon is not found on the desktop, search the App in Windows Program menu.

The GUI of HU-DLDLabs-FPGA software is shown in the figure below.

Figure 5b.4. HU-DLDLabs-FPGA software application for testing the hardware on chip.

2. Connection Settings
Drop down the COM Port menu and select COM5.

Every PC may have a different COM port assigned to your FPGA board. You
should select that COM port which appears in the Device Manager. In this
case, it is COM5 as shown in Figure 5b.3.

Next, drop down the Baud Rate menu and select 38400.

Now press the Connect button to start observing the output of a counter running on an FPGA
chip.

To disconnect the HU-DLDLabs-FPGA software with the FPGA board, press and hold
Disconnect button for 2 seconds.

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Lab 5b – Interactive Testing using External Software
Exercise

Exercise
Create a folder named Exercise under ..\Lab5b\ path and copy the design folder of Lab5b in it.
Now following the Lab5a tutorial, create a new project and use the copied files in it. Update these
files to incorporate the following requirements.

a. Update the counter module to count up to a value of 31.

b. Run the counter at a frequency of 1 Hz.
c. Connect the reset port to DIP Switch 4 (FPGA_DIP4).

Now download the bitstream of updated hardware on FPGA and verify the functionality on HU-
DLDLabs-FPGA App.

30
References
[1]. Avnet, “Xilinx Spartan-6 LX9 Microboard User Guide”, RevD, April 2015.
[2]. XILINX, ISE Design Suite Overview, ISE Help (v 12.2), 2010.
[3]. XILINX, XST User Guide, UG627 (v 11.3), 2009.
[4]. XILINX, PlanAhead User Guide, UG632 (v12.2), 2010.
[5]. Hasan Baig, “Jump-start to FPGA based Digital Designing and CAD Tools”, workshop presentation, 2010.
[6]. UART, https://en.wikipedia.org/wiki/Universal_asynchronous_receiver-transmitter.

31
 Digital Logic and Design
(EE-172 / CS-130)
Habib University

Lab 05 (a) and (b) – Hands on FPGA and Interactive Testing

Assessment Rubric

Name: __________________________ Student ID.: _________ Section: _______

Lab # 05 Marks Distribution:

LR2=70 LR4=30 LR7 = 20

Task # Code / Design / Data Collection / Viva
Simulation / Implementation Observation
Introduction Design Task 10 Points 10 Points 10 points
Lab Task a 10 Points - -
5(a) Task b 10 Points - -
In-Lab Task c 10 Points - -
Task d 10 Points - -
Task e 10 Points 10 Points
Task a 10 Points - 10 Points
Lab
In-Lab Task b - 10 Points -
5(b)
Task c 10 Points 10 Points 10 Points
Total 150

Lab # 05 Marks Obtained:

LR2=70 LR4=30 LR7 = 20

Task # Code / Design / Data Collection / Viva
Simulation / Implementation Observation
Introduction Design Task
Lab Task a - -
5(a) Task b - -
In-Lab Task c - -
Task d - -
Task e
Task a -
Lab
In-Lab Task b - -
5(b)
Task c
Total
 Lab Evaluation Assessment Rubric
# Assessment Elements (0<Level 1<=4)
Components are wired and
Neat and Clean Circuit didn’t show neat and clean
LR1
layout connections and minimal efforts
shown
Program/code/simulation
model/network model is not
well-documented (i.e. with no
Program/code/simulation
LR2 comments and proper variable
model/network model
names) and not efficiently
implemented and minimal
efforts shown
Unable to identify the
LR3 Troubleshooting
fault/minimal effort shown
Measurements are incomplete,
inaccurate and imprecise.
Observations are incomplete or
LR4 Data Collection
not included. Symbols, units
and significant figures are not
included
Figures, graphs, tables contain
errors or are poorly constructed,
LR5 Results & Plots
have missing titles, captions,
units missing or incorrect, etc.
All equipment/PC is not
powered off.
LR6 Clean-up
All items left at station and not
cleaned
Response shows a complete
LR7 Viva lack of understanding of
subjected task
No participation towards the
LR8 Contribution
group tasks
No summary provided. The
number/amount of tasks
LR9 Report completed below the level of
satisfaction and/or submitted
late
(4< Level 2<=6)
Components are wired with
untidy connection and
didn’t show neat and clean
connections
Program/code/simulation
model/network model (i.e.
with some comments but
has improper variable
names or vice versa) and is
implemented by
computationally complex
routine
Able to identify the fault
but unable to remove it
Measurements are somewhat
inaccurate and very
imprecise. Observations are
incomplete or recorded in a
confusing way. Major errors
using symbols, units and
significant digits
Most figures, graphs, tables
OK, some still missing
some important or required
features
Many equipment/PC is not
powered off.
Many items left at station
Response shows some
understanding of subjected
task
Slight participation towards
the group tasks
Couldn’t provide good
summary of in-lab tasks.
Some major tasks were
completed but not
explained well. Submission
on time. Some major plots
and figures provided
(6< Level 3<=8)
Few but not all Components
are wired with neat and
clean connections
Program/code/simulation
model/network model is
well-documented (i.e. with
comments and proper
variable names) but not
implemented efficiently
Able to identify the fault
but partially removes it
Measurements are mostly
accurate.
Observations are generally
complete. Minor errors
using symbols, units and
significant digits
All figures, graphs, tables
are correctly drawn, but
some have minor problems
or could still be improved
Some equipment/PC is not
powered off.
Some items left at station
Response shows substantial
understanding of subjected
task
Substantial participation
towards the group tasks
Good summary of In-lab
tasks. All major tasks
completed except few
minor ones. The work is
supported by some decent
explanations, Submission
on time, All necessary
plots, and figures provided
(8< Level 4<=10)
Complete components are
wired with neat and clean
tight connections and task
completed in due time
Program/code/simulation
model/network model is
well-documented (with
comments and proper
variable names) and task
efficiently implemented in
due time
Able to identify the fault
and able to make necessary
steps and actions to correct
it
Measurements are both
accurate and precise.
Observations are very
thorough. Includes
appropriate symbols, units
and significant digits and
task completed in due time
All figures, graphs, tables
are correctly drawn and
contain titles/captions
All equipment/PC is
powered off.
Station left neat and clean
Response shows complete
understanding of subjected
task
Outstanding participation
towards the group tasks
Outstanding Summary of
In-Lab tasks. All task
completed and explained
well, submitted on time,
good presentation of plots
and figure with proper
label, titles and captions