Académique Documents
Professionnel Documents
Culture Documents
LÓGICA COMBINACIONAL
Danilo A. García Hansen
Estructura general en VHDL
Módulos o unidades BÁSICAS de diseño
ENTITY (ENTIDAD)
Describe las entradas y salidas al bloque o sistema lógico.
ARQUITECTURE (ARQUITECTURA)
Describe como interactúan las entradas y salidas y como
funciona la lógica interna
ENTITY (ENTIDAD )
▪Modo In
▪Modo Out
▪Modo Inout
▪Modo Buffer
Ejemplos
entity funcor is
Port ( X : in STD_LOGIC;
Y : in STD_LOGIC;
Z : out STD_LOGIC);
end funcor;
entity FUNCION is
Port ( W : in STD_LOGIC;
X : in STD_LOGIC;
Y : in STD_LOGIC;
Z : in STD_LOGIC;
A : out STD_LOGIC;
B : out STD_LOGIC);
end FUNCION;
entity FUNCION2 is
Port ( W, X, Y, Z : in STD_LOGIC;
A, B : out STD_LOGIC);
end FUNCION2;
PROCESS (W, X, Y, Z)
BEGIN
IF (W AND X)='1' THEN
A<='1';
ELSE
A<='0';
END IF;
end BOOLEANA;
Tabla de Verdad (1)
----------------------------------------------------------------------------------
-- Module Name: tabla
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tabla is
Port ( A : in STD_LOGIC_VECTOR (0 to 1);
W : out STD_LOGIC); A(0) A(1) W
end tabla;
entity tabla2 is
Port ( X, Y : in STD_LOGIC; X Y W
W : out STD_LOGIC);
end tabla2;
0 0 1
architecture Arch_tabla of tabla2 is
begin 0 1 0
W<= ‘1’ WHEN (X=‘0’ AND Y=‘0’) ELSE
‘1’ WHEN (X=‘1’ AND Y=‘0’) ELSE
‘1’ WHEN (X=‘1’ AND Y=‘1’) ELSE
1 0 1
‘0’;
1 1 1
end Arch_tabla;
Tabla de Verdad (3)
----------------------------------------------------------------------------------
-- Module Name: tabla
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tabla3 is
Port ( X, Y : in STD_LOGIC; X Y W
W : out STD_LOGIC);
end tabla3; 0 0 1
architecture Arch_tabla of tabla3 is
begin 0 1 0
W<= ‘0’ WHEN (X=‘0’ AND Y=‘1’) ELSE ‘1’;
end Arch_tabla; 1 0 1
1 1 1
Multiplexor 2 a 1
---------------------------------------------------------------------------------
-- Design Name: MULTIPLEXOR 2 A 1
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2a1 is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
S : in STD_LOGIC;
Y : out STD_LOGIC);
end mux2a1;
Begin
WITH S SELECT
Y<=B WHEN '0',
A WHEN OTHERS;
end Arch_Mux21;
Multiplexor 4 a 1
---------------------------------------------------------------------------------
-- Design Name: MULTIPLEXOR 4 A 1
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4a1 is
Port ( I : in STD_LOGIC_VECTOR (3 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC);
end mux4a1;
entity deco2a4 is
Port ( S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end deco2a4;
begin
Y(0)<= '1' WHEN S="00" ELSE '0';
Y(1)<= '1' WHEN S="01" ELSE '0';
Y(2)<= '1' WHEN S="10" ELSE '0';
Y(3)<= '1' WHEN S="11" ELSE '0';
end Arch_deco2a4;
Decodificador 2 a 4 (Salidas Activas Bajo)
----------------------------------------------------------------------------------
-- Module Name: deco2a4B
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity deco2a4B is
Port ( S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end deco2a4B;
begin
Y(0)<= '0' WHEN S="00" ELSE '1';
Y(1)<= '0' WHEN S="01" ELSE '1';
Y(2)<= '0' WHEN S="10" ELSE '1';
Y(3)<= '0' WHEN S="11" ELSE '1';
end Arch_deco2a4B;
Comparador de magnitud 4 bits
-- Module Name: comparador - Arch_comp
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity comparador is
Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);
x, y, z : out STD_LOGIC);
end comparador;
begin
process (a,b)
begin
if (a>b) then
x <= '1';
y <= '0';
z <= '0';
elsif (a=b) then
x <= '0';
y <= '1';
z <= '0';
else
x <= '0';
y <= '0';
z <= '1';
end if;
end process;
end Arch_comp;
Sumador binario de 4 bits (1164)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sumador is
Port ( A,B: in STD_LOGIC_VECTOR (3 downto 0);
S : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end sumador;
end arch_sumador;
Sumador binario 4 bits (Std_logic_Arith)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SUMADOR is
Port ( A, B : in STD_LOGIC_VECTOR (3 downto 0);
SUMA : out STD_LOGIC_VECTOR (3 downto 0));
end SUMADOR;
architecture ARCH_SUMARITH of SUMADOR is
begin
SUMA <= A + B;
end ARCH_SUMARITH;
Decodificador BCD a 7 segmentos
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BCD_7_SEG is
Port ( BCD : in STD_LOGIC_VECTOR (3 downto 0);
SAL7SEG : out STD_LOGIC_VECTOR (6 downto 0));
end BCD_7_SEG;
Bibliografía:
VHDL El arte de programar sistemas digitales. David G. Maxinez, Jessica
Alcalá, CECSA- Tec de Monterrey. 2003