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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2018.2848728, IEEE
Transactions on Power Electronics
Single Input Space Vector Based Control System
for Ripple Mitigation on Single-Phase Converters
Caniggia Viana, Student Member, IEEE, Theodore Soong, Member, IEEE,
and Peter W. Lehn, Senior Member, IEEE
Abstract—Applications such as renewable energy generation,
electric vehicles and low power UPS require single-phase ac/dc
conversion. However, this conversion introduces a considerable
amount of second harmonic ripple on the dc link. If not
filtered, this distortion hinders the converter’s performance as
well as the energy quality on both the ac and dc side. To
mitigate this problem, a large electrolytic capacitor is usually
the solution of choice, which mitigates the voltage ripple, but
has drawbacks of its own, including the increased size and cost
associated with the large capacitance and the limited lifespan
of electrolytic capacitors. Alternative solutions to the problem
include integration of an active filter circuit to the converter,
which can utilize a storage element with the objective of mit-
igating power ripple. Such solutions have often been proposed
alongside a control system which is either highly complex or
relies on open-loop feed-forward techniques. This paper presents
a control system which adapts the single input space vector
concept for a single-phase application and leverages its simplicity
and closed-loop architecture, allowing the controller to perform
well in the presence of disturbances and parameter uncertainty.
Experimental results are provided to elucidate the controller’s
performance on a single-phase grid-connected photovoltaic array
application.
Index Terms—Power decoupling control, active filters, ripple
mitigation, closed-loop systems, feedback, single input space
vector.
I. I NTRODUCTION
D C power is the essence for numerous applications, in-
cluding some of the fastest growing areas of interest
in energy systems, such as battery systems, photovoltaic
applications and other renewable energy applications. In many
cases, these systems need to interface with a single-phase grid.
Particularly for relatively low-power ranges (< 10 kW) [1].
Single-phase dc/ac converters are used as a grid interface for
UPS [2], photovoltaic arrays [3], amongst others renewable
energy distributed generation. Single-phase converters are also
employed in low power ac/dc applications such as electric
vehicles charging [4].
Due to the increasing market presence of single-phase
converter applications, there has been a heightened interest in
achieving high power density while keeping a low-cost, low-
complexity topology. This trend can be observed in works such
as [5–12].
For single-phase converters, neglecting losses within the
converter, the power on the ac port equals the power on the dc
port of the converter, which results in second harmonic ripple
1 Extension of “DC ripple regulation of single-phase converters with
reduced harmonic impact”, presented at COMPEL 2017.
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1
current appearance on the dc side of the converter. Such a
ripple must be appropriately filtered, otherwise it hinders the
performance and efficiency and deteriorates the power quality
on both sides of the converter. The problem is commonly
addressed by the use of a large capacitor, typically electrolytic
[10], which has a limited lifetime [9], and has been identified
as the restricting component in achieving high power density
[13].
To avoid using an electrolytic capacitor, active filtering
methods are currently being studied to filter the second har-
monic ripple on the dc side of the converter to reduce link
capacitor requirements.
Active filtering methods are typically achieved with an
auxiliary circuit which absorbs ripple power produced from the
single-phase power transfer. This is achieved using an auxiliary
energy storage component, either a capacitor or an inductor. In
either case, the sizing and operation of the auxiliary circuit is
dictated by the second harmonic power that must be absorbed.
As such, auxiliary circuits must be designed to increase power
density with minimal additional loss. In the case of inductive
auxiliary circuits, such as [10, 14], large inductors are often
required to maintain reasonable conducted currents, which
leads to a bulky and costly solution [10]. Although inductors
offer very high reliability, capacitors are currently a better
choice for power density, cost, and weight [15, 16].
Examples of active filtering topologies using capacitive
storage for the auxiliary circuit are presented in [7, 15]. Some
topologies employ a similar design to what is shown in Fig.
1a. However, the capacitor voltage is limited to half the ac
voltage swing and imposes a strong dc component across the
capacitor preventing full component utilization. The topology
shown in Fig. 1b employs a capacitor as the energy storage
component, and the reference for the capacitor voltage is a
sinusoidal wave with the same frequency as the ac side, with
zero dc component. The efficiency is claimed to be higher
than the topologies that use an inductor as the energy storage
component, and the current stress in the two rectifier arms
does not increase.
Dc/ac single-phase converter ripple cancellation techniques
all hinge upon the creation of an appropriate reference for
the auxiliary circuit. For example, [15, 17] implement state
observer and all pass filters or consider the system an extreme
case of unbalanced system and applies adapted three-phase
technique, while [6, 11] use feedforward controllers. As a
result, the solutions tend to be a) computationally intensive,
using PLL or DFT, b) offer poor robustness not completely
eliminating the second harmonic voltage oscillation, c) de-
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Transactions on Power Electronics

idc

+ +
vac Lf 1 /2 Lf 2 /2
− − − +
+
+
Cdc vdc Cf vg
−
iac −
(a) Topology Presented in [7] (b) Topology Presented in [15] Lf 1 /2 Lf 2 /2

Fig. 1: Example of Previously Proposed Single-Phase dc/ac

Ripple Mitigation Topologies.
Fig. 2: Full-Bridge Inverter/Rectifier.

mand additional sensors, such current sensors [14], or rely on

detailed ac power information for ripple mitigation purposes, voltage is defined as vac = Vac cos(ω 0 t+δ), the ac side output
and/or d) are developed for topologies that impose dc volt- current is defined as iac = Iac cos(ω 0 t + β), and the grid
age across the capacitor [18, 19], preventing full component voltage is define as vg = Vg cos(ω0 t), having a somewhat
utilization. different angle and amplitude than vac .
In [17] the challenge of DC side second harmonic ripple Assuming that the switching and conduction losses are
is addressed for current source converters by leveraging dq- negligible, power balance across the converter input and output
frame concepts from 3-phase systems. The work of [20] terminals results in
also looks to control of unbalanced 3-phase converter for
inspiration, however, it leverages the concept of of single-input pdc = pac , (1)
space vectors, first introduced in [21]. This work expands on where
[20]. Specifically, a second harmonic space vector quantity Vac Iac Vac Iac
is formulated from the measured DC-side voltage ripple and pac = cos(φ) + cos(2ω 0 t + 2δ − φ). (2)
2 2
then regulated to zero through use of resonant control and
frequency shifting, which finally imposes a fundamental fre- As a result the power flowing through the dc side has an
quency voltage on the auxiliary capacity. average component, as well as a second harmonic power
Unlike other strategies that impose a fundamental frequency ripple, respectively,
voltage on the auxiliary capacitor [6, 7, 10, 11, 15, 22], the pro- Vac Iac
hpdc iT0 = cos(φ), (3)
posed approach employs closed loop state feedback to ensure 2
tracking accuracy in presence of parameter variations and other since
non-idealities. The simplicity of the proposed controller, allied Vac Iac
hpac iT0 = cos(φ) (4)
with the fact that it applies to any capacitor based auxiliary 2
circuit with bipolar voltage swing, makes it cross-compatible and
to different dc/ac converters with ripple mitigation [6, 11]. Vac Iac
pdc,2 = cos(2ω0 t + 2δ − φ), (5)
2
II. S YSTEM A NALYSIS since
Vac Iac
This section presents a standard single-phase dc/ac topology pac,2 = cos(2ω0 t + 2δ − φ), (6)
2
to develop an understanding of the electrical circuit behind the where
problem under analysis. Active filtering topologies are also φ = δ − β. (7)
presented to provide insight into operation of topologies that
use a zero dc voltage component across the auxiliary capacitor Equation (6) describes the second harmonic power ripple
when cancelling power ripple from a single-phase ac grid. present on the dc link and summarizes the cause of dc link
voltage ripple.
A. Full-Bridge Inverter/Rectifier
One of the simplest implementations of a bidirectional ac/dc B. Semi-Integrated VSC Ripple Mitigation
converter is the usage of the voltage source converter (VSC), There is a broad range of suitable topologies for second
shown in Fig. 2, combined with a split LCL filter to fulfill harmonic ripple mitigation at the dc side of converters, many
the IEEE 519 standard’s requirements regarding THD [23]. of which are compatible with the control system presented
Throughout this work, this circuit is used as a benchmark in this work. One of the topologies proposed to address the
topology to be compared with the ripple mitigating topologies problem in question is presented in [15]. Fig. 3 presents a
using the proposed control system. minor variant of this circuit with the inclusion of a split LCL
To understand the operation of the converter, it is assumed filter as required to meet harmonic standards. The circuit has
that the switching frequency is high enough so that an average an architecture similar to a regular three-phase VSC, thus
model can be used for analysis. In other words, only low order being potentially suited to leverage mature technologies such
harmonics are of concern. In addition, it should be noted that as three-phase intelligent power modules. With respect to the
the output voltages of all phase legs of the converter are limited benchmark topology, this solution adds two switches and an
by the available dc link voltage. The desired ac side output auxiliary capacitor, connected through a small series current

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Transactions on Power Electronics

limiting inductor. The auxiliary capacitor is responsible for the left to the right are expressed by
providing second harmonic power which is designed to cancel Vdc vac
out the power ripple on the dc side of the converter while vu =− − vaux (13)
2 2
boasting full component utilization. Since it operates with full
Vdc vac
voltage swing across Caux , it allows for a reduction in net vv = − (14)
capacitance and ultimately increased power density. 2 2
Vdc vac
vw = + . (15)
2 2
idc
It is clear that these voltages must be within 0V and Vdc to
−
vaux
+ −
vac
+
Lf 1 /2 Lf 2 /2 avoid saturation, i.e. equation (13) implies that that
+
Cdc vdc Laux Caux
iaux Cf
+
vg |2vaux + vac | < Vdc ∀ t (16)
−
−
− +
vC,aux iac Lf 1 /2 Lf 2 /2 such that
|2Vaux cos(ω 0 t + α) + Vac cos(ω 0 t + δ)| < Vdc ∀ t.
(17)
Fig. 3: Power Ripple Compensation Circuit with Semi- From (17), it directly follows that
Integrated Auxiliary Branch. 
 (2Vaux cos(α) + Vac cos(δ)) cos(ω0 t)−
 (18)
(2Vaux sin(α) + Vac sin(δ)) sin(ω0 t) < Vdc ∀ t
The auxiliary voltage is defined as vaux = Vaux cos(ω 0 t + and thus
α). To determine the theoretically desired auxiliary voltage
(i.e. the values of Vaux and α) necessary to achieve second (2Vaux cos(α) + Vac cos(δ))2 +(2Vaux sin(α) + Vac sin(δ))2 < Vdc
2

(19)
harmonic power cancellation, power balance can be applied
must hold.
to ensure that the power delivered to the capacitor cancels the
Solving the quadratic constrain, one can show that
second harmonic on the ac side of the converter, thus achieving
constant power on the dc port. It is desired that 2 2 2
Vaux + Vaux Vac cos(α − δ) + Vac − Vdc <0 (20)
pdc,2 = 0, (8) and
 s 
2
such that Vac  Vdc
Vaux < −cos(α − δ) + − sin2 (α − δ) (21)
pac + paux = hpac iT0 (9) 2 Vac

where pac is the instantaneous power at the ac port, hpac iT0 Observing the possibilities derived in (12) in light of (21)
is the average power at the ac side, given by (4), and paux it becomes clear that the control should set δ = α + φ2 + 3π 4
is the instantaneous power delivered to the auxiliary filter in order to maximize the auxiliary voltage swing.
capacitor. The power flowing through Caux , assuming a small An interesting characteristic of this approach is the sep-
inductance, can be approximated by aration of dc link high frequency switching harmonics and
second harmonic power ripple. Practically, this translate into
ω0 2
paux = − Caux Vaux sin(2ω 0 t + 2α). (10) Cdc being potentially used to filter switching ripple only,
2 while Caux is solely used for second harmonic power ripple.
As a direct consequence of (9), it is desired that paux + Therefore, from (11), Caux may be sized by
pac,2 = 0 to provide ripple cancellation, where pac,2 for Vac Iac
this system remains as expressed in (6). Thus the auxiliary Caux ≥ 2
, (22)
ω0 Vaux,max
capacitor can be sized by inserting (2), (3), and (10) into (9),
which results in where Vaux,max can be obtained by (12) and (21), taking in
Vac Iac cos (2ω 0 t + 2δ − φ) = consideration the power factor range required as a function of
 π (11) the application and applicable code.
2
ω 0 Caux Vaux cos 2ω 0 t + 2α − ,
2
showing that the ripple power delivered to the auxiliary circuit C. Double Full-Bridge Inverter/Rectifier
capacitor will cancel the dc side ripple power induced by Another way to mitigate the second harmonic power ripple
the single-phase ac power when the cosines’ phases equate. through the dc side of the converter is the topology presented
Therefore, two solutions exist for α: in [6] and [8], and shown in Fig. 4. It comprises two full-
φ bridges; one to interface the single-phase grid and the other
 δ − 2 + π4


α= or (12) to interface an auxiliary capacitor through a small inductor, a


δ − φ2 − 3π . similar operation principle to what was discussed in Section
4
II-B.
There are numerous ways of implementing voltages that When compared to the Semi-Integrated VSC, the double
satisfy (11). Here, the output voltages of each half-bridge, from full-bridge can achieve a smaller capacitance, due to the wider

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Transactions on Power Electronics

0.9
idc
0.85
vaux vac Lf 1 /2 Lf 2 /2
− + − +
0.8
+
Caux +
Cdc vdc Laux Cf vg
iaux − 0.75
−
− +
vC,aux iac Lf 1 /2 Lf 2 /2 0.7

0.65

0.6

Fig. 4: Power Ripple Compensation Circuit with Full-Bridge 0.55

Auxiliary Branch, Topology Introduced in [6].
0.5

0.45
1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2
range of Vaux which is only limited by the dc link voltage.
Thus, the minimum auxiliary capacitance for this circuit can (a) Normalized Applicable Auxiliary Vaux for Semi-Integrated VSC
4.5
be expressed as
Vac Iac 4
Caux > 2 . (23)
ω0 Vdc
3.5
However, the smaller auxiliary capacitance comes at the ex-
pense of 2 extra switches and no reduction in the required 3

energy storage is achieved. The small capacitance value is

2.5
achievable, but results in a commensurately larger capacitor
voltage rating. 2

Fig. 5 presents a comparison between the minimum capac-

1.5
itance in both topologies, as well as the maximum applicable
Vaux for the semi-integrated VSC. For the figure in question 1
1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2
Caux of Semi-Integrated VSC
C0 = . (24) (b) Normalized Minimum Auxiliary Capacitance
Caux of Double Full Bridge
Fig. 5: Capacitance Requirement Comparison Between Semi-
Integrated VSC and Double Full-Bridge.
III. C ONTROL D ESIGN
The control system is designed aiming to achieve dc voltage
regulation while ensuring second harmonic ripple cancellation 5) Oscillator (OSC): The oscillator, discussed in [25],
on the dc link through the generation of a reference for the capable of generating a voltage reference at the same
angle as the grid voltage and 90◦ phase shifted. The
voltage across the auxiliary circuitry. The first objective is oscillator is defined as
achieved through the standard use of a PI and an internal loop       
d vack −ksync ω0 vack ksync
comprised of of a resonant current controller as discussed in = + vac
dt vac⊥ −ω0 0 vac⊥ 0
[24]. The ripple regulation is the main focus of this paper and  
 vack
must process a second harmonic voltage error and provide a (25)

1 −j
vac⊥
fundamental frequency voltage reference in order to ensure ~
uac = q ,
2 2
second harmonic auxiliary power flow. vack + vac⊥
The proposed controller, is shown in Fig. 6. The entire
where
controller can be divided into five parts.
• ksync controls a trade-off between rate of synchronization
1) Voltage controller (VC): The active power control is and high frequency noise rejection,
achieved by controlling the dc side voltage vdc which is • vack is a signal with the same amplitude and phase as the

regulated via Proportional-Integral (PI) control. VC sets
∗ • vac⊥ is a signal with the same amplitude and 90 phase
the reference magnitude |iac | .
2) Current controller (IC): The current , iac is regulated
via proportional resonant control.
3) Ripple Controller (RC): The regulation of the dc side
power ripple is discussed in detail in Section III-A. The
output of RC, which is used as the reference for the
auxiliary capacitor voltage, is a fundamental frequency
signal constructed from the second harmonic ripple,
through frequency shifting.
4) Auxiliary Voltage Controller (AVC): The auxiliary
voltage, vaux , is controlled by a resonant controller
which includes lead-lag compensation.
fundamental component of vac , and
◦
shift as the fundamental component of vac .
• ~uac is a unit space vector with the same angle as the grid
voltage, equivalent to ejω0 t .
To achieve a user-defined displacement power factor angle for
the ac current, a phase shift, β, must be introduced.
A. DC Link Ripple Reduction Controller
As discussed in Section II-C, a fundamental frequency
voltage is imposed on the auxiliary capacitor. The AVC,
comprising a resonant controller with lead-lag compensation,
is responsible for providing this compensation. The crucial

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Transactions on Power Electronics

∗ ∗
Vdc e Ki
|iac | i∗ac ei Kr1 s ∗
vac
+ + Kp × +
−
s
− s2 + ω02 ∗
vaux Plant / Grid
vdc vdc Control iac iac Control
ejβ
vg ~uac
(25) × Re(u)

Oscillator vdc regulation

ripple mitigation

∗
Kr2 2ω 0 ~v1 ~v2 vC,aux eC,aux K(s − z1 ) s2 + 2ζωz s + ωz2
2 + × Re(u) + ·
s2 + (2ω 0 ) − s − p1 s2 + ω02
vC,aux vC,aux Control
Kr2 s
2 ×
s2 + (2ω 0 )

-j

Ripple Control

Fig. 6: Proposed Controller Architecture.

step in regulating the ripple voltage is the construction of a as

fundamental frequency reference from a second harmonic error
signal. This is achieved by adapting single-input space vector
theory [21] from three-phase to single-phase applications. The
methodology can be understood as filtering the error in such a
way to isolate the second harmonic ripple, which is then used
to generate a complex exponential that can be easily frequency
shifted to the fundamental harmonic.
The main ripple component present on the dc port of the
benchmark topology is at the second harmonic frequency. The
second harmonic error due to the power ripple, has the form
e = M2 cos(2ω0 t)
 j2ω0 t
e e−j2ω0 t

(26)
= M2 + ,
2 2
which is presented in the frequency spectrum shown in Fig.
7a.
To transform the signal at frequency 2ω0 into one at the
requisite frequency of ω0 , a frequency shift can be applied by
multiplying the spectrum by ejω0 t . However, this transforma-
tion would result in a fundamental frequency component and
an undesired third harmonic as shown in Fig. 7b. To prevent
the appearance of a third harmonic component, a single-input
space vector, can be used to first isolate the negative sequence
second harmonic. This step consists of designing resonant
controllers using the Laplace transform of cosine and sine
waves to produce quadrature signals at 2ω0 . These transfer
functions are designed based on the internal model principle
to enable proper operation while driving the ripple to zero
[26]. These signal are appropriately added, as shown in Fig.
6, to isolate the desired space vector, which can be expressed
~v1 = Kr2 M2 [cos(2ω0 t) − jsin(2ω0 t)]
(27)
= Kr2 M2 e−j2ω0 t ,
shown in Fig. 7c. The signal ~v1 is then modulated by ejω0 t ,
derived using equation (25), yielding
~v2 = ~v1 ejω0 t = Kr2 M2 e−jω0 t , (28)
presented in Fig. 7d. Finally, ~v2 is passed through a block
which takes only its real value to generate
∗
vC,aux = Kr2 M2 cos(ω0 t), (29)
resulting in only a fundamental frequency term. The final
output of the RC block can be seen in Fig. 7e.
This setup allows for the use of vC,aux as a control variable
in order to ensure (11) holds true, thus, achieving power ripple
cancellation.
The ripple control is performed in a closed-loop fashion,
such that the information regarding the phase of the ripple
will be used to determine the phase of the voltage command
to be imposed across the auxiliary capacitor. This property
eliminates the necessity to estimate ac power flow or voltage
phase, allowing the ac terminal to be abstracted and facilitating
the construction of plug-and-play solutions that only take into
consideration dc-link voltage.
B. Auxiliary Voltage Control
For the vC,aux control, an internal loop comprised of a
PR controller capable of tracking 60 Hz sinusoidal signals.
However, due to the lack of damping in the system, it can
be challenging to design a regular PR controller capable of
stabilizing the system. To address this issue, an extra lead

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Transactions on Power Electronics

e(ω)

ω
−2ω0 2ω0

(a) Frequency Spectrum of Signal e

e(ω)ejω0 t

ω
−ω0 3ω0

(b) Frequency Spectrum of e(ω)ejω0 t

~v1 (ω)

VC,aux (s)
ω Fig. 8: Root Locus Plot For the Plant Vaux (s) and Respective
−2ω0 Control System.
(c) Frequency Spectrum of Signal ~v1 TABLE I: Parameters Used in Simulation (Semi-Integrated
~v2 (ω) VSC - Benchmark Topology Comparison)

Parameter Active Filter Regular Topology

ω
hpdc i 2000 W 2000 W
−ω0
cos(φ) 1 1
(d) Frequency Spectrum of Signal ~v2 Cdc 480 µF 4800 µF
∗ Vdc 200 V 200 V
vC,aux (ω)
Vac 120 Vrms 120 Vrms
Lf 1 1.5 mH 1.5 mH
ω Lf 2 0.5 mH 0.5 mH
−ω0 ω0 Cf 5 µF 5 µF
Laux 1 mH -
∗
(e) Frequency Spectrum of Signal vC,aux Caux 480 µF -
fs 10 kHz 10 kHz
Fig. 7: Signals Inside Ripple Control in Frequency Domain.

compensation is included, with the objective of attracting the
root locus towards the left-half plane. The resulting root locus
plot is shown in Fig. 8. The controller‘s transfer function is
shown in (30).
K(s − z1 ) s2 + 2ζωz s + ωz2
C(s) = · (30)
s − p1 s2 + ω02
IV. S IMULATIONS
This section presents the implementation of the proposed
control on the topology presented in Fig. 3 in Plecs™. The
input is assumed to be a constant current source which
emulates the behavior of a solar power plant. For comparison,
the system is compared with the benchmark circuit with
the topology presented in Fig. 2. For the purpose of this
simulation, the parameters are presented on Table I.
Considering the negligible value of Cf , the data presented
in Table I shows an 80% reduction of the total capacitance and
even higher reduction in capacitive energy storage, since the
auxiliary voltage peaks at approximately 153.5 V as opposed
to the 200 V across Cdc . In spite of the size and cost allocated
for capacitive filtering, the active filtering topology regulated
by the proposed controller achieves a better ripple mitigation,
displaying much less variation of the regulated voltage. Fig. 9
provides a comparison between the amplitude of the voltage
variations as well as the waveforms involved.
The reduction in filtering requirements occurs due to the
fact that the power ripple is accommodated by the auxiliary
capacitor, limiting the power variation that is experienced by
the dc link. This process can be observed in Fig. 10. The
power delivered to the auxiliary capacitor, as described in
(10), has zero average, and the same frequency as the power
ripple. When the control is in place, the amplitude and phase
of the auxiliary power will to peak approximately when the
ac power is on a valley and vice-versa. It is still possible
to see some sinusoidal component in the sum of powers.
This residual oscillation is due to the compensation of the
sinusoidal energy storage through the inductor Laux , since
the controller directly regulates the dc voltage ripple to zero,
second harmonic energy consumed by Laux and/or LCL filter
components do not influence steady-state performance.
The power at the dc side is approximately the summation of

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Transactions on Power Electronics

203
10
202
8
201
6
200

4
199

198 2

197 0
0 0.005 0.01 0.015 0.02 0 0
2 0
3 0
4 0
5 0
6 0
7 0
8 0
9 0
10 0

(a) Benchmark
203
Fig. 11: Harmonic Content of the Current on the DC Link.

202
sient. After the system reaches steady-state. At time t = 0.1 s
201 the ripple mitigation strategy is turned on, and after after a
200
short transient ceases, at approximately t = 0.5 s, the active
power decoupling is turned off, and the system returns to its
199 original ripple profile.
198 210
197
0 0.005 0.01 0.015 0.02
200
(b) Active Filtering
Fig. 9: DC Link Voltage Waveform for Simulated Topologies, 190
9a) Benchmark Topology, 9b) Active Filtering Topology with 0 0.1 0.2 0.3 0.4 0.5
Proposed Control Scheme with 80% Reduction in net dc side
Capacitance.
ON

4000

3000

2000 OFF
1000
0 0.1 0.2 0.3 0.4 0.5

0
Fig. 12: Ripple Mitigation Turn ON/OFF Transient Response.
-1000

-2000

0 0.005 0.01 0.015 0.02 V. E XPERIMENTAL R ESULTS

Fig. 10: Instantaneous Power on the AC port, Auxiliary
Capacitor and Summation.
both these powers. The difference is the combination of the
instantaneous power on the filter components, as previously
mentioned, the auxiliary inductor, and the switching losses.
These powers are mainly on high frequencies, having consid-
erably low impact on the dc link voltage.
The impact of the controller can be seen in Fig. 11. The
benchmark topology shows a high second harmonic current
component in idc , whereas for the active filtering topology,
the controller ensures the mitigation of this ripple.
A transient simulation is performed to illustrate the system’s
behavior. Fig. 12 shows the ripple mitigation turn on/off tran-
The topology displayed in Fig. 3 was replicated with a solar
array on the dc port while a single-phase grid was connected
to the ac side of the converter, as presented in Fig. 13. A real-
time controller was integrated to the circuit with the goal of
providing regulation as proposed in this work. A similar setup
was assembled with the benchmark circuit showed in Fig. 2
for comparison.
The control technique presented in this paper allows for an
aggressive dc link capacitor reduction, which may lead the
converter to have little energy to accommodate power vari-
ations originating from step-like dc disturbances or changes
in reference voltage. In that sense, photovoltaic generation is
an example of a well suited application, since transients are
relatively slow and ramp-shaped.
The parameters utilized for the experimental verification of
the proposed method can be seen in Table II. The experiment

0885-8993 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2018.2848728, IEEE
Transactions on Power Electronics

idc when the active filtering control is in place (Fig. 14b) in

ipv
vaux vac Lf 1 /2 Lf 2 /2 comparison to the benchmark topology (Fig. 14a), despite a
− + − +
five-fold considerable capacitor reduction.
+
Caux +
Cdc vdc Laux Cf vg
iaux −
−
− + 300
vC,aux iac Lf 1 /2 Lf 2 /2

250

(a) Schematic
200
-0.06 -0.04 -0.02 0 0.02 0.04 0.06

(a) Benchmark
300

250

200
-0.06 -0.04 -0.02 0 0.02 0.04 0.06

(b) Active Filtering

300

250

(b) Actual Setup

200
-0.06 -0.04 -0.02 0 0.02 0.04 0.06
Fig. 13: Power Ripple Compensation Circuit with Semi-
Integrated Auxiliary Branch Fed by Photovoltaic Array. (c) Reduced Capacitor - Ripple Mitigation Off
Fig. 14: DC Link Voltage Waveform Measured from Imple-
uses the same set of parameters that are used in Section mented Topologies, 14a) Benchmark Topology, 14b) Active
IV, except for the dc link voltage. Since the solar array is Filtering Topology with Proposed Control Scheme with 80%
connected directly to the converter, the dc link voltage is kept Reduction in net dc side Capacitance, 14c) Reduced Capacitor
variable to provide the degree of freedom needed to achieve With Active Ripple Mitigation Control Turned Off.
MPPT of the solar array. The energy storage calculation uses
the maximum voltage to which the capacitor is subjected and The ac port current is shown in Fig. 15. For both cases, the
the capacitance value, and computes current THD index is below the 5% as specified in IEE519
1 [23].
CV 2 .
E= (31)
2 To achieve the displayed behavior, as mentioned in Section
This section presents the results measured from the described III, the ripple controller generates a reference voltage for the
experiment. auxiliary capacitor VC,aux , while the auxiliary voltage con-
troller is responsible to ensure this reference is tracked. This
TABLE II: Parameters Used in Experimental Verification voltage reference must comply with the angle requirements
(Semi-Integrated VSC - Benchmark Topology Comparison). state in (12). Fig. 16 shows vC,aux and iac , under unit power
factor.
Parameter Active Filter Regular Topology
hpdc i 2000 W 2000 W
cos(φ) 1 1 A. Transient Analysis
Cdc 470 µF 4720 µF While the transient requirements are not particularly strin-
Vdc variable variable gent for photovoltaic applications, reactive power injection
Vac 120 Vrms 120 Vrms might be required. A review of currently active standards is
Lf 1 1.5 mH 1.5 mH presented in [27] and is used to design a test case where
Lf 2 0.5 mH 0.5 mH the system is subjected to a large displacement power factor
Cf 5 µF 5 µF transient. The power factor requested is changed in a stepwise
Laux 1 mH - fashion from 0.90 capacitive to 0.90 inductive at t = 0s. Fig.
Caux 480 µF - 17 shows the system response to the applied transient.
fs 10 kHz 10 kHz The reference change causes an immediate phase shift in
Edc + Eaux 16.5 J 109.1 J ripple power, which transiently appears on the dc voltage. As
time passes, the ripple controller adjusts the voltage reference
The dc link voltage can be seen in Fig. 14. It is possible amplitude and angle until second harmonic component is
to notice that the voltage presents a commensurable ripple mitigated.

0885-8993 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2018.2848728, IEEE
Transactions on Power Electronics

20
100
0
10 -100
-0.1 0 0.1 0.2 0.3 0.4

0 10
0
-10
-10
-0.1 0 0.1 0.2 0.3 0.4

-20 220

200
-0.06 -0.04 -0.02 0 0.02 0.04 0.06
-0.1 0 0.1 0.2 0.3 0.4
(a) Benchmark 100
20 0
-100
10 -0.1 0 0.1 0.2 0.3 0.4

0 Fig. 17: Transient Response of the System to a Step in Reac-

tive Power Requirement, from 0.9 Inductive to 0.9 Capacitive.
-10

fluctuations in either the auxiliary inductor or the ac filtering

-20 components. The execution of the proposed controller requires
-0.06 -0.04 -0.02 0 0.02 0.04 0.06 only a single additional sensor to measure the auxiliary voltage
vaux for feedback. In addition, the proposed control scheme
(b) Active Filtering is closed-loop and does not rely upon precise parameter
information, hence it is robust to component variance and
Fig. 15: ac Port Current Waveform Measured from Imple-
aging. These advantages make the approach easily compatible
mented Topologies, 15a) Benchmark Topology, 15b) Active
with different ripple mitigating ac/dc bidirectional converter
Filtering Topology with Proposed Control Scheme with 80%
circuits, provided that the voltage applied to the capacitor can
reduction in net dc side capacitance.
assume both polarities.
The proposed control was implemented on an active filtering
200 40
topology in simulation using Plecs™ and the claim of circuit
ripple reduction capability with considerable reduction in ca-
100 20 pacitor energy storage has been verified through the simulation
results.
0 0 As a proof of concept, the proposed controller was im-
plemented with an active filtering topology which allowed
-100 -20
a considerable capacitance reduction while maintaining a
similar ripple level, fully validating the capacitive energy
storage minimization claims made throughout this work, with
-200 -40
-0.06 -0.04 -0.02 0 0.02 0.04 0.06 experimental implementation energy storage reduction of 85%
alongside with a net capacitance reduction of 80% without
Fig. 16: Auxiliary Capacitor Voltage and Output Current. increased ripple penalty. While this reduction is topology and
application dependent, the proposed control scheme presents a
solution that simultaneously minimizes sensory and computa-
VI. C ONCLUSION tional requirements while providing robustness and simplicity.
The system regulated a PV solar inverter which was operated
This work presents a widely applicable control strategy
at different displacement factors showing that the system is
capable of regulating second harmonic ripple on the dc side
readily expandable to allow for user-defined reactive power
of single-phase dc/ac bidirectional converters. The presented
supply.
controller adapts the single-input space vector concept to
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Caniggia Viana (S’17) received the B.A.Sc. degree
in electrical engineering from the Federal Univer-
sity of Rio Grande do Norte, Natal-RN, Brazil, in
2017 and is currently working toward the M.A.Sc.
degree in electrical engineering at the University of
Toronto.
His research interests include electric vehicles
integrated driving and charging, fast charging, power
electronics, active power decoupling, and DC micro-
grids.
Theodore Soong Theodore Soong (S’11/M’16) re-
ceived the B.A.Sc. degree in engineering science in
2009, and M.A.Sc. and Ph.D. degree in electrical
engineering in 2012 and 2015, respectively, from
the University of Toronto, Toronto, ON, Canada.
He is currently a Senior Research Associate at the
University of Toronto pursuing his research interests
in integration of renewable resources to the grid, and
power electronic systems in electric vehicles.
Peter W. Lehn (SM’05) received the B.Sc. and
M.Sc. degrees in electrical engineering from the
University of Manitoba, Winnipeg, MN, Canada, in
1990 and 1992, respectively, and the Ph.D. degree
from the University of Toronto, Toronto, Canada, in
1999.
He joined the faculty at the University of Toronto,
in 1999. He spent six months as Visiting Professor
at the University of Erlangen- Nuremberg, in 2001.
His research interests include HVDC technologies,
grid integration of storage and renewables, power
electronics for electric vehicles and theoretical analysis of power electronic
systems.
Dr. Lehn is currently an Editor of the IEEE Transactions On Energy
Conversion.