library ieee;

use ieee.std_logic_1164.all;

entity tb_LAB23 is
end tb_LAB23;

architecture tb of tb_LAB23 is

component LAB23
port (CLK : in std_logic;
RESETN : in std_logic;
WR_RD : in std_logic;
DIR : in std_logic_vector (2 downto 0);
DIN : in std_logic_vector (3 downto 0);
SEG : out std_logic_vector (6 downto 0);
DISP : out std_logic_vector (7 downto 0));
end component;

signal CLK : std_logic;

signal RESETN : std_logic;
signal WR_RD : std_logic;
signal DIR : std_logic_vector (2 downto 0);
signal DIN : std_logic_vector (3 downto 0);
signal SEG : std_logic_vector (6 downto 0);
signal DISP : std_logic_vector (7 downto 0);

constant TbPeriod : time := 100 ns; -- EDIT Put right period here
signal TbClock : std_logic := '0';
signal TbSimEnded : std_logic := '0';

begin

dut : LAB23
port map (CLK => CLK,
RESETN => RESETN,
WR_RD => WR_RD,
DIR => DIR,
DIN => DIN,
SEG => SEG,
DISP => DISP);

-- Clock generation
TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';

-- EDIT: Check that CLK is really your main clock signal

CLK <= TbClock;

stimuli : process
begin
-- EDIT Adapt initialization as needed
WR_RD <= '0';
DIR <= (others => '0');
DIN <= (others => '0');
RESETN <= '1';

wait for 100 ns;

WR_RD <= '0';
DIR <= "001";
DIN <="0010" ;
 RESETN <= '1';
wait for 100 ns;
WR_RD <= '0';
DIR <= "010";
DIN <="0001" ;
RESETN <= '0';
wait for 100 ns;
WR_RD <= '0';
DIR <= "011";
DIN <="0011" ;
RESETN <= '1';
wait for 100 ns;
WR_RD <= '1';
DIN <="0011" ;
wait for 100 ns;
WR_RD <= '1';
DIN <="0010" ;
-- Reset generation
-- EDIT: Check that RESETN is really your reset signal
RESETN <= '1';
wait for 100 ns;
RESETN <= '0';
wait for 100 ns;
RESETN <= '1';
wait for 100 ns;
RESETN <= '1';
wait for 100 ns;
RESETN <= '0';
wait for 100 ns;

-- EDIT Add stimuli here

wait for 100 * TbPeriod;

-- Stop the clock and hence terminate the simulation

TbSimEnded <= '1';
wait;
end process;

end tb;