library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity ctrlunit is
port(clk,en:in std_logic;ir:in std_logic_vector(31 downto 0);
mread,mwrite:out std_logic;zf,cf:in std_logic; reg_read:out std_logic;reg_write:out
std_logic;
alu_ctrl:out std_logic_vector(2 downto 0);alu_src:out std_logic;inc_pc:out std_logic;
ir_read:out std_logic);
end ctrlunit;
architecture Behavioral of ctrlunit is
component statemachine is
Port ( clk,en : in STD_LOGIC;
ir:in std_logic_vector(31 downto 0);zf,cf: in STD_LOGIC;
z : out STD_LOGIC_vector(3 downto 0));
end component;
component memoryctrl is
Port ( mclk : in STD_LOGIC;
mread,mwrite:out std_logic;
state : in STD_LOGIC_vector(3 downto 0));
end component;
component decoder is
Port ( opcode:in std_logic_vector(7 downto 0);
state:in std_logic_vector(3 downto 0);reg_read:out std_logic;reg_write:out std_logic;
alu_ctrl:out std_logic_vector(2 downto 0);alu_src:out std_logic;inc_pc:out std_logic;
ir_read:out std_logic);
end component;
signal t:std_logic_vector(3 downto 0);
begin
l1:statemachine port map(clk=>clk,en=>en,ir(31 downto 0)=>ir(31 downto 0),zf=>zf,cf=>cf,z=>t);
l2:memoryctrl port map(mclk=>clk,state(3 downto 0)=>t(3 downto
0),mread=>mread,mwrite=>mwrite);
l3:decoder port map(opcode=>ir(31 downto 24),state=>t,reg_read=>reg_read,reg_write
=>reg_write,alu_ctrl=>alu_ctrl,
alu_src=>alu_src,inc_pc=>inc_pc,ir_read=>ir_read);
end Behavioral;

// STATE GENERATOR :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity statemachine is
Port ( clk,en : in STD_LOGIC;
 ir:in std_logic_vector(31 downto 0);zf,cf: in STD_LOGIC;
z : out STD_LOGIC_vector(3 downto 0));
end statemachine;
architecture Behavioral of statemachine is
type state_type is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15);
signal ypre,ynxt:state_type; signal s:std_logic;
signal a:std_logic_vector(1 downto 0);signal p,t:std_logic_vector(1 downto 0);
begin
process(clk,en)
begin
if (en='0' ) then
ypre<=s15;
elsif(rising_edge(clk) and en='1') then
ypre<=ynxt;
end if;
end process;
process(ir,a,clk)
begin
if (ir(31 downto 24)="00000010"
or ir(31 downto 24)="00000000"
or ir(31 downto 24)="00011000"
or ir(31 downto 24)="00011010"
or ir(31 downto 24)="11110110"
or ir(31 downto 24)="11110010"
or ir(31 downto 24)="11110110"
or ir(31 downto 24)="11110110"
or ir(31 downto 24)="11111000") then
a<="00" ; -- arithmetic statements
elsif (ir(31 downto 24)="10101101" or ir(31 downto 24)="10101100"
or ir(31 downto 24)="10101010" or ir(31 downto 24)="10101011") then
a<="01" ;--memory statements
elsif (ir(31 downto 24)="11101010"
or(ir(31 downto 24)="01110100") or ir(31 downto 24)="01110101" or ir(31 downto
24)="11111110") then
a<="10" ;--unconditional and conditional statements
end if;
end process;
process(ypre,a,clk)
begin
case ypre is
when s0=>
ynxt<=s1;z<="0000";s<='1';
when s1=>
s<='0';
if(a="00") then
ynxt<=s2;z<="0001";s<='1';
elsif(a="01") then
ynxt<=s3;z<="0001";s<='1';
elsif(a="10") then
z<="0001";ynxt<=s4;s<='1';
end if;
when s2=>
s<='0';
if ((ir(23 downto 22) = "00") and (ir(21 downto 20) ="00" )) then
p<="00";
elsif ((ir(23 downto 22) ="00" and ir(21 downto 20) /= "00")
or (ir(23 downto 22) /="00" and ir(21 downto 20) = "00")) then
p<="01";
elsif ((ir(23 downto 22) /="00") or (ir(21 downto 20) /= "00" )) then
p<="10";
end if;
if(p <="00" ) then
ynxt<=s14;z<="0010";s<='1';
elsif(p <="01" ) then
ynxt<=s13;z<="0010";s<='1';
elsif(p <="10" ) then
ynxt<=s12;z<="0010";s<='1';
else
ynxt<=s0;z<="0010";s<='1';
end if;
when s3=>
s<='0';
if (ir(31 downto 24) = "10101101" or ir(31 downto 24) = "10101100") then
ynxt<=s7;z<="0011";s<='1';
elsif(ir(31 downto 24) = "10101011" or ir(31 downto 24) = "10101010") then
ynxt<=s10;z<="0011";s<='1';
else
ynxt<=s0;z<="0011";s<='1';
end if;
when s4=>
s<='0';
if (ir(31 downto 24)="01110100" or ir(31 downto 24)="01110101" ) then
ynxt<=s5;z<="0100";s<='1';
elsif(ir(31 downto 24)="11101010") then
ynxt<=s6;z<="0100";s<='1';
else
ynxt<=s0;z<="0100";s<='1';
end if;
when s5=>
s<='0';
if(ir(31 downto 24)="01110100" and (zf='0') and (cf='0') ) then
ynxt<=s6;z<="0101";s<='1';
elsif( ir(31 downto 24)="01110101" and (zf /='0') ) then
ynxt<=s6;z<="0101";s<='1';
else
ynxt<=s0;z<="0101";s<='1';
end if;
when s6=>
s<='0';
ynxt<=s0;z<="0110";s<='1';
when s7=>
s<='0';
if(s='1') then
ynxt<=s8;z<="0111";s<='1';
else
ynxt<=s7;z<="0111";s<='0';
end if;
when s8=>
s<='0';
if(s='1') then
ynxt<=s9;z<="1000";s<='1';
else
ynxt<=s8;z<="1000";s<='0';
end if;
when s9=>
if(s='1') then
ynxt<=s0;z<="1001";s<='1';
else
ynxt<=s9;z<="1001";s<='0';
end if;
when s10=>
if(s='1') then
ynxt<=s11;z<="1010";s<='1';
else
ynxt<=s10;z<="1010";s<='0';
end if;
when s11=>

if(s='1') then
ynxt<=s0;z<="1011";s<='1';
else
ynxt<=s11;z<="1011";s<='0';
end if;
when s12=>
s<='0';
ynxt<=s13;z<="1100";s<='1';
when s13=>
s<='0';
ynxt<=s14;z<="1101";s<='1';
when s14=>
if(s='1') then
ynxt<=s15;z<="1110";s<='1';
else
ynxt<=s14;z<="1110";s<='0';
end if;
when s15=>
if(s='1') then
ynxt<=s9;z<="1111";s<='1';
else
ynxt<=s15;z<="1111";s<='0';
end if;
when others=>
ynxt<=s0;
end case;
end process;
end Behavioral;

// MEMORY GENERATOR :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity memoryctrl is
Port ( mclk : in STD_LOGIC;
mread,mwrite:out std_logic;
state : in STD_LOGIC_vector(3 downto 0));

end memoryctrl;

architecture Behavioral of memoryctrl is

begin
process(mclk)
begin
if(state="1000") then
mread<='1';mwrite<='0';
elsif(state="1001") then
mwrite<='1';mread<='0';
elsif(state="1010") then
mread<='1';mwrite<='0';
elsif(state="1011") then
mwrite<='1';mread<='0';
elsif(state="1100") then
mread<='1';mwrite<='0';
elsif(state="1101") then
mread<='1';mwrite<='0';
end if;
end process;
end Behavioral;

// DECODER :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decoder is
Port ( opcode:in std_logic_vector(7 downto 0);
state:in std_logic_vector(3 downto 0);reg_read:out std_logic;reg_write:out std_logic;
alu_ctrl:out std_logic_vector(2 downto 0);alu_src:out std_logic;inc_pc:out std_logic;
ir_read:out std_logic);
end decoder;

architecture Behavioral of decoder is

begin
process(state,opcode)
begin
if(state="0000") then
alu_ctrl<="000";--idle state
reg_read<='0';
reg_write<='0';
alu_src<='0';
inc_pc<='1';ir_read<='1';
elsif(state="0001") then
alu_ctrl<="110";--sub
reg_read<='0';
reg_write<='0';
alu_src<='0';
inc_pc<='0';ir_read<='0';
elsif(state="0010") then
alu_ctrl<="110";--sub
reg_read<='0';
reg_write<='0';
alu_src<='0';
inc_pc<='0';ir_read<='0';
elsif(state="0011") then
alu_ctrl<="110";--sub
reg_read<='1';
reg_write<='0';
alu_src<='0';
inc_pc<='0';ir_read<='0';
elsif(state="0100") then
alu_ctrl<="110";--sub
reg_read<='1';
reg_write<='0';
alu_src<='0';
inc_pc<='0';ir_read<='0';
elsif(state="0101") then
alu_ctrl<="000";--idle state
reg_read<='0';
reg_write<='0';
alu_src<='0';
inc_pc<='0';ir_read<='0';
elsif(state="0110") then
alu_ctrl<="000";--idle state
reg_read<='0';
reg_write<='0';
alu_src<='0';
inc_pc<='0';ir_read<='0';
elsif(state="0111") then
alu_ctrl<="010";--add
reg_read<='1';
reg_write<='1';
alu_src<='1';
inc_pc<='0';ir_read<='0';
elsif(state="1000") then
alu_ctrl<="000";--idle state
reg_read<='1';
reg_write<='1';
alu_src<='0';
inc_pc<='0';ir_read<='0';
elsif(state="1001") then
alu_ctrl<="000";--idle
reg_read<='1';
reg_write<='0';
alu_src<='0';
inc_pc<='0';ir_read<='0';
elsif(state="1010") then
alu_ctrl<="010";--add
reg_read<='1';
reg_write<='1';
alu_src<='1';
inc_pc<='0';ir_read<='0';
elsif(state="1011") then
alu_ctrl<="000";--idle
reg_read<='1';
reg_write<='0';
alu_src<='0';
inc_pc<='0';ir_read<='0';
elsif(state="1100") then
alu_ctrl<="010";--add
reg_read<='1';
reg_write<='1';
alu_src<='1';
inc_pc<='0';ir_read<='0';
elsif(state="1101") then
alu_ctrl<="010";--add
reg_read<='1';
reg_write<='1';
alu_src<='1';
inc_pc<='0';ir_read<='0';
elsif(state="1110") then
if (opcode="00000010"
or opcode="00000000") then
alu_ctrl<="010";--add
elsif(opcode="00011000"
or opcode="00011010") then
alu_ctrl<="110";--sub
elsif(opcode ="11110110" ) then
alu_ctrl<="111";--mul
elsif(opcode ="11110010" ) then
alu_ctrl<="100";--div
end if;
reg_read<='1';
reg_write<='1';
alu_src<='0';
inc_pc<='0';ir_read<='0';
elsif(state="1111") then
alu_ctrl<="000";--idle
reg_read<='0';
reg_write<='0';
alu_src<='0';
inc_pc<='0';ir_read<='0';
end if;
end process;
end Behavioral;