M68000 Simplified Internal Structure

Address Bus Data Bus

A23 - A0 D15 -D0

MAR MBR

Instruction Reg Control Unit

Program Counter ALU

XZNVC CCR

A0 D0

A1 D1

A2 D2

A3 D3 Data
Address
Registers
Registers A4 D4

A5 D5

A6 D6

USP A7 D7

User Programming Model

15 8 7 0

SSP A7 System Byte CCR

Status Register

Supervisor Programming Model Supplement

 The 68000’s Data Registers
A data register is a general-purpose register that holds data. This data is either used by the CPU or
is the result of an operation performed by the CPU.

• 8 general-purpose data registers, D0-D7

• all 8 registers are 32-bits, but can be divided into 2 words or 4 bytes
• byte operations on a register affect bits 0-7
• word operations on a register affect bits 0-15
• long word operations on a register affect all 32 bits

D31 D16 D15 D8 D7 D0

D0

32-bit value, e.g., large number D1

16-bit value 16-bit value D2

8-bit value 8-bit value 8-bit value 8-bit value D3

D4
byte D5
word D6
longword D7
 Operand Size

Since the 68000 is capable of performing operations on bytes, words, and long words:

• In assembly language, a size indicator is appended to the instruction mnemonic

(B=Byte, W=word, and L=long word):

ADD.B D0,D1 ;add byte in D0 to byte in D1

ADD.W D0,D1 ;add word in D0 to word in D1
ADD.L D0,D1 ;add long word in D0 to long word in D1

• If the size indicator is omitted, a word operation is assumed.

Note: Most, but not all, 68000 instructions support

byte, word, and long word operations.
 Examples of Byte, Word, and Long-word MOVE Operations

• MOVE.B D0,D1 Registers

31 0

D1 = D0 FF FF FF FF
31 0

D1 12 34 56 78
• MOVE.W D0,D1

D1 =

• MOVE.L D0,D1

D1 =

• MOVE D0,D1

D1 =
 The 68000’s Address Registers
Address registers are always used to store the address of a memory location.

• 8 address registers, A0-A7

• A0-A6 can be used as you see fit; you should not use A7 explicitly.

A31 A16 A15 A0

A0 Memory
D0
A1

A2

12345678 A3 12345678
A4 +
A5

A6 Operation of ADD (A3),D0

A7 – USP/SSP
 Address Registers are Treated Different from Data Registers

• The contents of an address register are considered to be a signed value, and only long
word operations can take place on the contents of an address register.

− In the case of a word operation, the source operand is sign extended to a long
word.

e.g., 000516 becomes 0000000516 and FFF516 becomes FFFFFFF516

• If an address register is specified as the destination operand, the following address

register instructions

MOVEA ADDA SUBA CMPA

must be used instead of MOVE, ADD, SUB, and CMP, respectively.

 The Condition-Code Register (CCR)
The least significant eight bits of the Status Register (SR) constitute the Condition Code
Register (CCR) and indicate the outcome of instructions executed by the CPU.

ALU

7 6 5 4 3 2 1 0
X N Z V C CCR

BITS FUNCTION
0 Set to 1 if carry/borrow occurs; otherwise cleared (set to 0)
1 Set to 1 if signed overflow occurs; otherwise cleared
2 Set to 1 if result is 0; otherwise cleared
3 Set to 1 if result is negative, set to 0 if positive
4 Extend bit retains carry bit for multi-word arithmetic
5,6,7 Not used
 An Example Calculation

Instruction: ADD.B #25,D1

How each flag (bit) is calculated:
Before: D1 = $00000070 C = Sm⋅Dm + Rm⋅Dm + Rm⋅Sm

111
00011001
+01110000
10001001 V = Sm⋅Dm⋅Rm + Sm⋅Dm⋅Rm

Rm = 1
Dm = 0 N = Rm
Sm = 0

Z = Rm⋅Rm-1⋅Rm-2⋅⋅⋅R0
Note: No general rules for determining how an
instruction will affect bits in CCR

• Certain operations affect all bits

X = C
• Certain operations affect only some of the bits
• Certain operations do not affect any of the bits
 The 68000’s Program Counter and Address Bus

The 68000 has a 32-bit program counter and 32-bit address registers, but only a 24-bit
address bus.

⇒ Theoretical address space = 232 memory locations

A0
Only 24 address lines (A0-A23)
PC/A0-A7
are brought off-chip

A23
Actual address space = 224 =16,777,216 locations
A24
Not
A31 Connected
Implication: use 6 hex digits to specify
address instead of eight!
A0 implied by UDS and LDS bus signals
12345616 ⇔ xx12345616

(24 bits) (32 bits)

 68000 Memory Organization
The 68000 can address 224 unique memory locations and each location can store one byte (8 bits) of
information.

000000 byte 0
000001 byte 1
000002 byte 2
000003 byte 3

Address Space = 224 =16,777,216 bytes

FFFFFF

Byte View of Memory

 68000 Memory Organization
The 68000 can also output or receive data in word (16 bit) or long word (32 bit) format. However,
words and long words must start at an even address, otherwise a memory alignment error will be
generated.

000000 byte 0 First word at 000000 byte 0 First long word at

000001 byte 1 address 000000 000001 byte 1 address 000000
000002 byte 2 Second word at 000002 byte 2
000003 byte 3 address 000000 000003 byte 3
000004 byte 4 000004 byte 4
000005 Byte 5 Bytes 5 & 6 cannot 000005 Byte 5
000006 Byte 6 form a word – address 000006 Byte 6
000007 Byte 7 000005 is odd Another long word at
000007 Byte 7 address 000006
000008 Byte 8 000008 Byte 8
000009 Byte 9 000009 Byte 9

Word View of Memory Long word View of Memory

 68000 Memory Organization – Byte Ordering

When storing values in memory, the most significant byte is stored at the first address location
followed by the remaining bytes, as illustrated below.

31 0
memory
Register A1 D2 C3 B4
msb lsb

000100 A1 msb

Move the long word value in a 000101 D2

data (address) register to the 000102 C3
memory location addressed by
00010016 000103 B4 lsb
 A Few Examples of Storing Data in Memory

Memory Memory Memory

00000100 00000100 00000100

00000101 00000101 00000101
00000102 00000102 00000102
00000103 00000103 00000103

MOVE.B #1,$100 MOVE.W #1,$100 MOVE.L #1,$100

Memory Memory Memory

00000100 00000100 00000100

00000101 00000101 00000101
00000102 00000102 00000102
00000103 00000103 00000103

MOVE.B #1,$101 MOVE.W #1,$101 MOVE.L #1,$101

 A Few Examples of Reading Data from Memory

Memory Memory Memory

00000100 12 00000100 12 00000100 12

00000001 34 00000101 34 00000101 34
00000102 56 00000102 56 00000102 56
00000103 78 00000103 78 00000103 78

MOVE.B $100,D0 MOVE.W $100,D0 MOVE.L $100,D0

31
Before 0

D0 FF FF FF FF

After After After

31 0 31 0

D0 D0 D0
 68000 Instruction Format
An instruction consists of one to five instruction words (16 bits). An instruction may have no
operands, one operands, or two operands. Source operands are not changed by the instruction;
destination operands are changed during the execution of the instruction.

OPERATION WORD
(First word specifies operation and modes)

Literal (Immediate) Operand

(If any, one or two words)

SOURCE EFFECTIVE ADDRESS

(If any, one or two words)

DESTINATION EFFECTIVE ADDRESS

(If any, one or two words)