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analog
A/D DSP D/A analog
signal
converter algorithms converter signal
Software tools:
Assembly language tools, DSP simulator, C
compiler and C source debugger.
C
Compiler
Assemble
r Source
Assembler
Library
Archiver COFF build utility
Object Run time
file supp.Library
Library of Linker
Object file
Exec. Debugging
COFF file tools on a
To PC for PC
Emulatio
Absolute Cross-reference Hex n
lister lister conversion
utility
Hexadecimal
Object file
To
TMS320CXX
target system
Software Life Cycle - Waterfall Method
Requirements
Analysis
Architectural
Design
Detailed
Design
Coding
Unit Test
Integration
Test
System Test
Texas Instruments’ TMS320 family
Project Manager:
Source & object files
File dependencies
Compiler, Assembler &
Linker build options
Editor:
Structure Expansion
n n+1
Sample Time
Host PC
Signal
gen.
I/P O/P
Head-
phones
Host PC
DSP EVM
CRO
Bridge
8 4
5 1
Traditional Analog
Inrush/ DC/DC
DC/DC Current/Load
Current/Load
Hot-plug PFC Control Converter
Converter Sharing
Sharing Power Supply
Control Control
Control Control
Control Multiple chips for
Interface Multi-mode
Multi-mode control
Powercontrol
Power control
Circuit Micro-controller for
Monitor Supervisory
Supervisory
(MCU)
(MCU?)
MCU
MCU Housekeeping
Housekeeping supervisory
Circuits
Circuits
Dedicated design
Aux P/S To Host
Eliminate Components
Filter Output
V PFC DC/DC V Reduce Manufacturing Cost
Bridge
Better Performance Across Corners
Failure Prediction
Aux P/S One Device, Multiple DC Outputs
Variable DC Output
Digital controller enables multi-threaded applications
Analog Control System
e C P
R
+ (controller) (plant)
Y
-
“Analog Computation”
Differential equations
C2 C
C1
R
Energy
R2 R
R
Storage
Elements
R1
L
Difference equation C
U (n) a2 U (n 2) a1 U (n 1) Energy
R
Storage
b2 E (n 2) b1 E (n 1) b0 E (n) Elements
L
where E (n) R (n) Y (n)
- Control
A-D Law
D-A
+
Ref
t t t t
Continuous Discrete
time signal time signal
Digitally Controlled Power Supply
DAC
(PWM)
DSC
“Plant”
ADC
0110101100
1011011101
0010100111
“High fidelity”
Translation boundary
System Mapping
PFC – 3ph Interleaved
VOUT
F280xx Vin
Ch1
DSP ADC
Ch2
32 bit core
12 bit
60~100
(80nS)
MHz Ch16
1A
ePWM1 1B
2A Phase-Shifted Full Bridge
ePWM2 2B
3A VIN VOUT
ePWM3 3B
8A
ePWM8 8B
Software Library Approach
CNTL CNTL Buck E HR E
P P
2P2Z 3P3Z Single W
Buck W
Ref Ref DRV M Single M
FB
Uout
FB
Uout DRV
Duty H EPWMnA Duty H EPWMnA
W W
Control 2-pole / 2-zero Control 3-pole / 3-zero
Buck Single Output High Resolution Buck
IIR-FILT IIR-FILT
2P2Z 3P3Z EPWM1A PFC E
MPIL E
EPWM1B 2PHIL P
P W
f f DRV W DRV M
EPWM2A
M
Duty EPWMnA
In Out In Out EPWM2B H
H Adj W EPWMnB
2nd order IIR filter 3rd order IIR filter Duty W
Power Factor 2-phase
Multi-Phase Interleaved Interleaved
SinGen1 SGenHP1
HHB
E IBM
P E
Freq Freq DRV W FB P EPWMnA
Soft Start and Sequencing Phase Shifted Full Bridge Analog-Digital Converter driver
CPU dependency only:
• Math / algorithms
Peripheral Drivers
Depends on:
• Per-Unit math (0-100%) • PWM frequency
• Independent of Hardware • System clock frequency
E
BUCK P
CNTL DRV W
2P2Z M
Vref Ref Duty H
(Q15) Out In EPWM1A
Fdbk (Q15) W
ADC
SEQ1 A
DRV D
Vout Rslt0
C
ADC_A0
(Q15)
H ADC_A1
W ADC_A2
// pointer & Net declarations
int *CNTL_Ref1, *CNTL_Fdbk1, *CNTL_Out1; ADC_A3
int *BUCK_In1, *ADC_Rslt1;
int Vref, Duty, Vout;
H
Vout1 rslt0 W Ch0
400 kHz
H
Vout2 rslt0 W Ch1
400 kHz
Software Block Execution
(400 kHz)
SStartSeq
Context Save
Comms
ADC_DRV(1)
CNTL_2P2Z(1) Loop-1
BUCK_DRV(1)
ISR body
ADC_DRV(2)
CNTL_2P2Z(2) Loop-2
Other....
BUCK_DRV(2)
Context
Restore
Driving the Power Stage with PWM Waveforms
H
Duty1 Duty1 In W EPWMnA DRV Buck
Duty2
ADC A
D
Duty3 1CH
C
DRV
Duty1
H
slider Vfdbk Vout1 Rslt W Ch0
Scaleable PWM Peripherals
xSYNCI
SYNCI
VBus32
ADC
to ECAP1 module (sync in)
ePWM Module Block Diagram
Time-Base (TB)
Sync
TBPRD Shadow (16) CTR=ZERO In/Out
Select EPWMxSYNCO
TBPRD Active (16) CTR=CMPB Mux
Disabled
S0 S1
CTR=PRD
TBCTL[SYNCOSEL]
16
EPWMxSYNCI
Counter TBCTL[SWFSYNC]
UP / DWN TBCTL[CNTLDE] (software forced sync)
(16 bit)
TBCNT CTR=ZERO
Active (16) CTR_Dir
16
Phase
TBPHS Active (16) CTR=PRD
Control
EPWMxINTn
CTR=ZERO
Event
Trigger &
CTR=CMPA EPWMxSOCA
Interrupt
(ET)
Counter Compare (CC) CTR=CMPB
EPWMxSOCB
CTR_Dir
16 CTR=CMPA
Action
Qualifier
16 (AQ)
time
Action Qualifier Module (AQ)
Key Features TBCTR = Period
Zero Z Z Z Z
TBCTR
(ZRO) T
CMPA CA CA CA CA PRD
TBCTR Period
(CAu) T
(Up) CBu CBd
equals: CMPB CB CB CB CB CMPB
(CBu) T
CAu CAd
P P P P CMPA
Period
(PRD) T ZRO
CMPA CA CA CA CA Zero
TBCTR (CAd) T
(Down)
equals: CMPB CB CB CB CB
(CBd) T
SW SW SW SW
S/W force
T
Simple Waveform Construction
TBCTR
TBPRD
value
Z P CB CA Z P CB CA Z P
EPWMA
Z P CB CA Z P CB CA Z P
EPWMB
TBCTR
TBPRD
value
CA CB CA CB
EPWMA
Z Z Z
T T T
EPWMB
Fault Management Support
Vin Vout1
‘2808
EPWM1A Iin I1
EPWM2A
Iin EPWM1A Buck #1
HiZ
TZ1
ShutDown
I2
TZ2
CL2 Vout2
TZ3
CL1 I1
IsetCL1
Action on
Fault
I2
EPWM1B EPWM2A Buck #2
IsetCL2 HiZ
EPWM2B
IsetSD
ECAP1
IsetSD
Iin
2 X Vout
SyncOut
3 X
SyncOut
Switching Requirements – MPI
P P P
I I I
CA P CA
A
P • CMPA (1,2,3)
• CMPB (1,2,3)
EPWM3A
Half H-Bridge (HHB)
VDC_bus VOUT
Ext Sync In
(optional)
Master
EPWM1A
Phase Reg En SyncIn
EPWM1A
CNT=Zero
CNT=CMPB EPWM1B
1 X
SyncOut
EPWM1B
Switching Requirements – HHB
CMPA CMPA
modulation modulation • Up/Down Count
range range
• Asymmetrical PWM
• dead-band on A only
• 50 % max Modulation
CA CB Z CA Z (controlled by CMPA)
A
EPWM1B INIT-time
• ZRO Action (A,B)
Z CB CA Z CA • CAd Action
A • CAu Action
EPWM1A DBRED DBRED
• CBd ADC trigger
• CBd ADC trigger
• DBRED
Compare A modulation range:
0 < CMPA < ( PRD – ½ x DBRED ) RUN-time
• CMPA
• CMPB (optional)
Phase Shifted Full Bridge (PSFB)
Ext Sync In
Master
(optional)
VDC_bus VOUT
Phase Reg En SyncIn
EPWM1A
CNT=Zero
CNT=CMPB EPWM1B
EPWM1A EPWM2A
1 X
SyncOut
Slave
Phase Reg En SyncIn
Var EPWM2A
CNT=Zero
CNT=CMPB EPWM2B
EPWM1B EPWM2B
2 X
SyncOut
Switching Requirements – PSFB
Z
I
Z
I
Z
I
• Asymmetrical PWM
• Using dead-band module
• Phase (Φ) is the control variable
• Duty fixed at ~ 50%
Z CB CA Z CB CA Z
• RED / FED control ZVS trans.
A A i.e. via resonance
EPWM1A RED
• CMPB can trigger ADC SOC
ZVS
transition
EPWM1B
Power
Phase
FED INIT-time
ZVS
transition
• Period (1,2)
variable
• CMPA (1,2) ~ 50%
• CAu action (1,2)
• ZRO action (1,2)
Z CB CA
A
Z CB CA
A
Z
• CBu trigger for ADC SOC
EPWM2A RED
RUN-time
• Phase (2) – every cycle
EPWM2B
Power
Phase FED
• FED / RED (1,2) – slow loop
Software Driver Module – PSFB
50% duty
PSFB E
EPWM1A
DRV P
W EPWM1B
M
Net1 phase EPWM1A llegdb
EPWM2A Left leg
H dead-band
Net2 llegdb
W EPWM2B
EPWM1B Power
Net3 rlegdb Phase
llegdb
phase
VDC_bus VOUT
EPWM1A EPWM2A
EPWM2A rlegdb
right leg
dead-band
Power
EPWM2B Phase
EPWM1B EPWM2B rlegdb
EPWM1A +/-
Adj
VDC_bus
+/-
EPWM1B Adj
EPWM1A EPWM1B
1