VLSI ABSTRACTS

An Accumulator—Based Test-Per-Clock Scheme

Abstract

We propose a new scheme for reducing the test application time in accumulator-
based test-pattern generation. Within this framework, we reduce the problem of
efficiently generating test-patterns to that of finding the shortest Hamiltonian path
in an associated directed graph. The resulting scheme exhibits extremely low
demand for hardware based on a combination of decoders whose inputs are driven
by a very slow external tester. Experimental results on ISCAS benchmarks
substantiate the superiority of the proposed scheme over the previously-published
test-set embedding approaches for accumulator-based test generation

FPGA based system for video compression and transmission over bluetooth

Abstract

An implementation of real-time video compression and transmission method using

low-cost Field-Programmable Gate Array (FPGA) is presented in this paper. The
proposed system utilizes Bluetooth link in order to transmit 88x136 pictures at the
rate of up to 17 frames per second. The main focus was on the low-power
implementation of the system because of its mobility. This is why the Bluetooth
was chosen as wireless carrier. Also the demand for this kind of systems is
growing. Therefore the hardware design effort was targeted to the lowest FPGA
area usage at the appropriate performance level. This was done by modifying the
existing image compression methods in order to simplify the design. The system
captures input from widely known CMUCam video camera module and transmits
picture to the PC system

A Hardware and Software Cooperative Design of SoC IP

Abstract

As an advanced component of embedded systems, SoC issues excellent

performance in size, reliability and operating efficiency. Its application is popular.
SoC is mainly composed of some computing cores and IP modules. Its design is
concerned to cooperation of hardware HW and software SW. In this paper, a
method of HW-SW co-design for IP is discussed. As an example, the design of
some display IP modules for SoC is issued. The solution is based on FPGA
hardware with VHDL software. Simulation and test show that some software
function is replaced by hardware. With new IP modules, the application software
can be written more simply, and the operation of SoC will be faster and more
reliable

CPLD-based system for the quadrature digital upconverter

Abstract

This paper addresses an issue of proper parameter selection for a fast DCT-based
image filtering in non-overlapping or partially overlapping blocks. Images
processed with different parameter sets are compared to each other for a set of test
images in terms of standard criteria (output MSE) and visual quality measures
(PSNR-HVS-M and MSSIM). Comparison to other fast filters is done as well.
Advantages of the proposed methods for fast denoising are demonstrated. In this
paper CPLD-based realization of a radio technical system meant for the quadrature
digital up converter control being used in the communication systems of special
purpose

A harmonic signal generator based on DDS and SOPC

Abstract

A harmonic signal generator with adjustable frequency, phase and harmonic

proportion is designed in this paper. The design of this harmonic signal generator
is based on direct digital frequency synthesis (DDS) technology and the idea of
System on a Programmable Chip (SOPC). The classic structure of DDS is
introduced and a kind of compression ROM is designed. Then, the DDS core with
compression ROM is compiled using Quartus II by VHDL language. As a kind of
processor which is supplied by Atera Inc., the soft core, Nois II is embedded on
FPGA chip. Using Nois II and other modules, a system is designed on one single
FPGA chip. The performances such as integration, expansibility are very much
improved. The principle of DDS is discussed particularly; the optimized structure
of DDS core and the design SOPC on single FPGA are presented in this paper
The embedded measurement system for multiple motor speed based on FPGA

Abstract

In this paper, we discuss an embedded digital measurement system based on FPGA

for motor's speed. In order to overcome the shortcomings of T method and M
method, the improved M/T method is used. According to the principle of improved
method, the motor's speeding signals of four channels are measured and the
communication with PMC bus is attained. The hardware of system is composed of
photoelectric encoders, FPGA core chip, PMC bus, and the software of system
which programmed with hard description language is composed of the frequency
multiplication module, the direction judgment module, the speed measurement
module and the data transfer interface module. This scheme makes full use of
embedded technique, implement measurement of the motor's speed with less
hardware. Eventually the simulation analyses of program in the Quartus II is gave
in this paper. The results of simulation indicate this scheme is efficient, reliable,
and can meet the requirements of measurement

Design of frequency measurement based on FPGA and MCU

Abstract

Traditional frequency measurement based on MCU is benefit from its low-cost,

however, disadvantage which includes low precision and narrow frequency range
also exist in this kind of system. This paper demonstrates a project which combines
FPGA with MCU, fully exert the high speed property of FPGA, the easy-calculate
quality and flexible control of peripheral of MCU, using method of equal
precision. The product offers perfect performance of frequency range of
0.01Hz~10MHz. At the same time, this system has advantages of short reflect time
and high reliability

Optimization of DNA Sequences Data to Accelerate DNA Sequence Alignment

on FPGA

Abstract

This paper presents the design and development of high performance accelerating
and optimization technique for accelerate the process of DNA sequences
alignment. The scope of the paper focuses on memory and speed optimization by
optimizing and mapping the DNA sequences data before alignment. This
optimization technique is designed based on novel data compression technique in
optimizing the numbers of data transmitted from computer to DNA sequences
alignment accelerator. Consequently, the numbers of data per serial data
transmission for alignment can be optimize and accelerate up to 400% greater than
conventional DNA sequences alignment accelerator system. This technique has
been design and implemented on hardware based acceleration device and targeted
to Altera Cyclone II 2C70 FPGA and using 50 MHz oscillator for clock source.
The code is written in verilog HDL syntax using Quartus 2 version 7.2 and the
simulation is verified using Quartus 2 version 7.2 simulator tools. As a result, the
theoretical analysis, simulation and implementation result based on development
and implementation of the proposed design on FPGA are presented and well
organized in this paper. The comparative study based on theoretical, simulation
and implementation results of this technique has been made to accomplish result of
analysis

Time-Multiplexed Compressed Test of SOC Designs

Abstract

In this paper we observe that the necessary amount of compressed test data
transferred from the tester to the embedded cores in a system-on-a-chip (SOC)
varies significantly during the testing process. This motivates a novel approach to
compressed system-on-a-chip testing based on time-multiplexing the tester
channels. It is shown how the introduction of a few control channels will enable
the sharing of data channels, on which compressed seeds are passed to every
embedded core. Through the use of modular and scalable hardware for on-chip test
control and test data decompression, we define a new algorithmic framework for
test data compression that is applicable to system-on-a-chip devices comprising
intellectual property-protected blocks.

Practical Approach to Programmable Analog Circuits With Memristors

Abstract

We suggest an approach to use memristors (resistors with memory) in

programmable analog circuits. Our idea consists in a circuit design in which low
voltages are applied to memristors during their operation as analog circuit elements
and high voltages are used to program the memristor's states. This way, as it was
demonstrated in recent experiments, the state of memristors does not essentially
change during analog mode operation. As an example of our approach, we have
built several programmable analog circuits demonstrating memristor-based
programming of threshold, gain and frequency. In these circuits the role of
memristor is played by a memristor emulator developed by us