Analog IC Design

Chapter 3. Single-Transistor Primitives

Outline
3.1. Two-Port Models

3.2. Frequency Response

3.3. Signal Flow

3.4. Common-Emitter/Source Transconductor

3.5. Common-Base/Gate Current Buffer

3.6. Common-Collector/Drain Voltage Follower

3.7. Summary

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3.1. Two-Port Models: Philosophy and Extraction

Purpose: Model a device or complicated circuit with simple unloaded

two-component networks that can predict loaded response.

Philosophy: Avoid model redundancies.

Two-Port Models
with orthogonal components.

Extraction: When deriving a parameter,

nullify the effects

of the other.

Norton Equivalent: Derive gain ANI when iR = 0 à vN = 0: Short terminals.

Derive resistance RP when control signal sC = 0.

Thévenin Equivalent: Derive gain ATV when vR = 0 à iR = 0: Remove load.

Derive resistance RS when control signal sC = 0.

Examples
Sample Input–Output Model Popular Input–Output Model

Sample Model: Derive RIN when iO = 0 à Remove load.

Derive AG when iRIN = 0 à vIN = 0: Short input.

Derive AV when vRO = 0 à iO = 0: Remove load.

Derive RO when vIN = 0 à Short input.

Popular Model: Derive RIN as is à No redundancies to consider.

Derive GM when iRO = 0 à vO = 0: Short output.

Derive RO when vIN = 0 à Short input.

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3.2. Frequency Response: A. Pole

Pole ≡ Signal decays (i.e., loses energy) as operating frequency climbs.
Parallel capacitors shunt energy away from nodes.
∴ CSH shunts energy when 1/sCSH falls below parallel RSH, past pole pC.

! 1 $ i IN R SH i R 1
v O = i IN # R SH || &= = IN SH = R SH
sC 1+ sR C s à
sCSH
" SH % SH SH 1+ f=
1
≡pC
2πp C 2πR SH CSH

Capacitor voltage changes slowly.

à Poles delay signals 0° to 90°.
Lagging delay between two sinusoids
amounts to negative phase shift.
" f %
Phase Pole = − tan −1 $ ' à 0° to –90°.
# pC &
Since ZC = 1/sCEQ ∝ 1/f, gain drops linearly with frequency.
∴ Gain falls 10× with a 10× rise in frequency, which equates to –20 dB per decade.

B. Zeros: i. Feed-Forward Zeros

Zero ≡ Signal rises (i.e., gains energy) as frequency climbs à Opposite of pole.
A feed-forward capacitor CFF:
Steers energy away from input vIN à Contributes to input pole pIN.
Adds energy to output vO à Introduces feed-forward zero zFF when iFF ≥ iGM.
∴ Short-circuit transconductance (when vO = 0) incorporates a zero zFF:
v IN − v O
i FF =
ZC
= v INsC FF
z FF =
GM (
= i GM − i RO ) v O =0
= i GM = v IN G M
v O =0 2πCFF

Since ZC = 1/sCEQ ∝ 1/f, gain climbs linearly with frequency.

∴ Gain rises 10× with a 10× rise in frequency, which equates to +20 dB per decade.

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In-phase feed-forward capacitors do not oppose the amplifier.

∴ Zero zLHP removes the effects of a pole à Recovers 0°–90° à Left-half plane.
" f %
Phase LHP Zero = tan −1 $ '
# z LHP &

" f %
Phase RHP Zero = − tan −1 $ '
# z RHP &
Out-of-phase feed-forward capacitors oppose the amplifier à 180° = –90 – (0–90).

∴ Zero zRHP subtracts 0°–90° à Normally undesirable à Right-half plane.

ii. Current-Limiting Zero

At Low Frequency: CSHUNT is open ∴ iO = iIN and vO = iINRO à Flat response.

At Higher Frequency: CSHUNT shunts current energy away from RO.
∴ iO and therefore vO drop past pole pSHUNT when 1/sCSHUNT ≤ RO + RLIMIT.
At High Frequency: Series RLIMIT limits CSHUNT's shunting current,
∴ RLIMIT arrests (i.e., removes) the effects of pSHUNT past in-phase zero zLIMIT
when 1/sCSHUNT ≤ RLIMIT à Response flattens to vO = iIN(RO || RLIMIT).

1
= R LIMIT
sCSHUNT f=
1
≡z LIMIT
2πR LIMIT CSHUNT

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C. Miller Split iFF à zRHP

C MI = (1+ A V ) C M ≈ A VC M

! 1 $
C MO = ##1+ && C M ≈ C M
" AV %
As vIN rises, vO falls more ∴ vIN – vO rises more than vIN:
(vIN – vO)CM demands more current than vINCM, like higher capacitance would.

v IN v IN v IN 1 1
Z MI ≡ = = = ≡
iC ( v IN − v O ) sC M ( v IN + v IN A V ) sC M s (1+ A V ) C M sC MI

vO rises when vIN hardly falls ∴ vO – vIN rises nearly as much as vO.
à (vO – vIN)CM demands nearly as much current as vINCM.
vO vO vO 1 1
Z MO ≡ = = = ≡
iC ( v O − v IN ) sC M # vO & # 1 & sC MO
% vO + ( sC M s %1+ ( CM
$ AV ' $ AV '

D. Analysis: Capacitors Shunt Resistors

Capacitors open at low frequencies: Capacitors are absent at low frequencies.

Capacitors shunt resistors past their 1/2πREQCEQ frequencies.

∴ Capacitors replace resistors à Resistors disappear.

The lowest-frequency shunt corresponds to the highest REQCEQ product.

Note: Off-chip, intentional, load, and Cπ/GS capacitors normally shunt first.

Frequency-Response Analysis

Low-frequency gain A0: Exclude all capacitors to determine A0.

f1: Determine which capacitor shunts its parallel resistance first.

à Find highest REQCEQ when all other capacitors are still open.

f2: Replace REQ1 with CEQ1 and find the next highest REQCEQ.
1
fN: If N REQCEQ's are close, N capacitors short near fN ≈ .
2π ⎡⎣Avg ( R EQ C EQ )⎤⎦

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3.3. Signals and Terminals

Signal Composition
Bias (i.e., dc, steady state): All upper-case variables à IC, VDS, etc.
Small-Signal Variations: All lower-case variables à id, vbe, etc.
Entire Signal: Lower-case variables with
BJT
upper-case subscripts à iS, vD, etc.
Terminal Roles in Transistors:
Bases and gates carry little to no current ∴ Bad outputs.
Collectors, emitters, drains, and sources carry almost
all the current: iC ≈ iE and iD = iS ∴ Good outputs. MOS
iC/E and iD/S are sensitive to vBE and vGS.
∴ Bases, emitters, gates, and sources are good inputs.
iC/E and iD/S are insensitive to vC and vD.
∴ Collectors and drains are bad inputs.

A. Possible Transistor Configurations

Note common terminal is unused small-signal terminal.

Common Emitter/Source Common Collector/Drain

Base and gate are bad outputs ∴ When in use, they should be inputs.

Common Base/Gate

Collector and drain are bad inputs ∴ When in use, they should be outputs.

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B. Signal Flow
Possible Signal-Flow Paths

Base Input: Higher vB (+) raises vBE ∴ iC rises (+) à iC lowers vC (–) and raises vE (+).

Emitter Input: Lower vE (–) raises vBE ∴ iC rises (+) à iC lowers vC (–).

Polarity: Base/gate to emitter/source à In phase.

Emitter/source to collector/drain à In phase.

Base/gate to collector/drain à Out of phase à Only one that inverts.

3.4. Transconductor: A. Large-Signal Operation

Common-Emitter and -Source Configurations

Supply voltage – VBIAS is constant.

VO(MAX) ≈ vCC – VEC(MIN) or vDD because iD ≈ 0 and VO(MIN) = VCE(MIN) or IBIASRTRIODE.

ISOURCE(MAX) ≤ IBIAS IPULL(MAX) = f(iB or vGST) – IBIAS

Depends on bias. Depends on base or gate drive and bias.

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B. Small-Signal Model
Equivalent Low-Frequency Two-Port Models

BJT MOS
RIN: rπ = β0/gm ∞
RO when vin = 0: ro = VA/IC rds = 1/λID
GM when vo = 0: gm = IC/Vt gm = sqrt (2IDK'W/L)

v o −v in G M ( R O || R LOAD )
Voltage Gain: A V0 ≡ = = −g m ( ro || R LOAD ) à 50–100 V/V
v in v in

Example
Signal Propagation

Δv IN → Δi D1 → Δv O1 → ΔiC2 → Δv O2 = v in → id1 → v o1 → ic2 → v o2

v o2 " i d1 %" v o1 %" i c2 %" v o2 %

A V0 ≡ = $ '$ '$ '$ '
v in $# v in '&$# i d1 '&$# v o1 '&$# i c2 '&

( )( )( )(
= −G M(CS) R O(CS) || R D1 || R IN(CE) −G M(CE) R O(CE) || R C2 )
( )( )( )(
= −g m1 rds1 || R D1 || rπ2 −g m2 ro2 || R C2 )

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C. Frequency Response
Wide-Spectrum Model
Load Load

Source Source

Cµ feed-forwards energy to vo to produce a zero.

iCµ opposes igm à Out of Phase à In the right-half plane.

zRHP Location: When short-circuit gm inverts à When iCµ ≥ igm.

∴ When iCµ = igm, so vce = 0 and ro's and ZLOAD's currents = 0.

iCµ = ( v be − v ce ) sCµ = ( v be − 0 ) sCµ z gm ≡ igm + i ro ||Z LOAD = igm = v beg m

RHP =
2πCµ

Feed-Forward gm
Current Current

CS, Cπ, Cµ and Cµ, CLOAD shunt energy from vin and vo to establish poles.

Miller Split: Decompose Cµ into CMI and CMO.

C MI = (1+ A V ) Cµ = !"1+ G M ( R O || R LOAD )#$ Cµ

! 1 $ ' 1 *
C MO = #1+ & Cµ = )1+ , Cµ
" AV % )( G M ( R O || R LOAD ) ,+

Case 1. If RS ≈ RLOAD ≈ ro and CLOAD ≈ Cπ: RCICI is the highest REQCEQ.

∴ First pole occurs when CI shunts RCI, when 1/sCI ≤ RCI.

1
≡ R S || R IN
s (CS + C π + C MI ) p 1
IN =
2π(CS +C π +C MI )( R S ||R IN )

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Past pIN, CS + Cπ + CMI shunt and replace RS and RIN ∴ RS and RIN disappear.

1 1
≈ ( G C +

{ # ( %
s C LOAD + $Cµ ⊕ CS + Cπ & s C )} (
LOAD
+ Cµ ) pO ≈
* M µ -
* C +C +C -
) S π µ,
(
2π CLOAD +Cµ )

≡ R GM || R O || R LOAD ≈
(CS + Cπ ) + Cµ
iGM is a linear translation of vo. G M Cµ

R GM ≡
vo
=
vo
=
vo (C + Cπ ) + Cµ
= S
iGM # v o ( Z S || Z π ) & # Cµ & G M Cµ
% (G M vo % (G M
Z Z ||
%$ µ ( S π ) ('
+ Z C
$% ( S + C π) + Cµ(
'

Where GM is gm and RGM is moderately greater than 1/GM.

If Cµ' ≡ CC + Cµ >> CS + Cπ ∴ Cµ' shorts à RGM ≈ 1/GM.

Case 2. If RS ≈ 1/gm, RLOAD ≈ ro, and CLOAD ≈ Cπ: RCOCO can be the highest REQCEQ.

∴ First pole occurs when CO shunts RCO, when 1/sCO ≤ RCO.

1
≡ R O || R LOAD
s (C MO + C LOAD ) p 1
O'≈
2π( R O ||R LOAD )(C MO +C LOAD )

Past pO', CMO + CLOAD shunt and replace RO and RLOAD ∴ RO and RLOAD disappear.

1 1
≈ ≡ R S || R IN
s$CS + C π + (Cµ ⊕ C LOAD )&
# % s C
( S π + Cµ )
+ C 1
p IN'≈
2π(CS +C π +Cµ )( R S ||R IN )

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Example
Objective: If RS = 100 kΩ, vBS = 0, IC = ID = 25 µA, β0 = 100, KN' = 100 µA/V2,
VA = 1/λ = 50 V, Cπ = CGS = 100 fF, Cµ = CGD = 10 fF, W = 20 µm, L = 2 µm,
RL = 100 kΩ, and CL = 200 fF, determine AV0, fT, pIN, pO, and zRHP.
Solution:
BJT gm = 980 µS, 1/gm = 1.0 kΩ, rπ = 100 kΩ, and ro = 2 MΩ.
∴ AV0 ≈ –93 V/V and fT ≈ 1.4 GHz.
CMI ≈ 930 fF à CIN = CMI + Cπ = 1 pF.
∴ pIN ≈ 3.2 MHz, pO ≈ 77 MHz, and zRHP ≈ 1.4 GHz.
MOS gm = 224 µS, 1/gm = 4.5 kΩ, and rds = 2 MΩ.
∴ AV0 ≈ –21 V/V and fT ≈ 320 MHz.
CMI ≈ 220 fF à CIN = CMI + CGS = 320 fF.
∴ pIN ≈ 5.0 MHz, pO ≈ 23 MHz, and zRHP ≈ 324 MHz.

BJT's rπ shunts RS and higher gm raises CMI in pIN, so BJT's pIN ≈ MOS's pIN.

D. Emitter and Source Degeneration

Resistance RDEG in series with emitter and source.

RDEG raises input resistance RIN.

RDEG raises output resistance RO.

vbe and vgs drop a fraction of vin ∴ RDEG degenerates gm.

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i. Small-Signal Model
BJT:
GM when vo = 0 ∴ RDEG || ro.

v be g m −
ve
v be g m −
(
v be g m R DEG || ro )
i ro ro
GM ≡ o = ≈
v =0 v in
o v be + v e v be + v be g m R DEG || ro ( )

! $ igm >> iro

ro
g m ## &&
" ro + R DEG % gm gm
= = ≈ ≤ gm
(
1+ g m R DEG || ro ) !1 $
1+ ## + g m && R DEG
1+ g m R DEG
" ro %
∴ RDEG reduces GM.
igm >> iπ
"1 %
Where v e = v be $ + g m ' ( R DEG || ro ) ≈ v beg m ( R DEG || ro )
# rπ &

BJT: igm >> iro

# %
( )
v in v be + v e i b rπ + i e R DEG i b rπ + $i b + i b rπ g m & R DEG
R IN =
i in
=
ib
≈
ib
≈
ib
(
= rπ + 1+ rπ g m R DEG )
β0
RO when vin = vb = 0 ∴ RDEG || rπ.

v o ( io + v eg m ) ro + v e #$io + io ( R DEG || rπ ) g m %& ro + io ( R DEG || rπ )

RO v ≡ = =
in =0
io io io
50–100
= ro + g m ro ( R DEG || rπ ) + ( R DEG || rπ )

∴ RDEG raises RIN and RO.

Voltage gain from equivalent two-port model:

When RO >> RLOAD.

v o −v in G M ( R O || R LOAD ) $ −g m '
A V0 ≡ = ≈& ) R LOAD
v in v in % 1+ g m R DEG (

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MOS: Remove rπ and include gmb, where vbs = –vs.

RIN à ∞

GM when vo = 0: –igmb = vsgmb ≡ vs/RGMB.

∴ 1/gmb shunts rds.

igm, igmb >> iro

io gm gm
GM ≡ = ≈ ≤ gm
v o =0 v in (" 1 % +
1+ *$$ + g mb '' + g m - R DEG
(
1+ g mb + g m R DEG )
*)# rds & -,

∴ gmb reduces GM.

RO without rπ when vin = vg = 0 ∴ vgs = –vs = vbs à gm eff = gm + gmb.

R O = rds + (g m + g mb ) rds R DEG + R DEG

Example
Signal Propagation: Δv IN → Δv B → ΔiC → Δv O = v in → v b → ic → v o

v o " v b %" ic %" v o % " −1 % r

A V0 ≡ = $ '$ '$ ' ≈ (1) $$ '' ( rds(PL) ) ≈ − ds(PL)
v in # v in &# v b &# ic & # rds(ND) & rds(ND)

vb R IN(DCE) rπ + (1+ g m rπ ) R D
= ≈
v in R S + R IN(DCE) R S + rπ + (1+ g m rπ ) R D

=
( )
rπ + 1+ g m rπ rds(ND)
≈
β0 rds(ND)
≈1
( )
R S + rπ + 1+ g m rπ rds(ND) R S + β0 rds(ND)

ic −g m −g m −1
≡ −G M(DCE) ≈ = ≈
vb $ 1' $ 1' rds(ND)
1+ & g m + ) R D 1+ & g m + ) rds(ND) If RIN(DCE) >> RS.
% ro ( % ro (

vo
≡ R L || R O(DCE) = rds(PL) || #$ro + g m ( rπ || R D ) ro + ( rπ || R D )%& ≈ rds(PL) || β0 ro ≈ rds(PL)
ic

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3.5. Current Buffer: A. Large-Signal Operation

Common-Base and -Gate Configurations: Notice iO ≈ iIN à Current buffer.
Supply voltage – VBIAS P is constant.

VO(MAX) ≈ vCC – VEC(MIN) or vDD because iIN ≈ 0.

VO(MIN) = vIN + VCE(MIN) or vIN + iINRTRIODE.
ISOURCE(MAX) ≤ IBIAS IPULL(MAX) = iIN(MAX) – IBIAS à f(VBIAS N – vIN(MIN) and vBS)
Depends on bias. Depends on input drive and bias.
Raising iIN corresponds to lowering vIN. Bulk effect shifts vT.

B. Small-Signal Model ii Equivalent Low-Frequency

Two-Port Model

BJT " r + R LOAD % 1

R IN = rπ || R I = rπ || $ o '>
# 1+ g m ro & g m
v e = ( i i − v eg m ) ro + i i R LOAD v r + R LOAD 1
à RI ≡ e = o > ≈ 1/gm if RLOAD << ro.
ii 1+ g m ro gm

Non-degenerated
ro + R LOAD 2
High RI = ≈ à Still Low
CE Load 1+ g m ro R LOAD =ro
gm
RLOAD Moderate to High
Cases Degenerated ro + R LOAD g m ro ( rπ || ro )
RI = ≈ ≈ rπ || ro ≈ rπ
CE Load 1+ g m ro R LOAD ≈g m ro ( rπ ||ro )
1+ g m ro

RIN is a loaded 1/gm resistance à Often near 1/gm << rπ << ro and generally low.

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RO when vin = 0 ∴ vegm = 0 and RO = ro.

GM when vo = 0:

"v %
v eg m + $ e '
i # ro & 1
G M v =0 ≡ o = = gm + ≈ gm
o
v in ve ro

MOS: Remove rπ and include gmb.

Same, but since vg = 0, vgs = vbs = –vs.

∴ gm eff = gm + gmb

Gains:

(
v o v in G M R O || R LOAD " ) 1%
A V0 ≡
v in
=
v in ro &
(
= $$ g m + '' ro || R LOAD )
#

i gm " v %" i % ) "r +R %," 1%

A I0 ≡
i in
(
# i in &# v in &
)
= $$ in ''$$ gm '' = R S || R IN G M = +R S || rπ || $$ o LOAD
''.$$ g m + '' ≈ 1
+* # 1+ g m ro &.-# ro &

v o " i gm %" v o % (
A R0 ≡ (
i in $# i in '&$# i gm '& ) S
) ( )
= $ '$ ' = R || R IN G M *+ R O || R LOAD ≈ ro || R LOAD

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Example
Approach: Using two-port models.

Signal Propagation:

Δi IN → Δv G → Δi D → Δv E → ΔiC → Δv O = i in → v g → id → v e → ic → v o

v o " vg %" id %" v e %" ic %" v o %

A R0 ≡ = $ '$ '$ '$ '$ '
i in # i in &$# v g '&# id &# v e &# ic &

v e id ( rds(CS) || R IN(CB) ) " r + RL %

= = rds(CS) || rπ(CB) || $$ o(CB) ''
id id # 1+ g m(CB)ro(CB) &

" r +r % 2
= rds(CS) || rπ(CB) || $$ o(CB) ds(PL) '' ≈
# 1+ g m(CB)ro(CB) & g m(CB)

# 2 &# 1 &
A R0 ≈ ( R S ) (−g m(CS) ) %% ((%% g m(CB) + ( ( ro(CB) || R L ) = −2R Sg m(CS) ( ro(CB) || rds(PL) )
$ g m(CB) '$ ro(CB) ('

i. Direct Translation
Norton two-port models are short-circuit translations.

Direct translations do not impose test conditions.

Direct translations for the current buffer:

( " r + R LOAD %+
v in = v e = i in R IN(EQ) = i in ( R S || rπ || R GM(LD) ) = i in *R S || rπ || $ o '-
) # 1+ g m ro &,

Of RS, rπ, and RI, only RI's current io reaches RLOAD.

ve ! 1+ g m ro $
io = ic = = ve # &
R GM(LD) " ro + R LOAD %

ic = igm + iro ∴ ic flows through RLOAD.

v o = v c = ic R LOAD

! v $! i $! v $ ! 1 $
∴ A R0 = # in &# o &# o & = ( R S || rπ || R GM(LD) ) ## && R LOAD
" i in %" v in %" io % " R GM(LD) %

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C. Frequency Response
Wide-Spectrum Model CI ≡ CS || Cπ
RCI ≡ RS || RIN

Load

Source CO ≡ Cµ || CLOAD
RCO ≡ RLOAD || RC

Note: Equivalent shunt resistances do not correspond to short-circuit resistances.

RC Dominance: Equivalent C's, but RCO >> RCI ≈ Loaded 1/gm ∴ pO << pIN.
Response: Cµ and CLOAD shunt energy from vo to establish output pole pO.

1 ≡ R C || R LOAD = #$ro + g m ( rπ || R S ) ro + ( rπ || R S )%& || R LOAD

(
s Cµ + C LOAD ) pO =
1
( )(
2π R C ||R LOAD Cµ +CLOAD ) RC is equivalent shunt resistance,
not short-circuit output resistance.

CS and Cπ shunt energy from vin to establish input pole pIN.

1 # r + Z LOAD & 1
≡ R S || R IN = R S || rπ || % o ( ≈ R S ||
s ( CS + C π ) p 1 $ 1+ g m ro ' gm
IN ≈
# 1 &
2π% R S || ((CS +C π )
$ gm '

But since pO << pIN ∴ RLOAD disappears near pIN.

1
à Z LOAD ≈ << R LOAD
s (Cµ + C LOAD )

Base Degeneration: With resistance RB in series with the base,

vbe drops an rπ fraction of vin ∴ RB base-degenerates ve's gm.

g mrπ
à gm' is a voltage-divided translation of gm: g m' = < gm .
rπ + R B

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Example
Objective: If RS = 100 kΩ, vBS = 0, IC = ID = 25 µA, β0 = 100, KN' = 100 µA/V2,
VA = 1/λ = 50 V, Cπ = CGS = 100 fF, Cµ = CGD = 10 fF, W = 20 µm, L = 2 µm,
RL = 100 kΩ, and CL = 200 fF, determine AI0, pO, and pIN.
Solution:
BJT gm = 980 µS, 1/gm = 1.0 kΩ, rπ = 100 kΩ, and ro = 2 MΩ.
∴ Shunt collector resistance RC(DEG) ≈ 100 MΩ.
∴ AI0 ≈ +0.98 A/A, pO ≈ 7.6 MHz, and pIN ≈ 1.6 GHz.
MOS gm = 224 µS, 1/gm = 4.5 kΩ, and rds = 2 MΩ.
∴ Shunt drain resistance RD(DEG) ≈ 45 MΩ.
∴ AI0 ≈ +0.96 A/A, pO ≈ 7.6 MHz, and pIN ≈ 370 MHz.

RS and rπ steer current away from input.

Dominant low-frequency pole is usually at the output.

3.6. Voltage Follower: A. Large-Signal Operation

Common-Collector and -Drain Configurations

VBIAS is constant.
VO(MIN) = VCE(MIN) or zero and VO(MAX) BJT = vIN – vBE.

Note Bulk Effect in vTN: VO(MAX) MOS = vIN – vGS = vIN – [vTN(f(vBS)) + VDS(SAT)]

ISOURCE(MAX) = f(iB or vIN – vO and vBS) – IBIAS IPULL(MAX) ≤ IBIAS

Depends on base and gate drive and bias. Depends on bias.

Since IBIAS is nearly constant, vBE is constant ∴ vO "follows" vIN à Voltage Follower.

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B. Small-Signal Model
Equivalent Two-Port Model

BJT

MOS and BJT are similar, but rπ is absent and 1/gmb shunts ro.
vo vo 1
à vbs = –vs = –vo ∴ R GMB ≡ = =
i gmb v o g mb g mb

RIN: RLOAD || ro raises RIN like degenerating RDEG in CE BJT.

R IN = R B(DEG) = rπ + (1+ g m rπ ) ( R LOAD || ro )

GM when vo = 0 ∴ iro = iLOAD = 0.

v be
+ v beg m
i r 1
G M v =0 = o = π = + gm ≈ gm
o
v in v be rπ

RO when vin = 0 à Unloaded and undegenerated 1/gm.

∴ ΔvE à ΔvBE à Δigm à Large ΔiE à Low RO.

And
1 1
RO = ro || R GM || rπ = ro || || r ≈
v in =0 gm π gm

Where
vo ve v 1
R GM = = = e =
i gm −v be g m v eg m g m

Voltage Gain:

A V0 ≡ =
(
v o v in G M R O || R LOAD # )1 &#
= %% g m + ((%% ro ||
1 & # 1 &
|| rπ || R LOAD (( ≈ g m %% R LOAD || ((
v in v in $ rπ '$ gm ' $ gm '

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 Analog IC Design

Example
Approach: Using two-port models.
Signal Propagation:
Δi IN → Δv B → Δi E → Δv O = i in → v b → ie → v o

v o " v b %" i e %" v o %

A R0 ≡ = $ '$ '$ '
i in $# i in '&$# v b '&$# i e '&

vb
= R S || R IN(CC) = R S || "#rπ + (1+ g m rπ ) ( R L || ro )$% = R S || "#rπ + (1+ β0 ) ( rds(NL) || ro )$% ≈ R S
i in

ie 1
≡ G M(CC) = + g m ≈ g m If RS << RIN(CC).
vb rπ

vo " 1 % 1
= R O(CC) || R L = $$ rπ || || ro '' || rds(NL) ≈
ie # g m & g m

v o " v b %" i e %" v o % " 1 %

A R0 ≡ ( )( )
= $ '$ '$ ' ≈ R S g m $$ '' ≈ R S
i in $# i in '&$# v b '&$# i e '& # gm &

i. Direct Translation
A voltage follower outputs ie à io = ie.

Current vbe/rπ reinforces vbegm à gm(EFF) = 1/rπ + gm.

RLOAD degenerates gm(EFF) à GM(DEG) = GM(DCE) with gm(EFF).

1
+ gm
ie g m(EFF) rπ
= G M(DEG) = =
vb ! 1$ !1 1$
1+ # g m(EFF) + & R LOAD 1+ # + g m + & R LOAD
" ro % " rπ ro %

ie = irπ + igm + iro = irπ + ic flows through RLOAD.

v o = v e = ie R LOAD
) 1 ,
+ + gm .
v rπ .R
∴ A V0 ≡ o = G M(DEG) R LOAD = +
v in + #1 1& . LOAD
+1+ % + g m + ( R LOAD .
* $ rπ ro ' -

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C. Frequency Response
Wide-Spectrum Model

Source Source
Load Load

MOS and BJT are similar, but rπ is absent and 1/gmb shunts rds because vbs = –vo.
Cπ feed-forwards energy to vo to produce a zero.
iCπ reinforces igm à In Phase à In the left-half plane.
zLHP Location: When iCπ ≥ irπ + igm.
$1 '
iCπ = v besC π z
≡ i rπ + igm = v be & + g m ) ≈ v beg m
gm
% rπ
LHP ≈
(
2πCπ

Cπ shunts vbe ∴ ZIN falls with frequency à Capacitive effect.

igm falls and ZO ≈ 1/gm rises à Inductive effect.

CS, Cµ, Cπ and Cπ, CLOAD shunt energy from vin and vo to establish poles.

Miller Split: Decompose Cπ across non-inverting stage into CMI and CMO.
*, $ gm ' .,
C MI = (1− A V ) C π ≈ +1− & )( R O || R LOAD )/ C π << C π
,- &%1+ g m ( ro || R LOAD ) )( ,0

" 1 %
C MO = $1− ' C π << C π ∴ Cπ has negligible effects on pIN and pO.
# AV &

Case 1. Normally, RS || RB(DEG) >> RGM(DEG) || ro || RLOAD ∴ CI shunts first.

1
≡ R S || R B(DEG) = R S || %&rπ + (1+ β0 ) ( R LOAD || ro )'( ≈ R S
s (CS + Cµ ) 1
p IN ≈
2πR S (CS +Cµ )

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Past pIN, RS disappears ∴ RGM(DEG)'s degeneration lightens.

AV is still nearly 1 ∴ Cπ is still negligible.

∴ CO shunts RLOAD || (rπ + ZCI) || RGM(DEG) || ro:

1 1 rπ + Z CI
≡ R LOAD || ( rπ + Z CI ) || R GM(DEG) || ro ≈ =
sC LOAD pO ≈
gm' g m' g m rπ
2πC LOAD

Case 2. If RS ≈ RGM ∴ CO and CI both shunt at high frequency:

1 1
≡ R LOAD || rπ || R GM(DEG) || ro ≈ R GM(DEG) ≈
sC LOAD pO'≈
gm gm
2πC LOAD

1 1
≡ R S || R B(DEG) ≈ R S ≈
s (CS + Cµ ) g m(S) g m(S)
p IN'≈
2π(CS +Cµ )

Note pO is usually high and normally precedes zLHP's gm/Cπ à Pole–zero pair.

Example
Objective: If RS = 100 kΩ, vBS = 0, IC = ID = 25 µA, β0 = 100, KN' = 100 µA/V2,
VA = 1/λ = 50 V, Cπ = CGS = 100 fF, Cµ = CGD = 10 fF, W = 20 µm, L = 2 µm,
RL = 100 kΩ, and CL = 200 fF, determine AV0, pIN, pO, and zLHP.
Solution:
BJT gm = 980 µS, 1/gm = 1.0 kΩ, rπ = 100 kΩ, and ro = 2 MΩ.
∴ Shunt input resistance RB ≈ 10 MΩ.
∴ AV0 ≈ +0.99 V/V, pIN ≈ 160 MHz,
pO ≈ 810 MHz, and zLHP ≈ 1.6 GHz.
MOS gm = 224 µS, 1/gm = 4.5 kΩ, and rds = 2 MΩ, and RG à ∞.
∴ AV0 ≈ +0.96 V/V, pIN ≈ 160 MHz,
pO ≈ 185 MHz, and zLHP ≈ 360 MHz.

Pole–zero pair pO–zLHP à zLHP recovers pO's phase.

MOS's lower gm reduces AV0, pO, and zLHP.

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3.7. Summary: A. Primitives Transconductor

Possible Transistor Configurations
Common Emitter (Source)

Base to collector: ic = vbGM à Transconductor.

Common Collector (Drain)

Voltage Follower
Base to emitter: vb ≈ ve à Voltage Follower.

Common Base (Gate)

Emitter to collector: ie ≈ ic à Current Buffer.

Relative Magnitudes: Current Buffer

gm >> 1/rπ, gmb >> go, gds ∴

1/gm << rπ, 1/gmb << ro, rds << gmrπro, gmrdsrds
Cµ, CGD << Cπ, CGS(SAT) << CINTENTIONAL << COFF-CHIP

Low << Moderate << High << Very High

B. Expressions
Small-Signal Translations:

RE/S and gmb degenerate vbe/gs's gm. ie's vbe/rπ

ic/d/s gm reinforces vbegm.
≡ G M(EQ) =
v b/g ⎛ 1⎞ ⎛ 1⎞
1+ ⎜ g m + g mb + ⎟ R E/S ⎜gm + ⎟
⎝ ro ⎠ ie ⎝ rπ ⎠
=
RE/S loads RB(EQ) and RC/D(EQ): v ⎡⎛ 1 ⎞ 1⎤
b
1+ ⎢⎜ g m + ⎟ + g mb + ⎥ R E/S
⎣⎝ rπ ⎠ ro ⎦
vb
≡ R B(EQ) ≈ rπ + (1+ g m rπ ) R E = rπ + (1+ β0 ) R E
ib
v c/d
≡ R C/D(EQ) = ro + (g m' + g mb ) ro R E/S' + R E/S' R E/S' = R E/S || ( rπ + R B )
ic/d

RC/D loads RE/S's 1/gm, rπ + RB shunts RE, and gmb reinforces gm:

v e/s ⎡ r +R ⎤ v eg mrπ
≡ R E/S(EQ) = ⎢ o C/D
⎥ || ( rπ + R B ) v eg m' =
ie/s ⎢⎣1+ (g m' + g mb ) ro ⎥⎦ rπ + R B
RB degenerates veb's gm.
RGM

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 Analog IC Design

Emitter/Source Resistance
Emitter/source's RGM resistance is a 1/gm translation.
rπ and RB shunt emitter's RGM.
Plain Base Degeneration Loading Effect

R GM || ( rπ + R B ) R GM || ( rπ + R B ) R GM || ( rπ + R B )

⎛ 1 ⎞ ⎛ rπ + R B ⎞ ⎛ ro + R C ⎞
⎜ ⎟ || ( rπ + R B ) ⎜ ⎟ || ( rπ + R B ) ⎜ ⎟ || ( rπ + R B )
⎝ gm ⎠ ⎝ g m rπ ⎠ ⎝ 1+ g m ro ⎠
Plain RGM. Degenerated RGM. Loaded RGM.

Loaded RGM reduces to 2/gm when RC ≈ ro and to rX when RC ≈ gmrorX >> ro.

C. Small-Signal Analysis
Approach: Trace small-signal path and track voltage–current conversions.

Insightful Approach: Use direct translations.

Example: iin à vg(CS) à id(CS) à ve(CB) à ic(CB) à vo1 à ie(CC) à vo

v o1 ⎛ 1 ⎞
= ( R S ) (−g mCS ) ( rdsCS || rπCB || R GM(CB) ) ⎜⎜ ⎟⎟ ( rdsPL || R B(CC) ) ≈ −R Sg mCSrdsPL
i in ⎝ R GM(CB) ⎠

⎡ 1 ⎤
⎢ g mCC + ⎥
vo ⎢ rπCC ⎥r
= ≈1
v o1 ⎢ ⎛ 1 1 ⎞ ⎥ dsNL
⎢1+ ⎜ g mCC + + ⎟ rdsNL ⎥
⎣ ⎝ rπCC roCC ⎠ ⎦

roCB + ( rdsPL || R B(CC) ) 2

Where: R GM(CB) = ≈
1+ g mCBroCB g mCB

R B(CC) = rπCC + (1+ β0CC ) ( rdsNL || roCC )

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D. Noise Analysis
Refer measured non-degenerated noise current iN* to base or gate vB/G* with gm.
Translate forward vB/G* to collector/drain current iC/D*.
iN
*
v B/G =
*
iC/D = v B/G G M
* *

gm
Degenerated Transistors:
Translate vB/G* to degenerated iC/D* with degenerated gm.
" i * %" gm iN
% *
iC/D = v B/G G M ≈ $ N '$
* *
'=
# g m &# 1+ g m R DEG & 1+ g m R DEG
à Emitter/source resistors degenerate noise contributions.
Multiple Noise Sources:
Random and uncorrelated ∴ Use root–square sum.

* 2 * 2 * 2 * 2
v TOTAL =
*
(v ) + (v ) + (v ) +... + (v )
N1 N2 N3 N(K)

à Statistical sum magnifies effects of dominant terms ∴ Others fade.

Example
Every component contributes noise to input-referred noise voltage vIN*.

iCS
*
* 2 * 2 * 2 * 2 * 2 * 2
v IN = (v ) + (v ) + (v ) + (v ) + (v ) + (v )
*
v NCS =
*
NRS NCS NCB NPL NCC NNL
g mCS
* 2 * 2 * 2 * 2
≈ (v ) + (v ) + (v ) + (v )
NRS NCS NPL NNL

!i *$ ! 1 $ ! i * $( g mCB +! 1 $
v NCB = # CB &G MCB #
*
& = # CB &* -# &
" g mCB % " g mCS % " g mCB %*)1+ g mCB ( rπCB || rdsCS ) -," g mCS %

i PL R O1 i PL ( rdsPL || R B(CC) || R C(CB) ) i PL

* * *
v NPL =
*
≈ ≈
A V1 g mCS ( rdsPL || R B(CC) ) g mCS

⎛ i * ⎞ ⎛ 1 ⎞ ⎛ i * ⎞⎡ 1 ⎤
v NCC = ⎜ CC ⎜
*
⎟ ≈ ⎜ CC ⎟⎢ ⎥
⎝ g mCC ⎠⎝ A V1 ⎠ ⎝ g mCC ⎠⎢⎣ g mCS ( rdsPL || R B(CC) ) ⎥⎦
First gain stage
⎤ suppresses
* 1+ g mCC ( rdsNL || roCC )
⎛ i * ⎞⎛ 1 ⎞ ⎡ ⎤⎡ 1
v NNL = ⎜⎜ NL ⎟⎟⎜ ⎟ ≈ i NL ⎢
*
⎥⎢ ⎥
⎝ G M(CC) ⎠⎝ A V1 ⎠ ⎣ g mCC ⎦⎢⎣ g mCS ( rdsPL || R B(CC) ) ⎥⎦ output noise.

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E. Offset Analysis
Collector/drain voltage difference ΔvC/D produces a small offset current ΔiC/D.
Measured non-degenerated current mismatches ΔiM* are usually 5%–15%.
ΔiM* and ΔvC/D are small ∴ Treat as small signals.
Refer ΔiM* to base or gate ΔvB/G* with gm.
ΔvC/D is systemic and ΔiM* is random.
∴ Linear and root–square sum: iOS = iOS(S) ± iOS*.
Degenerated Transistors:
Translate gate offset ΔvB/G* to degenerated ΔiC/D* with gm(DEG).
⎛ %I ⎞⎛ g m12 ⎞ %I12
iOS = Δi12 ≈ ⎜ 12 ⎟⎜
* *
⎟=
⎝ g m12 ⎠⎝ 1+ g m12 R 34 ⎠ 1+ g m12 R 34
ΔvC/D into drain resistance RD produces ΔiOS(S).
⎛ i ⎞ Δv D Δv D
iOS(S) = Δv D ⎜ d ⎟ = =
⎝ v d ⎠ R D12 rds12 + R 34 + g m12 rds12 R 34
à Emitter/source resistors degenerate mismatch effects.

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