Analog IC Design

Chapter 6. Operational Amplifiers

Outline
6.1. Generalities

6.2. Power-Supply Rejection

6.3. Output Stages

6.4. Two-Stage Class-A Transconductor

6.5. Class-AB Amplifiers

6.6. Current-Mode Amplifiers

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6.1. Generalities: A. Characteristics – Ideal Op Amp

High ZIN Low VOFFSET

Symbol:
Low ZO High SR ≡ dvO/dt
High AV High iO(MAX)
High fBW High ICMR
Low PVDD/VSS High ΔvO(MAX)
Low Cost Wide Temperature Range
High SNR Low Headroom
vO = (vP – vN)AV ≡ vIDAV
… …
Headroom ≡ Min{vDD – vSS}
Null Ports:

High-Input Impedance ZIN à iP ≈ iN ≈ 0.

Virtual Short à Series-mixed negative feedback virtually shorts input terminals.

Actual Op Amp
Differential- and common-mode response:
"v +v %
v O = ( v P − v N ) A V + $ P N ' A C ≡ v ID A D + v IC A C
# 2 &
Differential-mode frequency response:
z1,… are zeros.
" s %
A V0 $1+ '...
AV =
# 2πz1 &
=
( )
A V0 2πp1 2πp 2 ... s + 2πz1 ...
"
$1+
s % "
'$1+
s %
'...
( )( )
2πz1... s + 2πp1 s + 2πp 2 ...
# 2πp 1 &#
2πp 2&
p1, p2,… are poles.

Insightful format because AV = AV0 at low frequency when s = 0.

One dominant low-frequency bandwidth-setting pole.

∴ All other poles are at or above f0dB.

f0dB = GBW = AV0pBW OL.

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v dd A VDD v dd v ic A C v ic
v PSRR+ = = v CMRR = =
AD PSRR + AD CMRR

v ss A VSS v ss
v PSRR− = =
AD PSRR −

RO = Output resistance IOS* = Input-referred offset current (IBP – IBN)

RID = Differential input resistance VOS* = Input-referred offset voltage
CID = Differential input capacitance vN* = Input-referred noise voltage
RIC = Common-mode input resistance iN* = Input-referred noise current
CIC = Common-mode input capacitance PSRR = Power-Supply Rejection Ratio
IBP and IBN = Input bias currents CMRR = Common-Mode Rejection Ratio

B. Composition
Differential Input Stage:
Buffer differential input signals à High input impedance.
Convert differential input to ground-referenced signal (although not always).
Gain Stage: Amplify signals.

Output Buffer: Drive heavy loads à Low output impedance.

Compensation: Stabilize circuit when looped with negative feedback.
Bias: Establish bias currents and voltages.
Design Strategy:
Translate
Voltages to Currents
Currents to Currents
Currents to Voltages
Voltages to Voltages

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Internal Components

Loads

Gain Stages

Bias Circuits
Using N- and P-type MOSFETs and BJTs.

6.2. Power-Supply Rejection

Power-supply rejection ratio PSRR is a measure of
how much a circuit favors input signals over supply ripples.
à Ratio of forward gain
to supply–output gain.

AV
v dd/ss =0
PSRR +/− ≡
A VDD/VSS
v id =0

Negative feedback opposes the effects of supply noise à Suppresses Noise.

vo = (0 – vo)AV + vdd/ssAVDD/VSS ∴

v dd/ss A VDD/VSS v dd/ss A VDD/VSS v dd/ss

vo = ≈ =
1+ A V AV PSRR +/−

As long as AV > 1 à Up to f0dB.

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A. Power-Supply Gain
Voltage-Divider Model: Model what connects to the output vO.

Output transistors MT and MB

couple (voltage-divide) supply noise.

∴ High supply impedances

limit supply noise.

Output transconductors igmt and igmb

inject supply noise.

Grounded loads ZLOAD shunt output noise.

Shunt feedback shunts output noise with

Z OL Z OL 1 1
ZSHUNT = ≡ = ≡
A OLβ FB A G.OL Z OLβ FB A G.OLβ FB G LG

B. Feed-Through Noise: i. In Mirrors

Current mirrors convert supply noise voltage vac to noise current iac.

Supply impedance ZO limits noise current iac.

Current mirrors reproduce noise current iac.

∴ High supply impedance limits noise current iac à iIN's ZO should be high.

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ii. From Differential Stages

P-type mirrors
into balanced loads:
Reproduce positive-
supply noise vdd.
Cancel negative-
supply noise vss.

N-type mirrors
into balanced loads:
Cancel positive-
supply noise vdd.
Reproduce negative-
supply noise vss.

iii. In Power Transistors

Common-Mode Concept:
MOS iD ∝ (|vG – vS| – |vT|)2 and BJT iC ∝ exp(|vB – vE|/Vt).
∴ Noise that is common to gate/base and source/emitter terminals cancels.
Possible Output Terminals:
Source/emitter: Voltage followers reproduce gate noise.
∴ Remove gate noise.

Drain/collector: Unmatched gate–source noise in CS/CE transconductors

produces noise current ∴ Reproduce supply noise in gate.
Eliminate feed-through noise from output transistors with:
Balanced mirror-gain stages and coupling common-mode capacitors.

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6.3. Output Stages: A. Class A, i. Follower

Class-A Transistor: Always conducts current ∴ Considerable power.

Conducts across 360° of a sinusoid: Conduction angle is 360°.

iC/D, gm, and gain > 0 across vO's swing ∴ vO is linear.

Class-A Stage: A current source biases a Class-A transistor.

vO = vIN – vGS1 = vIN – vTN1 – VDS1(SAT).

Class-A NMOS Follower
à vIN(MAX) and vGS (i.e., IQ2 and RL) limit vO(MAX).

à VDS2(SAT) or RL limits vO(MIN).

iO ≈ 0.5KN'S1[(vIN – vO) – vTN1]2 – IQ2.

à vIN(MAX), vO, and IQ2 limit iO(MAX)+.

à Bias IQ2 limits iO(MAX)–.

Bulk effect raises vTN1 à Reduces vO(MAX) and iO(MAX)+.

Example: vIN(MAX) = vDD = –vSS = 2.5 V, KN' = 150 µA/V2, γN = 0,

VTN0 = 0.7 V, (W/L)1 = 300, (W/L)2 = 150, IQ2 = 1 mA, and RL = 1.5 kΩ.
Solution: vO(MAX) = iO(MAX)+(1.5k) = 1.5 V and VDS2(SAT) ≈ 300 mV.
∴ vO(MIN) = Max{–2.5 + 300m, –(1m)(1.5k)} = –1.5 V
iO(MAX)– = 1 mA when vIN shuts M1. vO(MAX)
iO(MAX) ≈ 0.5(150µ)(300){[2.5 – iO(MAX)+(1.5k)] – 0.7}2 – 1m ≈ 1 mA
+

Power-Supply Rejection
MT's igmt reproduces gate noise vdd or vss in vO.
MB's igmb mirrors RBIAS's noise vss/RBIAS and vdd/RBIAS.
MT's 1/gmT shunts MB's noise in igmb and
MT's and MB's rds noise contributions.

v dd/ssg mT rdsB ⎛ v dd v v dd v ss ⎞⎛ 1 ⎞
vo ≈ + ⎜− + ss + + ⎜ ⎟ ≈ v dd/ss
1+ g mT rdsB ⎝ R BIAS R BIAS rdsT +1/g mT rdsB +1/g mT ⎠⎝ g mT ⎠

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Power Efficiency η
For maximum power efficiency (i.e., long operational life), reduce power losses ∴
Low vDS(AVG) à For sinusoids, vO(PEAK)'s swing close to the supplies vDD and |vSS|.
Ideal Maximum-Efficiency ηMAX Waveforms:
When vDD = |vSS|, vO(MAX) ≈ |vO(MIN)| ≈ vDD.
∴ vDS1(MIN) ≈ 0, vDS1(MAX) ≈ vDD – vSS = 2vDD.
At vO(MIN) and vDS1(MAX), iD1 can near zero.
For a symmetrical vO, iO(MAX)+ ≈ iO(MAX)– = IQ.
∴ iD1(MAX) ≈ 2IQ at vO(MAX) and vDS1(MIN).
PM1 = vDS1iD1 = [vDD(1 + sinωt)] [IQ(1 – sinωt)]
= vDDIQ(1 – sin2ωt) ∴ PM1(MAX) = vDDIQ at Q point.
η ≡ Fraction of PSUPPLIES delivered: ⎛ Maximum Possible η
v R(PK) ⎞⎛ i R(PK) ⎞
⎜ ⎟⎜ ⎟
PO v R(RMS)i R(RMS) ⎝ 2 ⎠⎝ 2 ⎠ v R(PK)i R(PK) v I
η= = = = < DD Q = 25%
PSUPPLIES ( v DD − v SS ) i DD(AVG) (v DD − v SS ) IQ 2 (v DD − v SS ) IQ 4v DDIQ

Maximum efficiency when iD vs vDS with Parabolas of Constant Power

vDS(AVG) is lowest: vDS(MAX) = 2vDD.

Drive is symmetrical: iD(MAX) = 2IQ.

When designed for maximum

efficiency, PM1(MAX)

is at Q point.

Load-line slope is 1/RL.

à Pivots about Q point with RL.

With higher RL: vO bottoms to vSS before iD1 is zero à iD1 ≠ 0 at 2vDD ∴ Higher PM1.

With lower RL: M1's 2IQ does not raise vO to vDD à vDS1 ≠ 0 at 2IQ ∴ Higher PM1.

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Design Example Objective:

Select RL for maximum efficiency
when vTN ≈ 0.5 V, VDS(SAT) = 0.2 V,
vIN(MAX) ≈ vDD = –vSS = 5 V, and IQ2 = 2 mA.
Solution: vO(MAX) ≈ vDD – vGS1 = 4.3 V
≡ (2IQ2 – IQ2)RL = IQ2RL
∴ RL ≈ 4.3 V/2 mA = 2.15 kΩ

PO 4.3m v R(PK) 1 ⎛ 4.3 ⎞

Efficiency = = = = ⎜ ⎟ = 21.5%
PSUPPLIES 20m 2 ( v DD − v SS ) 4 ⎝ 5 ⎠
!v $! I $ (4.3)(2m)
PO = v R(RMS)i R(RMS) = # R(PK) &# Q2 & = = 4.3 mW
" 2 %" 2 % 2

PSUPPLIES = ( v DD − v SS ) i DD(AVG) = (2v DD )IQ2 = (10)2m = 20 mW

Ideally: PO(MAX) at vO(MAX) ≈ vDD is 5 mW ∴ Efficiency ≤ 5m/20m = 25%.

ii. Transconductor
VDS1(SAT), VSD2(SAT), and RL limit ΔvO(MAX).

à vGS does not limit ΔvO(MAX).

Class-A
NMOS iO ≈ IQ2 – 0.5KN'S1(vIN – vSS – vTN1)2.

CS Stage à Bias IQ2 limits iO(MAX)+.

à vIN(MAX) and IQ2 limit iO(MAX)–.

Example: vIN(MAX) ≈ vDD = –vSS = 2.5 V, KN' = 150 µA/V2, KP' = 50 µA/V2, γN = 0.5,

VTN0 = 0.7 V, (W/L)1 = 300, (W/L)2 = 150, IQ2 = 1 mA, and RL = 1.5 kΩ.

Solution: iO(MAX)+ = 1 mA when vIN shuts M1.

iO(MAX)– = |vO(MIN)|/1.5k = 1.45 mA

VSD2(SAT) = 0.27 V ∴ vO(MAX) = Min{2.5 – 0.27, (1m)(1.5k)} = 1.5 V

2 " v O(MIN) %
v O(MIN) = −2.5 + $$ +1m '' ≈ −2.17 V
(150µ)(300) # 1.5k &

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Design Example Objective:

Select RL for maximum efficiency
when vTN = 0.5 V, VDS(SAT) = 0.2 V,
vIN(MAX) ≈ vDD = –vSS = 5 V, and IQ2 = 2 mA.
Solution: vO(MIN) ≈ vSS + VDS(SAT) = –4.8 V
≡ (IQ2 – 2IQ2)RL = –IQ2RL
∴ RL ≈ 4.8 V/2 mA = 2.4 kΩ

PO 4.8m v R(PK) 1 ⎛ 4.8 ⎞

Efficiency = = = = ⎜ ⎟ = 24%
PSUPPLIES 20m 2 ( v DD − v SS ) 4 ⎝ 5 ⎠

!v $! I $ (4.8)(2m)
PO = v R(RMS)i R(RMS) = # R(PK) &# Q2 & = = 4.8 mW
" 2 %" 2 % 2

PSUPPLIES = ( v DD − v SS ) i DD(AVG) = (2v DD )IQ2 = (10)2m = 20 mW

Class-A CS/CE efficiency is closer to 25% than that of a Class-A Follower.

Power-Supply Rejection
When driven by a P-type mirror, MT's vg ≈ vdd and igmt ≈ 0.
MB's igmb mirrors RBIAS's noise vss/RBIAS and vdd/RBIAS.
MT's rdsT and MB's rdsB voltage-divide supply noise.
⎛ v v ⎞ v r v r
v o ≈ ⎜ − dd + ss ⎟ ( rdsB || rdsT ) + dd dsB + ss dsT
⎝ R BIAS R BIAS ⎠ rdsT + rdsB rdsT + rdsB

Distortion
Characterized by influence on a pure sinusoid à vin = VPsin(ωt).
Output with distortion: vo = a1VPsin(ωt) + a2VPsin(2ωt) + … + aNVPsin(Nωt)
Harmonic Distortion: Harmonic-to-fundamental signal-strength ratio: HDi ≡ |ai|/|a1|
Total Harmonic Distortion: Combined square–root contributions:
a 2 + a 3 +... + a N
2 2 2
Small signals are linear. THD ≡
a1
Large signals and square law for FETs and exponential for BJTs.

∴ iD/C in gm and gain vary with vO à Gain variation produces nonlinearity.

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In BJT
vIN = VBE + vin ∴
( "V % " v %+ ( "v % +
v O = R L ( I Q − i C ) = R L *I Q − I S exp $ BE ' exp $ in '- = −R L I Q *exp $ in ' −1-
) # Vt & # Vt &, ) # Vt & ,
Taylor-Series Expansion: Exp (x) = 1 + x + x2/2! + x3/3! + ··· ∴
(" % 2 3 +
v 1"v % 1"v %
v O = −R L I Q *$ in ' + $ in ' + $ in ' +...- ≡ a 1v in + a 2 v in 2 + a 3 v in 3 +...
*)# Vt & 2 # Vt & 6 # Vt & -,

R L IQ R L IQ R L IQ
Where a1 = − a2 = − 2
a3 = − 3
Vt 2Vt 6Vt
∴ vin = VPsin(ωt) à vO = a1VPsin(ωt) + a2VP2sin2(ωt) + a3VP3sin3(ωt) + ···

a 2 VP 2 # a 3 VP 3 #
Or v O = a 1VP sin (ωt ) + $1− cos ( 2ωt )%& + $3sin (ωt ) − sin (3ωt )%& +...
2 4
" a V 2 %" 1 % V " a V 3 % " 1 % 1 " V %2
∴ HD 2 ≈ $ 2 P '$ '= P HD 3 ≈ $ 3 P '$ '= $ P '
# 2 &# a1VP & 4Vt # 4 &# a1VP & 24 # Vt &

Example: If VP = 0.5Vt ∴ HD2 = 12.5% and HD3 ≈ 1%.

Example
Class-A CE NPN with ΔvO(PEAK) = ±0.6 V, RL = 1 kΩ, and IQ = 1.86 mA:
AV ≈ –gm1RL = –70.6 ∴ ΔvIN(PEAK) ≈ ΔvO(PEAK)/AV = ±0.6/70.6 = ±8.5 mV
HD2 = VP/4Vt = 8.5m/4(26m) = 8.2% à Significant.
HD3 = VP2/24Vt2 = (8.5m)2/24(26m)2 = 0.45% à Less significant.

Origin of distortion: Gain variation across vO's swing.

⎛ 0.6 ⎞
⎛ iC(MIN) ⎞ ⎛ IQ − i R(PK) ⎞ ⎜ 1.86m − ⎟
AV v = −⎜ ⎟ R L = −⎜ ⎟ R L = −⎜ 1k ⎟ (1k) = −49
O(MAX)
⎝ Vt ⎠ ⎝ Vt ⎠ ⎜ 26m ⎟
⎝ ⎠
⎛ 0.6 ⎞
⎛ iC(MAX) ⎞ ⎛ IQ + i R(PK) ⎞ ⎜ 1.86m + ⎟
AV v = −⎜ ⎟ R L = −⎜ ⎟ R L = −⎜ 1k ⎟ (1k) = −95
O(MIN)
⎝ Vt ⎠ ⎝ V t ⎠ ⎜ 26m ⎟
⎝ ⎠
The gain of the follower varies less (i.e., is more linear) because
inherent negative feedback suppresses gain sensitivity.

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B. Class B/AB
Class-B Transistor: Conducts half the sinusoid cycle ∴ Conduction angle is 180°.

Less conduction than Class A à More power efficient than A.

iC/D, gm, and gain = 0 when vO crosses zero ∴ Less linear than A.

Class-AB Transistor: Conducts more than half, but less than a full cycle.

Conduction angle is between 180° and 360°.

Less conduction than Class A à More efficient, but less linear than A.

More conduction than Class B à Less efficient than B.

iC/D, gm, and gain > 0 when vO crosses zero ∴ More linear than B.

Class-B/AB Stage: Two Class-B/AB push–pull transistors.

One transistor conducts when the other does not.

i. Followers
vIN, vGS1 and vSG2 (and RL) limit ΔvO(MAX).

vIN and vO limit gate drive à Limit iO(MAX).

à IQ does not limit iO(MAX).

Bulk effect reduces ΔvO(MAX) and iO(MAX).

M1 and M2 conduct less than the full cycle ∴ More efficient than Class A.

Maximum possible power efficiency η with lowest vDS à When vR(PK) ≈ vDD.

"v %" v % Maximum Possible η

$$ R(PK) ''$ R(PK) '
v R(RMS)i R(RMS) $ '
PO # 2 &# R L 2 & πv R(PK) πv DD
η= = = = < = 78.5%
PSUPPLIES v DDi DD(AVG) + v SS i SS(AVG) "v % "v (
% 2 2v
v DD $$ R(PK) '' + v SS $$ R(PK) ''
) DD
4v DD
# πR L & # πR L &
E.g.: If vDD = 5 V
Each transistor conducts half the cycle from each supply.
and vR(PK) = 4 V,
With symmetrical supplies à vDD = |vSS|. η ≈ 62.8%.

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Distortion
iD1 and iD2 rise with a higher gate–gate bias voltage.
Higher vG1 – vG2 à Higher gate drive vGS1 + vGS2.
iL, iC/D, and gm fall to minimum when vO crosses zero.
∴ Produces cross-over distortion.

Class B Class AB

M1 and M2 are off. M1 and M2 are on.

Cross-over distortion when iD12 = 0. iD12 ≠ 0 à Less cross-over distortion.

Followers are linear because iD ≠ 0. Followers are linear because iD ≠ 0.
Each transistor conducts 180°. Each transistor conducts > 180°.

Shorted-Gates Class-B Example

M1 and M2:

Push–Pull Output

Shorted Gates:

Class-B Battery

Gate–gate bias voltage is zero ∴ iD1 = iD2 = 0 when vO is zero.

à M1 and M2 shut when vIN is within vTN and |vTP| of 0 V.

à Class-B operation ∴ Considerable cross-over distortion.

vO(MAX) = vIN(MAX) – vGS1 = vIN(MAX) – vTN – VDS1(SAT)

vO(MIN) = vIN(MIN) + vSG2 = vIN(MIN) + |vTP| + VSD2(SAT)

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Diode-Stack Class-B/AB Example: "Diamond" Driver

M1 and M2: Push–Pull Output

IQ–M7–M6: Bias Current

M4–M5 Diode Stack: Class-B/AB Battery

+
VBAT M3: CS Amplifying Driver
–
vGS loop sets iD1 and iD2 from:

vGS5 + vSG4 = Constant ≡ VBAT = f(IQ) ∴

VSD4(SAT) + VDS5(SAT) = VSD2(SAT) + VDS1(SAT)

Operation: When M2 sinks iL, vSG2 is higher ∴ VBAT reduces vGS1 to set iD1.
When M1 supplies iL, vGS1 is higher ∴ VBAT reduces vSG2 to set iD2.
When vO is zero, iD1 = iD2 and VBAT sets iD12.
If VBAT is low, iD12 = 0 when vO = 0 à Class B.
If VBAT is high, iD12 > 0 when vO = 0 à Class AB.

ii. Transconductors

VDS1(SAT) and VSD2(SAT) (and RL) limit ΔvO(MAX).

à vGS does not limit ΔvO(MAX).

vIN limits gate drive à Limits iO(MAX).

à vO and IQ do not limit iO(MAX).

vDS(MIN) of CS < vDS(MIN) of Follower ∴ More efficient than AB–B followers.

Example: If vDD = –vSS = 5 V and vR(PK) = 4.8 V.

PO π⎛ v ⎞ π ⎛ 4.8 ⎞
η= = ⎜ R(PK) ⎟ = ⎜ ⎟ ≈ 75.4% à Closer to 78.5%.
PSUPPLIES 2 ⎝ v DD − v SS ⎠ 4 ⎝ 5 ⎠

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Distortion
iD1 and iD2 rise with a lower gate–gate bias voltage.
Lower vG2 – vG1 à Higher gate drives |vGS's|.
iL, iC/D, and gm fall to minimum when vO crosses zero.
∴ Produces cross-over distortion.

Class B Class AB

M1 and M2are off. M1 and M2 are on.

Cross-over distortion when iD12 = 0. iD12 ≠ 0 à Less cross-over distortion.

Transconductors produce gain distortion. Transconductors produce gain distortion.
Each transistor conducts 180°. Each transistor conducts > 180°.

Shorted-Gates Class-AB Example

M1 and M2:

Push–Pull Output

Shorted Gates:

Class-AB Battery

Gate–gate bias voltage is zero:

Gate drives peak when vO transitions à Shoot-through current can be excessive.

∴ Too lossy for many analog applications.

M1 and M2 shut when vIN is within |vTP| and vTN of vDD and vSS.

à vO(MAX) = vDD and vO(MIN) = vSS with capacitive loads à Wide swing.

∴ Useful as digital inverter.

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Diode-Stack Example
MPO–MNO: Push–Pull Output Operation:
MPP–MNP: Push Bias MNN and MPP voltage-buffer vIN.
MNN–MPN: Pull Bias
MPN and MNP current-buffer iNN and iPP.

MNM–MNO and MPM–MPO mirror iNN and iPP.

Bias:

iNO and iPO rise with iNN and iPP.

+
iNN and iPP rise with gate–gate voltage VGN – VGP.
VBAT
iNO pulls current when vIN > vTN + |vTP| + VGP.
–
iPO supplies current when vIN < VGN – vTN – |vTP|.

Class AB: iNO = iPO > 0 when vO crosses zero.

If VBAT ≡ VGN – VGP > 2vTN + 2|vTP|.

Min{vDD – vSS} > 4|vGS| + 2VDS(SAT) Class B: iNO = iPO = 0 when vO = 0 otherwise.

Adaptive-Stack Example
Operation: MNIN amplifies and drives vIN. MPO–MNO: Push–Pull Output

When vIN is low à iNIN is low. MNB–MPG: B/AB Bias

∴ IPI raises vGNO à MNO pulls iRL.

pG+
MNB shuts and MPB current-buffers IPI.

VGP, VSGPB, and IPI bias MPO to IPO(MIN).

When vIN is high à iNIN is high.

∴ MNB carries IPI and MPB shuts.
pG–
iNIN lowers vGPO à MPO supplies iRL.

VGN, VGSNB, and IPI bias MNO to INO(MIN). Min{vDD – vSS} > 2|vGS| + VDS(SAT)
Bias: VGN and MNB bias MNO and VGP and MPB bias MPO.
Class AB: iNO = iPO > 0 when vO = 0 if VGN > vSS + 2vTN and VGP < vDD – 2|vTP|.

Class B: iNO = iPO = 0 when vO = 0 otherwise.

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C. Summary
Conduction Angle: Class A's > AB's > B's.

vGS/BE limits followers' ΔvO(MAX) and VDS(SAT)/CE(MIN) limits transconductors' ΔvO(MAX).

vO limits gate drive in followers, but not in transconductors.

More efficient when transistors conduct less ∴ ηB > ηAB > ηA.

More efficient when vDS/CE is low ∴ ηCS/CE > ηFollowers.

1 π
Maximum Efficiency: = 25%
ηA < ηB < = 78.5%
4 4
More linear when current and gain vary less ∴

HDA < HDAB < HDB and HDFollowers < HDCS/CE.

More cross-over distortion when vO crosses zero if current is zero ∴

Substantial in B. Less in AB. Little in A.

More current when gate/base drive is high ∴ iCS/CE(MAX) > iFollowers(MAX).

6.4. Two-Stage Class-A Transconductor

Process differential input: Combine and amplify signals:
Differential Pair M1–M2 Pair into mirror load M3–M4.
Amplify and drive load:
Class-A CS transconductor MA.
Bias:
Reference circuit generates IBIAS.
MB, MT, and MB2 mirror IBIAS.
Input and feedback
set VN, VP, and VO.
Compensation:
Design Feature: Miller CC splits pGA and pO.

vSD3 = vSG3 ≈ vSD4 = vSGA and vDS1 ≈ vDS2 when vSG3 ≡ vSGA.
∴ Systemic input-referred offset VOS(S) is practically nil.

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A. Static Parameters
Bias Currents (where Si ≡ Wi/Li):
IT = IBIAS(ST/SB)
IA = IBIAS(SB2/SB)
With negative Feedback, vN ≈ vP.
∴ I13 ≈ I24 ≈ 0.5IT.

To match VSD3(SAT) and VSDA(SAT),

I13/S3 should match IA/SA.
Limits:
vIC(MAX) = vDD – vSG3 – VDS1(SAT) + vGS1
= vDD – |vTP| – VSD3(SAT) + vTN
vIC(MIN) = vSS + VDST(SAT) + vGS1
= vSS + VDST(SAT) + vTN + VDS1(SAT)
vO(MAX) = vDD – VSDA (SAT)
vO(MIN) = vSS + VDSB2(SAT)
iO(MAX)+ = 0.5KP'SA(vSGA(MAX) – |vTP|)2 – IB2
Drive: vSGA(MAX) = vDD – (vIC(MAX) – vTN2)
iO(MAX)– = IB2 = IBIAS(SB2/SB)

B. Slew Rate
Slew-Rate Limit ≡ Maximum possible dvO/dt.
Largest C's limit circuit to dvC/dt ≡ iC/C ∴ Consider largest C's à CC and CL.

IT

iA+
SR– IT
IT IT IT
iL iL
IB2
SR+
IB2

Slew-Rate Scenarios: CC by i2 or i4 à SRC± = IT/CC Design usually

CL by iA – i2 – IB2 à SRL+ = (iA – IT – IB2)/CL ensures:
CL by IB2 – i4 à SRL– = (IB2 – IT)/CL iA+ >> IB2 >> IT.

vo/vgA is high ∴ Large ΔvO's result from small ΔvGA's: ΔvGA ≈ 0 ∴ SRC ≈ SRO.
Worst-Case SRO: SRO+ = Min{SRC+, SRL+} ≈ IT/CC, SRO– = Min{SRC–, SRL–} ≈ IT/CC.

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 Analog IC Design

C. Offset and Electronic Noise

Systemic Offset VOS(S): Design ensures vDS1 ≈ vDS2 and vSD3 ≈ vSD4 ∴ VOS(S) ≈ 0.

Random Offset VOS* results from mismatched transistors.

Differential pair M1–M2's Δv12 appears across input vID.

Load mirror M3–M4's Δi34 offsets i12.

Diode connections M3–MA's Δv3A alters vGA, except gain GDRD2 divides it.

Bias mirror MT–MB2's ΔiTB2 offsets i3A, except gain gmAGDRD2 divides it.

2 2 2 2 2 2
⎛ Δi ⎞ ⎛ Δi ⎞ ⎡ Δi3A ⎤ ⎡ Δi TBA ⎤ ⎛ Δi ⎞ ⎛ Δi ⎞
VOS = ⎜ 12 ⎟ + ⎜ 34 ⎟ + ⎢
*
⎥ +⎢ ⎥ ≈ ⎜ 12 ⎟ + ⎜ 34 ⎟
⎝ g m1 ⎠ ⎝ g m1 ⎠ ⎢⎣ g mAg m1 ( rds2 ||rds4 ) ⎥⎦ ⎢⎣ g mAg m1 ( rds2 ||rds4 ) ⎥⎦ ⎝ g m1 ⎠ ⎝ g m1 ⎠

Electronic Noise vN*: Gain gmAGDRD2 suppresses iAB2* ∴ i1234* and gm12 set noise vN*.

2 2 2 2 2 2
⎛i *⎞ ⎛i *⎞ ⎡ iA
* ⎤ ⎡ i BA
* ⎤ ⎛i*⎞ ⎛i*⎞
vN = 2⎜ 12 ⎟ + 2⎜ 34 ⎟ + ⎢ 2 2
* 1 3
+
⎥ ⎢ ⎥ ≈ ⎜ ⎟ + ⎜ ⎟
⎝ g m1 ⎠ ⎝ g m1 ⎠ ⎢⎣ g mAg m1 ( rds2 ||rds4 ) ⎥⎦ ⎢⎣ g mAg m1 ( rds2 ||rds4 ) ⎥⎦ ⎝ g m1 ⎠ ⎝ g m1 ⎠

D. Small-Signal Response
Small-Signal Parameters: AV0 = gm1(rds2 || rds4)gmARO
RO = rdsA || rdsB2 RID à ∞
pGA = pMiller ≈ 1/2π(rds2 || rds4)(gmAROCC)
f0dB ≈ GBW = AV0pGA = gm1/2πCC
CC shorts after pGA ∴ ZO à 1/gmA and
pO ≈ gmA/2π(CL + CPAR)
pG3 = pMirror ≈ gm3/2π(2CGS3 + CGD4 + CGD1)
zD4 = zMirror = 2pG3
zRHP = zC ≈ gmA/2πCC

Example: gm13 = 100 µS, CG3 = 200 fF, gmA = 1 mS, rds24 = 2 MΩ, rdsAB2 = 0.5 MΩ,
CC = 5 pF, and CL + CPAR = 10 pF ∴ RID à ∞, RO = 250 kΩ,
AV0 = 25 kV/V, pGA = 127 Hz, f0dB = 3.18 MHz, pO = 16 MHz, zRHP = 32 MHz,
pG3 = 80 MHz, and zD4 = 160 MHz ∴ pGA << f0dB < pO < zRHP < pG3, zD4.

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E. Power-Supply Rejection: i. Model and ii. Miller Effect PSRR Model

Model what connects to vO à MA, MB2, CC, and CL.
IBIAS's ZO should be high ∴ MB2's igmB2 can be negligible.
P-type mirror reproduces vdd and cancels vss
at MA's gate ∴ vsgA ≈ 0 à igmA ≈ 0.
CC diode-connects MA to vDD.
∴ MA's rdsA || ZgmA falls after ZgmA = rdsA.
Slightly below
1 Miller pole pMiller.
R O1 +
vo vo sCC 1
Z gmA = = = ≈ ≡ rdsA
igmA ⎛ v o R O1g mA ⎞ g mA R O1 g mA R O1sCC fM ≈
1
<p Miller
⎜ ⎟ 2πR O1g mA rdsACC
⎝ R O1 + Z C ⎠ 1
sCC
>>R O1

Where vGA's RO1 ≈ rds2 || rds4.

rdsA || ZgmA stops falling past fM after ZgmA flattens at 1/gmA.

à When 1/sCC ≤ RO1, past fgmA ≈ 1/2πRO1CC ≈ fMgmArdsA >> fM.

iii. Positive Supply Gain

At low frequencies, rdsA || ZgmA ≈ rdsA ∴ rdsA and rdsB2 voltage-divide vdd.

Past fM, rdsA || ZgmA falls ∴ MA couples more vdd to vo and AVDD rises à Zero.

As rdsA || ZgmA drops below rdsB2, AVDD flattens to rdsB2/rdsB2 or 1 à Pole.

r +r
à From fM, AVDD climbs rdsA + rdsB2 ∴ Frequency rises dsA dsB2 .
rdsB2 rdsB2
∴ ⎛r +r ⎞ ⎛ ⎞⎛ rdsA + rdsB2 ⎞
1
f = fM ⎜ dsA dsB2 ⎟ ≈ ⎜ ⎜ ⎟ ≈ p Miller
r
⎝ dsB2 ⎠ ⎝ 2πR O1 mA C ⎠ ⎝ rdsA rdsB2 ⎠
g C

CL then shunts what 1/gmA couples of vdd to vo past pO.

⎛ rdsB2 ⎞⎛ s ⎞
⎜ ⎜1+ ⎟
rdsB2 || Z CO ⎝ r + r ⎠⎝ 2πfM ⎠
A VDD = ≈ dsA dsB2
(rdsA || Z gmA ) + (rdsB2 || Z CO ) ⎛⎜1+ s ⎞⎛⎜1+ s ⎞⎟
⎝ 2πp Miller ⎠⎝ 2πp O ⎠

AVDD ≈ 1 after pMiller and before pO.

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 Analog IC Design

Positive PSRR

A V0 ⎛r +r ⎞
PSRR 0 =
+
= g m1 ( rds2 || rds4 ) g mA ( rdsA || rdsB2 ) ⎜ dsA dsB2 ⎟ = g m1 ( rds2 || rds4 ) g mA rdsA
A VDD0 ⎝ rdsB2 ⎠

If rdsA ≈ rdsB2 ∴ PSRR0+ ≈ 2AV0.

pMiller and pO appear in both AV and AVDD ∴ They cancel in PSRR+:

AV PSRR 0 g ( r || r ) g r
+
PSRR + = ≈ = m1 ds2 ds4 mA dsA
A VDD ⎛ s ⎞ ⎛ s ⎞
⎜1+ ⎟ ⎜1+ ⎟
⎝ 2πfM ⎠ ⎝ 2πfM ⎠

PSRR 0
+
g ( r || r ) g r
PSRR + g ≈ = m1 ds2 ds4 mA dsA ≈ 1
f0dB ≈ m1 >>fM ⎛ 2πf0dB ⎞ ⎛ g m1 ⎞
⎟ R O1g mA rdsA CC
2πCC
⎜ ⎟ ⎜
⎝ 2πfM ⎠ ⎝ CC ⎠

∴ PSRR0+ ≈ 1 at f0dB à No rejection.

iv. Negative Supply Gain

At low frequencies, rdsA || ZgmA ≈ rdsA ∴ rdsA and rdsB2 voltage-divide vdd.

As ZgmA drops below rdsA || rdsB2, AVSS falls ∴ MA shunts more vss to vDD à pMiller pole.

Past fgmA = fMgmArdsA, rdsA || ZgmA stops falling at 1/gmA ∴ AVSS flattens à Zero.

CL then shunts rdsB2's injection of vss across 1/gmA in vo past pO.

⎛ rdsA ⎞⎛ s ⎞
⎜ ⎜⎜1+ ⎟⎟
rdsA || Z gmA || Z CO ⎝ rdsB2 + rdsA ⎠⎝ 2πfgmA ⎠
A VSS = ≈
rdsB2 + ( rdsA || Z gmA || Z CO ) ⎛ s ⎞⎛ s ⎞
⎜1+ ⎜1+ ⎟
⎝ 2πp Miller ⎠⎝ 2πp O ⎠

1/g mA
A VSS ≈ after fgmA and before pO.
rdsB2

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Negative PSRR
A V0 ⎛r +r ⎞
PSRR 0 = = g m1 ( rds2 || rds4 ) g mA ( rdsA || rdsB2 ) ⎜ dsA dsB2 ⎟ = g m1 ( rds2 || rds4 ) g mA rdsB2
−

A VSS0 ⎝ rdsA ⎠

If rdsA ≈ rdsB2 ∴ PSRR0– ≈ 2AV0.

pMiller and pO appear in both AV and AVSS ∴ They disappear in PSRR–:

AV PSRR 0 g ( r || r ) g r
−
PSRR − = ≈ = m1 ds2 ds4 mA ds5
A VSS ⎛ s ⎞ ⎛ s ⎞
⎜⎜1+ ⎟⎟ ⎜⎜1+ ⎟⎟
⎝ 2πfgmA ⎠ ⎝ 2πfgmA ⎠

PSRR 0
−
g ( r || r ) g r
PSRR − g m1 ≈ = m1 ds2 ds4 mA dsB2 ≈ g mA rdsB2
f0dB ≈ >>fgmA ⎛ 2πf ⎞ ⎛ g m1 ⎞
⎟ R O1CC
2πCC 0dB
⎜⎜ ⎟⎟ ⎜
⎝ 2πfgmA ⎠ ⎝ CC ⎠

∴ PSRR0– ≈ gmArdsB2 at f0dB à Considerable rejection.

v. Summary

P-type mirror reproduces vdd and cancels vss in MA's vGA.

MA cancels vdd in vGA with vdd in vSA.

IBIAS's ZO suppresses vdd and vss in igmB2.

CL shunts both input and supply

signals ∴ No effects in PSRR.

CC diode-connects MA.

∴ rdsA || ZgmA falls to 1/gmA.

à CC couples vdd and shunts vss ∴ PSRR+ << PSRR–.

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F. Nulling Zero
Challenge: zRHP ≈ gmA/2πCC may not be sufficiently high.

Fix: Limit CC's iFF, transform zRHP into an in-phase zero zM, and

use zLHP to recover pO's phase with current-limiting resistor RM.

Design: zM ≈ 1/2π(RM – 1/gmA)CC ≡ pO ≈ gmA/2πCL: 1 ⎛ C L + CC ⎞

RM = ⎜
g mA ⎝ CC ⎠

But: CC and CL short past pO.

∴ RM shunts rds2 || rds4.

CGA shorts RM at pNULL.

pNULL = pGA' ≈ 1/2πRMCGA.

p NULL 2π (1/g m1 ) CC
= >> 1
f0dB 2πR M CGA

Since gmA >> gm1 and CGA << CC, RM's KC/gmA is low and pNULL >> f0dB.

CMOS Implementation
When moderate-resistance, low voltage-coefficient, and low temperature-drift

(analog) resistors are not available, channel resistance RCHANNEL is useful:

à MR's IDR = 0 ∴ VSDR = 0 and MR is biased in triode as RCHANNEL.

Derive required vSGR from desired RCHANNEL = ∂vSD/∂iD TRIODE ≈ 1/KP'SR(vSGR – |vTP|).

Design desired vSGR with MB3 and MB4's vSGB3 + vSGB4 = vSGR + vSGA.

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 Analog IC Design

G. Design Variables
Low-Frequency Gain AV0:
gm1,A and rds2,4,A,B2.
Unity-Gain Frequency f0dB:
gm1 and CC.
Phase Margin PM:
f0dB, pO, and zM.
à gm1,A, CC, CL, and RM.
Input Common-Mode Range ICMR:
VDST,1,3(SAT). Power Dissipation PQ:
Slew Rate SR: vDD – vSS and IQuiescent = IBIAS + IT + IB2.
IT and CC. Offset VOS: Low if vSG3 ≈ vSGA and transistors match.
Output Swing ΔvO(MAX): M1 to M2 and M3 to M4: Critical for i1 ≈ i2.
VDSA,B2(SAT). M3 to MA and MT to MB2: Good for vD13 ≈ vD24.

H. Design Example
Specifications: vDD = –vSS = 2.5 V –1 ≥ vIC ≥ 1.8 V –2 ≥ vO ≥ 2 V
PQ ≤ 1 mW –80 ≥ iO ≥ 80 µA CL ≤ 10 pF SR ≥ 10 V/µs

AV0 > 3 kV/V f0dB ≥ 5 MHz PM ≥ 60° IBIAS = 6 µA

Process: L ≥ 0.6 µm, LOL = 100 nm, COX'' = 2.4 fF/µm2, KN' = 115 µA/V2,

KP' = 40 µA/V2, |VTP0| = 0.9 V, VTN0 = 0.65 V, and 1/λL = 30 V for L = 3 µm.

Sample Design:
1. Differential pair from ICMR and supplies.

Headroom to vDD = vDD – vIC(MAX) = 2.5 – 1.8 = 0.7 V.

Headroom to vSS = vIC(MIN) – vSS = (–1) – (–2.5) = 1.5 V.

à Negative Margin > Positive Margin.

∴ Accommodate tail current with an N-type pair

and if possible, connect bulk to source à No bulk effect on vTN.

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2. gm12 and CC from f0dB ≈ gm12/2πCC ≥ 5 MHz. Designed:

CC ≡ 5 pF ∴ gm12 ≥ 157 µS. CC ≡ 5 pF

3. IT from CC and SR = IT/CC ≥ 10 V/µs. IT ≡ 60 µA

∴ IT ≥ 50 µA à 60 µA. S12 ≡ 10

4. S12 from IT and gm12 = √[2(0.5IT)KN'S12] ≥ 157 µS. ST ≡ 10

∴ S12 ≥ 3.6 à 10. S34 ≡ 15

5. ST from IT and vIC(MIN) = vSS + VDST(SAT) + VTN0 + VDS12(SAT) ≤ –1 V.

Where VDS12(SAT) = √[2(0.5IT)/KN'S12] ≈ 228 mV.

∴ VDST(SAT) ≤ 0.62 V à ST ≥ 2IT/[KN'VDST(SAT)2] = 2.7 à 10.

6. S34 from IT and vIC(MAX) = vDD – |VTP0| – VSD34(SAT) + VTN0 ≥ 1.8 V.

∴ VSD34(SAT) ≤ 0.45 V à S34 ≥ 2(0.5IT)/[KP'VSD3(SAT)2] = 7.4 à 15.

7. IB2 from iO(MAX)– = IB2 ≥ 80 µA à 90 µA. Designed:

à MB2 mirrors MT ∴ IB2/IT = SB2/ST à SB2 = 15. CC ≡ 5 pF

8. Check vO(MIN) = vSS + VDSB2(SAT) ≈ –2.18 V ≤ –2 V. IT ≡ 60 µA

à VDSB2(SAT) = √[2IB2/KN'SB2] ≈ 320 mV. S12 ≡ 10

9. SA from S3 and IB2 à VSDA(SAT) ≡ VSD3(SAT). ST ≡ 10

∴ VSD3(SAT) = √[2(0.5IT)/KP'S3] ≡ VSDA(SAT) = √[2IB2/KP'SA]. S34 ≡ 15

à (0.5IT)/S3 ≡ IB2/SA à SA ≡ 3S3 = 45. IB2 ≡ 90 µA

10. Check pO ≈ gmA/2πCL ≈ 10 MHz ≥ f0dB = 5 MHz. SB2 ≡ 15

11. For reasonable gain (i.e., low λ effects) and matching, SA ≡ 45

all L's can be 5LMIN = 3 µm. L's ≡ 3 µm

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 Analog IC Design

12. RM from PM = 180° – Tan–1(f0dB/pMiller) – Tan–1(f0dB/pO) + Tan–1(f0dB/zM) ≥ 60°.

à f0dB ≈ gm1/2π(CC + WALOLCOX") ≈ 8 MHz.

à pMiller ≈ 1/2π(rds2 || rds4)[gmA(rdsA || rdsB2)(CC + WALOLCOX") ≈ 670 Hz.

à pO ≈ gmA/2πCL ≈ 9 MHz.

∴ Tan–1(f0dB/zM) ≥ 12° à In-phase zero at zM ≤ 38 MHz.

And since zM = 1/2π(RM – 1/gmA)CC, Designed: IB2 ≡ 90 µA

RM ≥ 2.6 kΩ à 3 kΩ. CC ≡ 5 pF SA ≡ 45

13. SB from IBIAS, IT, and ST. IT ≡ 60 µA SB2 ≡ 15

à MT mirrors MB. S12 ≡ 10 L's ≡ 3 µm

∴ IT/IBIAS = ST/SB ST ≡ 10 RM ≡ 3 kΩ

à SB = ST(IBIAS/IT) = 1. S34 ≡ 15 SB ≡ 1

14. Check f0dB ≈ gm12/2π(CC + WALOLCOX") ≈ 8 MHz > 5 MHz. Designed:

15. Check AV0 = gm12(rds2 || rds4)gmA(rdsA || rdsB2) IT ≡ 60 µA

S12 ≡ 10
≈ (263µ)(0.5M)(569µ)(167k)
ST ≡ 10
≈ 12.5 kV/V = 82 dB > 3 kV/V.
S34 ≡ 15
16. Check vO(MAX) = vDD – VSDA(SAT)
IB2 ≡ 90 µA
= 2.5 – 0.32 = 2.18 V > 2 V.
SA ≡ 45
17. Check pMirror ≈ gm3/2πCG3.
SB2 ≡ 15
à CG3 ≈ COX"{2W34[(2/3)L3 + LOL] + (W4 + W1)LOL} = 465 fF. L's ≡ 3 µm

∴ pMirror ≈ 65 MHz >> f0dB = 8 MHz. RM ≡ 3 kΩ

18. Check PQ = (IBIAS + IT + IB2)(VDD – VSS) = 780 µW < 1 mW. SB ≡ 1

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 Analog IC Design

19. Check pNULL ≈ 1/2πRMCGA. Designed:

à CGA ≈ COX"{WA[(2/3)LA + LOL] + (W4 + W2)LOL} = 698 fF. IT ≡ 60 µA

∴ pNULL ≈ 76 MHz ≈ 10f0dB = 80 MHz. S12 ≡ 10

20. Check iO(MAX)+ = iA(MAX) – IB2. ST ≡ 10

à iA(MAX) ≈ 0.5KP'SA(vDD – vGA(MIN) – |VTP0|)2. S34 ≡ 15

à Worst case of vGA(MIN) is at vIC(MAX). IB2 ≡ 90 µA

vGA(MIN) = vIC(MAX) – vGS2 + VDS2(SAT) SA ≡ 45

= vIC(MAX) – VTN0 = 1.8 – 0.65 = 1.15 V. SB2 ≡ 15

∴ iA(MAX) ≈ 182 µA and iO(MAX)+ ≈ 92 µA > 80 µA. L's ≡ 3 µm

21. Check other specifications, and if necessary, RM ≡ 3 kΩ

revisit design steps and choices. SB ≡ 1

6.5. Class-AB Amplifiers: A. One-Stage Transconductor

Differential Input: Differential Currents:
M1–M2 processes vP – vN. M3–M5 and M6–MAB1 mirror i1.
M4–MAB2 mirrors i2.
Class-AB Output:
MAB1 and MAB2 combine i1 and i2.
Bias:
Reference circuit generates IBIAS.
MB–MT mirrors IBIAS.
Input and feedback
set VP, VN, and VO.

Feature: pO is dominant and all other poles IT splits between M1 and M2.

are at gm/CPAR ∴ No CC and fast. M3–M5, M6–MAB1, and M4–MAB2

Tradeoff: Lower AV0 and higher VOS and vN*. mirror M12's bias currents.

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 Analog IC Design

i. Static Parameters
Bias Currents (where Si ≡ Wi/Li):
IT = IBIAS(ST/SB)
With negative Feedback, VN ≈ VP
∴ I13 ≈ I24 ≈ 0.5IT.
IAB1 ≡ IAB2 à Design must ensure:
(S5/S3)(SAB1/S6) ≡ (SAB2/S4).
∴ IAB12 = I12(SAB2/S4) = (0.5IT)(SAB2/S4)
Limits:
vIC(MAX) = vDD – vSG3 – VDS1(SAT) + vGS1 vO(MIN) = vSS + VDSAB1(SAT)
= vDD – |vTP| – VSD3(SAT) + vTN iO(MAX)– = iAB1(MAX) = IT(S5/S3)(SAB1/S6)
vIC(MIN) = vSS + VDST(SAT) + vGS1 iO(MAX)+ = iAB2(MAX) = IT(SAB2/S4) ≡ iO–(MAX)
= vSS + VDST(SAT) + vTN + VDS1(SAT) iAB1 = 0 at iAB2(MAX), iAB2 = 0 at iAB1(MAX),
vO(MAX) = vDD – VSDAB2(SAT) iAB1 = iAB2 > 0 when vO = 0 ∴ Class AB.

ii. Small-Signal Response AV0 = gm1(SAB2/S4)RO

RO = rdsAB1 || rdsAB2 RID à ∞
pO ≈ 1/2πRO(CL + CPAR)
f0dB ≈ GBW = AV0pO
= gm1(SAB2/S4)/2π(CL + CPAR)
pG3 and pG4 each affect half of AV.
∴ They produce the effect of one pole.
pG3 = gm3/2πCG3, pG4 = gm4/2πCG4
pG6 = gm6/2πCG6, zAB1 = zMirror ≈ 2pG6

Example: If gm12AB12 = 200 µS, gm3456 = 100 µS, CGS12AB12 = 200 fF,
CGS3456 = 100 fF, rdsAB12 = 2 MΩ, and CL = 10 pF.
Results: RID à ∞, RO = 1 MΩ, AV0 = 400 V/V, pO ≈ 16 KHz, f0dB ≈ 6.4 MHz,
pG4 = pG6 ≈ 53 MHz, pG3 ≈ 80 MHz ∴ pO << f0dB << pG4, pG6 < pG3.

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 Analog IC Design

iii. Other Parameters

⎛ S ⎞⎛ 1 ⎞
Slew Rate: iAB1(MAX) and iAB2(MAX) slew CL + CPAR ∴ SR ± = I T ⎜ AB2 ⎜ .
⎝ S4 ⎠⎝ C L + C PAR ⎠
Systemic Offset: vDS mismatch across all mirrors contribute à High.

à VOS(S) must counter the effects of all mismatches:

Δv DS6AB1 Δv SD4AB2 ( Δv SD35 /rds5 ) Δv DS6AB1 − Δv SD4AB2 Δv SD35

VOS(S) = − + = +
AV AV ( 5 3 ) m1 m1 ( AB2 4 ) ( dsAB1 dsAB2 ) ds5 (S5 /S3 ) gm1
S /S g g S /S r || r r

Random Offset: Mismatches in the differential pair and all mirrors contribute à High.

2 2 2 2 2
⎛ Δi ⎞ ⎛ Δi ⎞ ⎡ Δi35 ⎤ ⎡ Δi 6AB1 ⎤ ⎡ Δi ⎤
VOS
*
= ⎜ 12 ⎟ + ⎜ 34 ⎟ + ⎢ ⎥ +⎢ ⎥ +⎢ 4AB2
⎥
g g ⎢ S /S g ⎥ ⎢ S /S S /S g ⎥ ⎢ S /S g
⎝ m1 ⎠ ⎝ m1 ⎠ ⎣ ( 5 3 ) m1 ⎦ ⎣ ( AB1 5 )( 5 3 ) m1 ⎦ ⎣ ( AB2 4 ) m1 ⎥⎦

Electronic Noise: Differential pair and all mirrors inject noise à Noisy.
2 2 2 2 2 2
⎛i *⎞ ⎛i *⎞ ⎛ i * S ⎞ ⎛ i * S ⎞ ⎛i * S ⎞ ⎛i * S ⎞
v N = 2 ⎜ 12 ⎟ + 2 ⎜ 34 ⎟ + ⎜ 5 ⋅ 3 ⎟ + ⎜ 6 ⋅ 3 ⎟ + ⎜ AB1 ⋅ 4 ⎟ + ⎜ AB2 ⋅ 4 ⎟
*

⎝ g m1 ⎠ ⎝ g m1 ⎠ ⎝ g m1 S5 ⎠ ⎝ g m1 S5 ⎠ ⎝ g m1 SAB2 ⎠ ⎝ g m1 SAB2 ⎠

iv. Supply Rejection and v. Cascodes

Supply impedances to mirror M6–MAB1 balance when vO is unloaded.

∴ N-type mirror: Cancels vdd à AVDD ≈ 0 and PSRR+ approaches ∞.

Reproduces vss à AVSS ≈ 1 and PSRR– ≈ AV.

Design Notes:

Cascoding mirrors can

Reduce VOS(S) and

Raise AV0, but also

Reduce ΔvO(MAX).

RLOAD and CLOAD to ground

Shunt signal and noise in vO.

∴ AV and AVSS fall.

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 Analog IC Design

B. Two-Stage Hybrid
AB CS input amplifies and AB follower/transconductor drives the load.
MOB shuts when MOT drives iOT(MAX) ∴ iO(MAX)+ = iOT(MAX) ≠ f(IT).
MOB mirrors IT when MOT is off à iO(MAX)– = iOB(MAX) = IT(SOB/S6)(S5/S3).
iOT = iOB = 0.5IT(SOB/S6)(S5/S3) > 0 when vO = 0. Distortion:
∴ Class AB à Little cross-over distortion. MOT's AV ≠ MOB's AV.
∴ AV(PK)+ ≠ AV(PK)–.
à Gain distortion.
Power-Supply Rejection:
Gain stage cancels vdd
and reproduces vss.
MOT reproduces vss
and shunts rdsOT's
and MOB's injection.

C. Two-Stage Folded-Cascode Follower

Stacked gate–gate battery vSGO1 + vGSO2 biases MAB1 and MAB2:
Sets MAB1's and MAB2's no-load current.
Shuts MAB1 and MAB2 when supplying iO(MAX)+ or pulling iO(MAX)–.

PSR: Gain stage cancels vdd and reproduces vss and followers reproduce vss.

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 Analog IC Design

D. Two-Stage Transconductor
MBOT and MBOB bias MOT and MOB:

When MOB pulls iO(MAX)–, MBOB shuts and MBOT cascodes MAB2 and biases MOT.

When MOT supplies iO(MAX)+, MBOT shuts and MBOB cascodes MAB1 and biases MOB.

CCT and CCB split poles and RM impedes out-of-phase feed-forward currents.

i. When Sinking Power

M5C balances mirror M6–MAB1 when MOB sinks the load.

∴ N-type mirror M6–MAB1 cancels vdd and reproduces vss in vGOB.

igmOB excludes vdd and MOB cancels vss à Low supply gain.

Without M5C, RDBOT magnifies igAB1's vdd and vss noise à Higher supply gain.

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Example when MNO dominates:

vss appears in vGOB à Feed-through to vGOB ≈ 0 dB.
∴ MOB rejects vGOB's vss and rdsOB–rdsOT voltage-divides vss à AVSS0 ≈ –7 dB.
vdd is nearly absent in vGOB à Feed-through to vGOB ≈ –55 dB.
∴ MOB excludes vdd and rdsOB–rdsOT voltage-divides vdd à AVDD0 ≈ –10 dB.

PSRR0 ≈ AV0's 78 dB – AVDD0/VSS0's –7 to –10 dB = 85–88 dB.

Balanced mirror favors MOB ∴ PSRR is high when iO < 0.

ii. When Supplying Power

When MOT supplies the load: M5C current-buffers i5 and MBOB current-buffers iAB1.

à M5 and MAB2 tend to balance mirror M6–MAB1.

∴ N-type mirror M6–MAB1 tends to cancel vdd and reproduce vss in vGOT.

MOT amplifies vSOT's vdd and vGOT's vss à High supply gain.
M5C–MBOB cascode M5–MAB1 to diminish igmAB1's vdd and vss and rdsAB1's vss.

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Example when MOT dominates:

Some vdd appears in vGOT à Feed-through to vGOT ≈ –7 dB.

Some vss is absent in vGOT à Feed-through to vGOT ≈ –25 dB.

∴ MOT amplifies imperfections à AVDD/VSS0 ≈ 11–30 dB.

PSRR0 ≈ AV0's 91 dB – AVDD0/VSS0's 11–30 dB = 61–80 dB.

iii. Combined Response

When iO is 0 mA, MOB and MOT both conduct in Class-AB fashion.

∴ MOB–MOT dominance determines feed-through and supply gain.

vss mostly in vGOB and vdd in vGOT à Feed-through ≈ 0 to –4 dB.

vdd is mostly absent in vGOB and some vss in vGOT à Feed-through < –14 dB.

PSRR0 ≈ AV0's 87 dB – AVDD0/VSS0's 6–25 dB = 62–81 dB.

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6.6. Current-Mode Amplifiers

Motivation for processing currents:

Low-resistance nodes ∴ High-frequency poles.

Low-voltage swings ∴ Lower large-signal slew-rate delays.

∴ Lower charge/discharge energy for capacitors.

∴ More headroom to supplies à Higher dynamic range.

Ideal Characteristics:
Current Amplifier
AI à ∞.
RINP
RINP, RINN à Should shunt iIN à 0 Ω.
RO à Should impede iO à ∞.
RO Ideal Source and Load:
RINN
RS à Should impede iIN à ∞.
iO = (iP – iN)AI
RL à Should shunt iO à 0 Ω.

A. Current-Mode Concept
Conceptual Development:

High accuracy with negative feedback.

Highest bandwidth fI 0dB when βFB does not attenuate AI LG.

∴ Use current amplifier in unity-gain feedback.

Translate vIN to iIN with RIN.

A load RL steals current away from iFB.

à iFB ≠ iO with RL.

∴ Should not load the circuit à Buffer the output.

iO ⎛ i IN ⎞⎛ iO ⎞ ⎛ 1 ⎞ ⎛ 1 ⎞⎛ A I ⎞
AG ≡ =⎜ ⎜ ⎟=⎜ ⎟ A I(CL) = ⎜ ⎟⎜
v IN ⎝ v IN ⎠⎝ i IN ⎠ ⎝ R IN ⎠ ⎝ R IN ⎠⎝ 1+ A I ⎠

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For a voltage gain:

Translate iO to vOI with ROI.

Buffer vOI with high-ZIN AV so iFB = AI's iO.

∴ Since ROI does not affect iFB, AI remains in unity gain across ROI values.

v O " i IN %" i O %" v OI %" v O % " 1 % " A A %" R %

A V.IO ≡ = $$ ''$$ ''$$ ''$$ '' = $$
v IN # v IN &# i IN &# i O &# v OI & # R IN &
( )
'' A I(CL) −R OI A V = − $$ I V ''$$ OI ''
# 1+ A I &# R IN &

Frequency Response:

AI(CL) sets vO/vIN's bandwidth fV BW to fI 0dB.

ROI/RIN sets vO/vIN's gain, but not fV BW.

∴ fV BW = fI 0dB ≠ f(Gain).

à No fall in fV BW for higher gain.

B. Example: i. Operation
RIN translates vin to iin.

M1–M2 amplifies iin – ifb.

ROI translates io to vg8.

M8 buffers and reproduces vg8.

M34567 bias M1–M2 and M8.

⎡ ⎤
⎢ ⎥
v in ⎛ i ⎞ ⎛ i ⎞ ⎛ v ⎞ ⎛ v ⎞ ⎛ 1 ⎞ ⎛ S /S ⎞ g m8 ( rds7 || R L )
= ⎜ in ⎜ o ⎜ g8 ⎟⎜⎜ o ⎟⎟ ≈ ⎜ ⎜ 2 1 ⎟ (−R OI )⎢⎢ ⎥
v o ⎝ v in ⎠⎝ i in ⎠⎝ io ⎠⎝ v g8 ⎠ ⎝ R IN ⎠⎝ 1+ S2 /S1 ⎠ ⎛ 1 ⎞ ⎥
⎢1+ ⎜ g m8 + ⎟ ( rds7 || R L ) ⎥
⎣ ⎝ r ds8 ⎠ ⎦
Design Notes:
M2's rds2 and M4's rds4 steal current from ROI ∴ Reduce ROI, lengthen M2's L2
and M4's L4, degenerate M2 and M4, and/or cascode M2 and M4.
1/gm1 adds load to vIN ∴ Raise RIN and/or gm1 (i.e., I34 and/or W12).

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ii. Small-Signal Response AI OL ≡ io/ie = S2/S1

βFB ≡ ifb/io ≈ 1 if ROI << rds2 || rds4

AI CL ≡ io/iin = AI OL/(1 + AI OL)

AV IO = vo/vin ≈ (1/RIN)AI CL(–ROI)

if iin ≈ vin/RIN ∴ RIN >> 1/gm1.

fV BW = fI 0dB ≈ GBWI = AI OLpG8

≈ (S2/S1)/2πROICG8
fV 0dB ≈ GBW = AV IOfV BW
For iR1 ≈ vin/R1, RIN >> 1/gm1.
pG1 ≈ gm1/2π(CGS1 + CGS2)
For ifb ≈ io, ROI << rds2 || rds4.
∴ Limited gain ROI/RIN. pO ≈ gm8/2π(CGS8 + CL)

Raising RD2 and RD4 relaxes ROI's limit. zGS8 ≈ gm8/2πCGS8 à In phase.

If RIN = 10 kΩ, ROI = 200 kΩ, S1 = S2, CG8 = 250 fF ∴ AV IO = –10 and fV 0dB = 32 MHz.

C. Design Notes on High-Speed Amplifiers

gm/CPAR limits bandwidth:
gm I K '(W/L) I C "(W/L) I t
∝ D ∝ D OX ∝ D OX3
C PAR COX"WL COX"WL WL
Higher currents raise gm/CPAR (i.e., gain and bandwidth), but also power.
Shorter channel lengths raise gm/CPAR more than shorter tOX lowers gm/CPAR.
∴ Finer-pitch technologies reach higher bandwidths.
Each stage introduces at least one bandwidth-limiting pole.
Because BJTs are exponential and FETs are square law,
BJT gm's are normally higher than MOS gm's.
1Compensating a negative-feedback loop reduces bandwidth.
∴ Avoid negative feedback if possible and unnecessary.
Since: 2Low resistances raise bandwidth and lower gain.
And: 3Poles near f0dB in an open-loop system (with no feedback) are harmless.
∴ Implement 1open-loop system with 3several 2low-gain, high-bandwidth stages.

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Chapter 7. Comparators

Outline
7.1. Generalities

7.2. Open-Loop Comparators

7.3. Summing Comparators

7.4. Hysteretic Comparators

7.5. Regenerative Comparators

7.6. High-Speed Comparators

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7.1. Generalities: A. Operation

A comparator is a one-bit analog–digital (A/D) converter.
à Compares analog inputs and outputs a "high" only if vP > vN.

Desirable Static Parameters:

High output swing ΔvO = VOH – VOL.
High input common-mode range ICMR.
Good resolution à Low ΔvID(MIN) = ΔvO/AV0 ≡ VIH – VIL.
∴ High gain AV0. Desirable Dynamic Parameters:
Low input-referred offset VOS. Short propagation delay tP.
Low input-referred noise. High slew rate SR.
High input resistance RIN… …

B. Dynamic Response Step Response

Propagation Delay:

From vID's VID(MID) = 0.5(VIL + VIH).

To vO's VO(MID) = 0.5(VOL + VOH).

t P(RISE) + t P(FALL)
( )
t P ≡ Avg t P(RISE) , t P(FALL) =
2

Bandwidth-Limited Response:

Linear single-pole system produces an exponential response.

A V0 ) # −t &,
AV = à v O = v ID A V0 +1− exp % (.
s $ τ1 '-
1+ *
2πp1

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Step Response: When vID undergoes an instant step transition.

* $ −t '-
Δv O = Δv ID A V0 ,1− exp && ))/ à tP ≡ t when ΔvO ≡ 0.5ΔvO(FINAL) ≡ 0.5(VOH – VOL).
,+ % τ1 (/.

Minimum drive ΔvID(MIN) ≡ (VOH – VOL)/AV0. ∴ ΔvID ≡ KOΔvID(MIN)

# 2K &
Input-overdrive factor KO ≡ ΔvID/ΔvID(MIN). t P = τ1 ln %% O
((
$ 2K O −1 '

With a linear circuit, response tP is a negative exponential ∴ Fast at first, then slow.

Slew-Rate Limited Response:

dv O i O(MAX) ⎛ C ⎞ Δv 0.5 ( VOH − VOL )
SR = = ∴ t P(SR) = Δt C = ⎜⎜ L ⎟⎟ Δv O = O =
dt CL ⎝ iO(MAX) ⎠ SR SR

Example
Parameters: pBW = 1.6 kHz, AV0 = 1 kV/V, SR = 1 V/µs,

VOH = 1.5 V, VOL = 0.5 V, and ΔvID = 10 mV.

Solution: ΔvID(MIN) = (VOH – VOL)/AV0 = 1 mV

KO = ΔvID/ΔvID(MIN) = 10

tP(BW) = (1/2πpBW) ln [2KO/(2KO – 1)] = 5.1 µs

tP(SR) = 0.5(VOH – VOL)/SR = 0.5 µs

∴ tP ≈ tP(BW) + tP(SR) = 5.6 µs

Consider both bandwidth and slew rate.

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C. Noise
Noise in vID produces uncertainty in transition and jitter at the output.
Comparator vin
threshold

vout
VOH
Noise
Jitter
VOL

Incorporating sufficient hysteresis in the comparator removes noise jitter.

ΔvHYS > vN*
vin
VTRP+
VTRP-

vout
VOH

VOL No Jitter
VTRIP+ ≡ VTH(RISE) > VTRIP– ≡ VTH(FALL)

7.2. Open-Loop Comparators: A. Class-A Transconductor

VOH = vDD because iA is 0.

VOL = vSS + vDSA(TRIODE)

vDSA(TRIODE) = IBRDSA(ON)

Performance Parameters: RDSA(ON) is channel resistance:

2I B v DS 1
VTRIP = VGSA(IQ ) + v SS = VTN0 + + v SS R DSA(ON) = ≈
K N'(W/L)A iD K N'(W/L)A v GSTA

SR+ = IB = IBIAS(SB/S1)/CL Where vGSTA ≡ vGSA – vTN

SR– = (iA – IB)/CL AV0 ≈ gm1(rdsA || rdsB)

= [0.5KN'(W/L)AvGSTA2 – IB]/CL pO ≈ 1/2π(rdsB || rdsB)CL

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B. Class-AB Transconductor Performance Parameters:

VOH = vDD because iAB1 = 0.

VOL = vSS because iAB2 = 0.

ICMR is same as in op amp.

AV0 ≈ gm1(SAB2/S4)(rdsAB1 || rdsAB2)

pO ≈ 1/2π(rdsAB1 || rdsAB2)CL

SR+ ≈ IT(SAB2/S4)/CL

SR– ≈ IT(S5/S3)(SAB1/S6)/CL

Low gain (one gain stage), limited SR (by IT), symmetrical SR (MAB12 push–pull),

high-swing (rail-to-rail to vDD and vSS), one low-frequency pole (at vO), and

poor offset and poor noise (from several transistors in first stage).

C. Two-Stage Class-A Transconductor

Op amp without compensation because circuit is not used in negative feedback.

Performance Parameters:

VOH = vDD – vSDA(TRIODE)

vSDA(TRIODE) = IB2RSDA(ON)
v SD 1
R SDA(ON) = ≈
iD K P'(W/L)A v SGTA(MAX)
vIC limits vSGTA(MAX).

VOL = vSS because iA is 0.

ICMR is same as in two-stage op amp. AV0 ≈ gm1(rds2 || rds4)gmA(rdsA || rdsB2)

SR– = IB2/CL = IBIAS(SB2/SB)/CL pO ≈ 1/2π(rdsA || rdsB2)CL

SR+ = (iA(MAX) – IB2)/CL CL shunts CGDA's Miller gain.

= [0.5KP'(W/L)AvSGTA(MAX)2 – I5]/CL ∴ pGA ≈ 1/2π(rds2 || rds4)CGSA.

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Step Response
Differential stage trips when vP crosses vN.
Class-A transconductor trips when vGA crosses VTRIPA: Analyze when circuit balances.
⎛ 2I B2 ⎞
VTRIPA = v DD − v SGA(IBIAS ) = v DD − ⎜⎜ VTP 0 + tGA: IT slews CGA.
⎝ K P'(W/L)A ⎠
MA reacts when

vGA reaches VTRIPA.

∴ tP = tGA + tO.

IO(MAX) – << IO(MAX) +

∴ SRO– << SRO+.

à tP(F) >> tP(R).

IT limits SRGA delays tGA+ and tGA– à Faster with higher IT.
Wide gate swing at vGA delays falling response (tGA+) à Faster with lower swing.

Linear Two-Pole Step Response

Assuming no slew-rate conditions exist:
Raising the second pole pO
à Removes pO.
accelerates response.

Two
equivalent
poles.
Reducing the
second pole pO à Removes
slows response. pGA.

All poles slow response ∴ Shift as many poles as possible to high frequency.

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D. Clamped and Buffered Two-Stage Class-A Transconductor

MG12 limits vGA's swing and Class-AB inverters(1,2,3) drive low-Z loads.
(1) Center trip points: Balance FET strengths ∴ Offset µN/P and vT mismatches.
(2) Raise bandwidth: Lighten MAB2's load ∴ Minimum-size clamp and inverter.
(3) Raise CL's slew rate: Build drive current ∴ Increasingly larger inverters.
Lowest delay with e ≡ 2.67× larger stages, but inverters dissipate power ∴
use 5× to 10× larger stages.

Example if VTN0 = |VTP0|:

(1) W ≡ 2.5WNI1
PI1

(2) L ≡ LMIN
G1,G2,I1,I2

(2) W ≡ WMIN
G1,G2,NI1

(3) W ≡ 5WPI1
PI2

(3) W ≡ 5WNI1
NI2

7.3. Summing Comparators

Use: Sum analog inputs ∴ Trip when vA + vB crosses 0.
How: Project voltages to currents that sum.
Operation: MA12 and MB12's iD projections sum and balance when inputs balance.
Matching Requirements: M1:M2, MA1:MA2, MAT:MBT, MA12:MB12, M9:M10, M3:M4.

iO = (vAP – vAN)gmA12 + (vBP – vBN)gmB12 = 0 when inputs balance.

∴ If gmA12 ≡ gmB12, vO trips when vA + vB crosses 0.

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7.4. Hysteretic Comparators: A. Externally Defined

i. Inverting Configuration

State of vO sets vP and comparator trips when vIN crosses vP.

Positive feedback VOH R IN

VTRIP+ = v P =
v O =VOH R FB + R IN
establishes hysteresis.

VOL R IN
VTRIP− = v P =
v O =VOL R FB + R IN

VHYS = ΔVTRIP =
(V OH )
− VOL R IN
R FB + R IN

Inserting a voltage between RIN and ground shifts VTRIP+ and VTRIP–

by the same amount without affecting VHYS.

Trip points are sensitive to supplies via VOH and VOL à Variable and noisy.

ii. Noninverting Configuration

vIN and state of vO set vP and comparator trips when vP crosses 0.

" V %
Positive feedback VTRIP+ = v IN = i RFB R IN = $$ − OL '' R IN
establishes hysteresis.
v P =0 and v O =VOL
# R FB &

" V %
VTRIP− = v IN = i RFB R IN = $$ − OH '' R IN
v P =0 and v O =VOH
# R FB &

#R &
(
VHYS = ΔVTRIP = VOH − VOL %% IN ((
$ R FB '
)

Connecting a voltage to vN shifts VTRIP+ and VTRIP–

by the same amount without affecting VHYS.

Trip points are sensitive to supplies via VOH and VOL à Variable and noisy.

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B. Current Defined: i. Class-AB Transconductor

Transition when i1 ≥ i3. Schmidt Trigger
M2 is off and about to trip: vS2 = VTRIP+ – vTN2.
2
∴ i1 = 0.5K N'S1 ( VTRIP+ − VTN0 )
2
≡ i3 = 0.5K N'S3 ⎡⎣( v DD − v S3 ) − v TN2 ⎤⎦
2
≈ 0.5K N'S3 ( v DD − VTRIP+ )
Positive
Transition when i4 ≥ i6. Feedback

M5 is off and about to trip: vS5 = VTRIP– + |vTP5|. Trip points are insensitive to K',
2
∴ i 4 = 0.5K P'S4 ⎡⎣( v DD − VTRIP− ) − VTP0 ⎤⎦ but sensitive to vTN, vTP, vDD, and vSS.
2
≡ i 6 = 0.5K P'S6 ( v S5 − v TP5 ) ∴ Inaccurate, variable, and noisy.

≈ 0.5K P'S6 VTRIP− 2 Useful for digital applications.

ii. Two-Stage Class-A Transconductor

State of vO and iH produce an offset that vID must overcome to trip the comparator.

When vP rises towards vN,

Positive vO is initially low,
Feedback
∴ MFB is off and iH is 0, so

vO rises when i2 overcomes i1.

When vP falls towards vN,

vO is initially high,

∴ MFB is on and iH > 0, so

vO falls when i1 overcomes i2 + iH.

Notes: Positive feedback establishes hysteresis.

Hysteresis is asymmetrical: ΔVTH+ ≠ –ΔVTH–.

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If iH is low, use linear model. If iH is not low, use large-signal model.

iH 2i 2 2 (i2 + iH )
VHYS = VTRIP+ − VTRIP− = 0 − VOS(S) ≈ VOS(S) = v GS2 − v GS1 = −
g m1 S2 K N ' S1K N'

Where VT's cancel and

i1 + i2 = (i2 + iH) + i2 = IT.

Hysteresis is asymmetrical.

Trip points are

independent of the supplies.

C. Voltage Defined
ΔvH produces an offset that vID must overcome to transition vO.

MH1–MH2: Adds offset ΔvH when vO is low. ⎛g ⎞

VTRIP+ = VTRIP− = Δv H ⎜ mH12
Subtracts offset ΔvH when vO is high. ⎝ g m12 ⎠

ΔvH should be low to keep translation linear.

MH1–MH2 should match M1–M2 and MT should match MHT.

Hysteresis is symmetrical.

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D. Load Defined: Cross-Coupled Mirrors

When vI1 rises towards vI2,

vO1 is initially high,

∴ M3–M6 is off and vO1 falls

when i1 overcomes i2(S5/S4).

2i 2 (S5 /S4 ) Where VT's cancel and

2i 2
VTRIP+ = v GS1 − v GS2 = −
S1K N' S2 K N ' i1 + i2 = i2(S5/S4) + i2 = IT.

i1 = i2(S5/S4) > i2 ∴ i1 must surpass 0.5IT by some margin to induce a transition.

When vI1 falls towards vI2,

vO2 is initially high,

Positive
∴ M4–M5 is off and vO2 falls Feedback

when i2 overcomes i1(S6/S3).

2i1 2i1 (S6 /S3 ) Where VT's cancel and

VTRIP− = v GS1 − v GS2 = −
S1K N' S2 K N ' i1 + i2 = i1 + i1(S6/S3) = IT.

Notes: S6/S3 and S5/S4 should be greater than 1 to establish hysteresis.

S6/S3 and S5/S4 set the symmetry of the hysteresis.

Positive feedback establishes hysteresis.

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Example
Parameters:

vI1 = vIN, vI2 = VREF = 1 V,

S1 = S2 = S5 = S6 = 10,

S3 = S4 = 2, IT = 20 µA,

vDD = 2.5 V, vSS = –2.5 V,

and KN' = 100 µA/V2.

Solution:
VOH ≈ vDD
vIN+: i2(S5/S4) + i2 = IT at i1 = 16.7 µA.

ΔvO(MAX)
VTRIP+ = vGS1 – vGS2 + VREF ≈ 1.136 V

vIN–: i1(S6/S3) + i1 = IT at i1 = 3.33 µA.

VOL = vDD – vSG3
VTRIP– = vGS1 – vGS2 + VREF ≈ 0.864 V
Note that ΔvO(MAX) is vSG34 at IT à Low.

Folded Class-AB Transconductor

MAB1 mirrors M3's current i3 and M7 mirrors M4's current i4.
M8 and MAB2 fold M7's projection of i4 to output vO.

iO(MAX)+ = IT(SAB1/S3) ≡ iO(MAX)– = IT(S7/S4)(SAB2/S8)

Symmetrical slew rate, high voltage swing, and push–pull architecture.

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7.5. Regenerative Comparators: A. Concept and Latch

Concept: Positive feedback regenerates and latches vO to the supplies.
As vO regenerates, feedback grows and response accelerates.
Location: Positive feedback at the input shifts threshold to establish hysteresis.
Positive feedback at the output accelerates response with
gain-divided and therefore minimal effects on trip points.
Latch: Operation:
Small vI1 – vI2 difference vid
produces imbalance.
Positive feedback
Positive
Feedback regenerates
initial imbalance.

Basic Advantage: Regeneration accelerates transition à Faster response.

B. Response Time ⎛C t⎞ ⎛v ⎞ ⎛ 1 ⎞ ⎛ +t ⎞
Δv O(FIN) = Δv O(INI) exp ⎜ GS ⎟ = ⎜ id ⎟ g m1 ⎜ ⎟ exp ⎜ ⎟
Small Differential Input: g
⎝ m3 ⎠ ⎝ 2 ⎠ g
⎝ m3 ⎠ ⎝ τLATCH ⎠

i1 = 0.5vidgm1 ≈ –i2 = –0.5vidgm2 Positive Exponential

∴ ΔvO1(INI) = –ΔvO2(INI)

Δv O1 Δv O1 1
R EQ ≡ ≈ =−
Δi3 Δv O2g m3 g m3

C EQ ≈ CGS

Propagation Delay:

ΔvO(FIN) reaches 0.5(VOH – VOL) in tP.

⎛V −V ⎞
t P = τLATCH ln ⎜⎜ OH OL
⎟⎟
⎝ 2Δv O(INI) ⎠

Lower drive vID produces an exponentially slower response.

With positive feedback, response tP is a positive exponential ∴ Slow at first, then fast.

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7.6. High-Speed Comparators: A. Response Time

Regenerative Response
Linear Response

Fast at first, Slow at first,

even with low input drive, and with little regeneration, and
Slow in the end. Fast in the end,
as output regenerates.
∴ Use: Linear input stages to amplify drive.
Regenerative output stages to accelerate transitions.

B. Design Notes
Low resistances raise bandwidth and lower gain.
Poles near f0dB are harmless.
∴ Use multiple low-gain, high-bandwidth stages.
Linear stages are faster with low overdrive ΔvIN.
Regenerative stages are faster with high overdrive ΔvIN.
Low-voltage swings ΔvO shorten propagation delay.
∴ Use linear low-swing preamplifier and regenerative high-swing output.

To drive large CL with least delay, use increasingly 2.67× larger AB inverters.
But to reduce power, build drive with 5× to 10× larger AB inverters.

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Example
Two low-gain, low-swing pre-amplifiers with regenerative Class-AB output.

Gate-Drive Booster à Three balanced

5× larger
Class-AB inverters.

High-swing Class-AB latch.

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