Interfacing ADC and DAC

with 8051
Quantization
• The process of assigning/demarcating fixed, discrete and identifiable
levels to a range of continuous amplitude voltage is called
quantization.
• The discretization process is performed on the amplitude of the
analog voltage profile.
• Example:
• A voltage level between 0 V to 5 V can be divided into 2, 4, 8,…or upto 2n levels. Where
each level can be represented/indicated by a combination of binary symbols.
• If n=8, then each of the 256 levels can be represented by 00H, 01H, …, FFH binary words.
• Resolution of quantization is given by (Max voltage range-Minimum voltage)/(2n-1).
• For n=8, Vmax=5V and Vmin=0V, Resolutions is=5/255=19.6078 mV
Ratio-metric conversion
Vmeasured Dmeasured 𝑉𝑚𝑒𝑎𝑠 − 𝑉𝑚𝑖𝑛 𝐷𝑚𝑒𝑎𝑠 − 𝐷𝑚𝑖𝑛
=
0 V (Vmin) 00H (Dmin) 𝑉𝑚𝑎𝑥 − 𝑉𝑚𝑖𝑛 𝐷𝑚𝑎𝑥 − 𝐷𝑚𝑖𝑛
Vmeas Dmeas
5V (Vmax) FFH(Dmax) 𝑉𝑚𝑎𝑥 − 𝑉𝑚𝑖𝑛
𝑉𝑚𝑒𝑎𝑠 = × 𝐷𝑚𝑒𝑎𝑠 − 𝐷𝑚𝑖𝑛 + 𝑉𝑚𝑖𝑛
(𝐷𝑚𝑎𝑥 −𝐷𝑚𝑖𝑛 )

𝑉𝑚𝑒𝑎𝑠 = 𝑅𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 × 𝐷𝑚𝑒𝑎𝑠 − 𝐷𝑚𝑖𝑛 + 𝑉𝑚𝑖𝑛

𝑉𝑚𝑎𝑥 −𝑉𝑚𝑖𝑛
Where, Resolution=
(𝐷𝑚𝑎𝑥 −𝐷𝑚𝑖𝑛 )

𝑉𝑚𝑒𝑎𝑠 = 𝑅𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 × 𝐷𝑚𝑒𝑎𝑠 − 𝐷𝑚𝑖𝑛 + 𝑉𝑚𝑖𝑛

𝑉𝑚𝑎𝑥 −𝑉𝑚𝑖𝑛 𝑉 −𝑉
Where, Resolution= = 𝑚𝑎𝑥𝑁 𝑚𝑖𝑛
(𝐷𝑚𝑎𝑥 −𝐷𝑚𝑖𝑛 ) (2 −1)
Where, N = Number of binary bits required to encode
a level
Practical Implementation
• Analog to Digital conversion: ADC Hardware
• N=Resolution of ADC
• Types: Successive approximation , Sigma delta
• Application: Most general application is to quantize and digitize analog
signals from sensors indicating external conditions in analog form for
processing in digital domain by digital devices like a PC.
• Important properties of an ADC device:
• Resolution
• Conversion time
• Type
• Accuracy. Linearity
• Requirement of power supply and clock
• Interfaces available to interact with other digital devices or processors
ADC 0808/ADC0809
• 8-Bit μP Compatible A/D Converters with 8-
Channel Multiplexer
• Resolution: 8 Bits, Successive approximation type
• 8-Channel Multiplexer with Address Logic
• 0V to VCC Input Range
• Single Supply: 5 VDC, Low Power: 15 mW
• Clock requirement: 10 KHz-1280KHz, Typ: 500
KHz
• Conversion Time: 100 μs
• 28 Pin PDIP
Input channel selection
ALE

C Internal C (MSB)
B B
A Latch A (LSB)

IN0 Input
IN1 8 BIT
IN2 channel
IN3 multiplexer SAR
IN4
IN5
IN6
IN7
Timing Diagram
Steps to operate ADC0808/0809 (protocol)
1. Provide the channel address pins C (MSB), B, A(LSB). Allow time for the logic states on pins to
stabilize
2. Make ALE=1 and after a while make ALE=0. After making ALE =0 the logic states present on C, A
and B pins will be latched in an internal latch. The latched status of those pins will provide the
control signal to an internal multiplexer that will select appropriate input channel.
3. Make Start=1 (From zero). This clears the SAR registers and initializes the SAR ADC for
operation
4. Make Start=0. This starts the conversion. Thus a negative edge on Start pin starts the
conversion
5. Wait for EOC pin to Go low (From a normally high state). EOC=0 means conversion has started.
6. Wait for EOC pin to go high (from Low state). EOC=1 mean conversion has ended
7. Make output enable pin, OE=1. Making OE=1 allows the converted codes to appear on eight
output pins for being read by microcontrollers or processors. The output pins D0-D7 of 0809
will be tristated as long as OE remains 0.
Interfacing ADC 0809 with 8051
+5 V Clock Ground

IN0
P0.7
.
D7 IN1
.
. .
IN2
. . IN3
P0.0 D0 IN4
IN5
P3.3 EOC
IN6
IN7
8051 P3.5
ADC0809
Start
P3.6 OE
Vref+ +5 V
P3.4 ALE
Vref-
P3.2 C 0V
P3.1 B
P3.0 A
Interfacing Program: To read continuously the
ADC data and output at port 1.
ORG 0000H
MOV P0, #0FFH; SET P0 AS INPUT PORT
MOV P1, #00H; SET P1 AS OUPUT PORT TO SEND OUT ADC DATA
MOV P3, #08H; CONFIGURE P3.3 AS INPUT PIN (EOC), REST AS OUTPUT PINS
CLR P3.4; MAKE ALE=0;
CLR P3.0; BIT A=0
CLR P3.1; BIT B=0
CLR P3.2; BIT C=0, SELECT CHANNEL 0
ITER: SETB P3.4; ALE=1
NOP
NOP
CLR P3.4; ALE=0
SETB P3.5, SOC=1
CLR P3.5, SOC=0
Interfacing Program
HERE1: JB P3.3, HERE1; WAIT FOR EOC PIN TO GO LOW
HERE2: JNB P3.3, HERE2; WAIT FOR EOC PIN TO GO HIGH
;CONVERSION ENDS AT THIS POINT, TIME TO READ CONVERTED DATA
SETB P3.6; MAKE OE=1, THEN DATA WILL BE AVAILABLE AT D0-D7 PINS
;OF ADC0809
MOV A, P0; READ CONVERTED WORD AVAILABLE AT PORT 0
CLR P3.6; OE=0, D0-D7 OF ADC0809 IS TRISTATED AGAIN
CALL DELAY; A SUITABLE DELAY BETWEEN READING SAMPLES MAY BE GIVEN
MOV P1, A; OUTPUT THE DATA READ FROM ADC TO PORT A
SJMP ITER
END
Interfacing DAC with 8051
IC DAC1408
• 8 bit monolithic multiplying DAC
• 8 nos. of R-2R ladder network
• Needs a Current reference (Iref+ and
Iref-)
• Produces a Current mode output (Iout)
• Package: 16 pin Ceramic or Molded
DIP
• Power supply requirement:
• V+ = +5V (typical),
• V- = -15 V (typical)
• Digital input voltage (D7 – D0): 5 V
(TTL), 3.3 V (CMOS logic)
• Power consumption: 33 mW ( at ±5
V supply)
Connection diagram
Example: Generate a triangular wave of 0-5 V
using Digital to Analog converter 1408 and micro-
controller 8051
ORG 0000H
MOV A, 0
INCOUT: MOV P2, A
LCALL DELAY
INC A
CJNE A, #0FFH, INCOUT
DECOUT: MOV P2, A
LCALL DELAY
DEC A
CJNE A, #00H, DECOUT
SJMP INCOUT
END