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Disclaimer
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continued progress in methodology, design and manufacturing. Ericsson shall
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Contents
1 Product Overview 1
1.1 Purpose 2
1.2 Client Signal Mapping 3
1.3 Variants 8
1.4 Hardware and Software Compatibility 9
2 Function Description 9
2.1 FPGA, CPLD and Flash 12
3 Dimensions 14
4 Power 14
5 Physical Interfaces 14
5.1 Optical Interfaces 14
5.2 Front Panel Devices 18
5.3 Link Settings 19
Glossary 21
Reference List 23
1 Product Overview
This document describes the 10G ADM Muxponder E1, ROA 128 4372/1.
Figure 1 shows the unit.
The board is intended to equip MHL3000 High Density Subrack and MHL3000
Compact Subrack. In Both subracks it will occupy two 0.8” slots for a total
of 1.6” width.
1.1 Purpose
The 10G ADM board supports a flexible Add-Drop function over a 10G OTU2
link. A great variety of client signals can be multiplexed and loaded onto the
2xOTU2 Line interfaces. Flexibility is achieved by:
• the number of signals to add and drop (clients), from 0 to 8 optical data
streams and up to 16 E1 electrical data streams
The 10G ADM Muxponder E1, ROA 128 4372/1 is provided with:
The unit consists of a single board, without any Line Termination Unit (LTU)
associated. The SFP and XFP modules are not included.
Note: Mapping into ODU0 is not allowed, direct mapping into ODU1 is
implemented
The data-path has to be chosen, according to the client signal, following the
indications provided in Table 1.
For all the client types supported, Table 1 details the types of signal mapping
that each client can support.
4.25 Gbit/s ± 100ppm = Fibre Channel 8B/10B GFP-T >> OPU1-2v >>
ODU2
This operation can be performed via GFP or via proprietary OPTM; this has
to be selected according to the client signal type (refer to Table 1) to be
multiplexed in order to achieve the best bandwidth allocation; in case no need
of multiplexing (for example STM-16/OC-48 or OTN client signal) the standard
OTN transparent mapping is adopted as usually performed in any other
transponder/muxponder card. A particular case is instead represented by the
4G Fibre Channel where a proprietary concatenation of 2xODU1 is required.
GFP Multiplexing
As a general rule the Ethernet clients (Fast Ethernet
or Gigabit Ethernet) are mapped via GFP-F, while all
8B/10B coded signal are mapped according GFP-T (in
any case a Gb Ethernet client could be also mapped via
GFP-T - path 2 - if seen as a generic 8B/10B data signal,
this is not true for the FE which is a 4B/5B data signal).
OPTM Multiplexing
This method is proprietary and allows a sub-allocation of
the OPU1 payload area into 16xOPU1 Tributary Slots:
at first the OPU1 area is divided using the OPTM in 16
slots and then each one (or group of them) is allocated
to SDH/SONET clients or to data clients previously
mapped via GFP standard protocol.
TS-1 155,52
TS-4 622,08
TS-4-3c 1866,24
2xODU1 Concatenation
In case of 4G FC, it is needed to select a specific
mode to carry this type of traffic. Two ODU1 are used
in concatenated mode (G.709 standard OPU1-2v
concatenation) so that they are seen as a single payload
and managed according to the concatenation rules.
Also this type of mapping is identified by a specific
payload type, according to the standard in this case,
to be associated to the relevant ODU1’s, so that the
receiving ADM knows how to demap the container.
The mapping into the ODU2 is standard, following, for each line, the following
path: 4xODU1 to ODTU12 » ODU2 » OTU2
The exact number of VC-4s to be multiplexed into the destination STM-16 can
be assigned to each individual client during the configuration phase.
E1 Mapping
16xE1 > 16xV12 > 1xVC-4 > STM-1 ≡ VC-4 > STM-16 > OPU1 > ODU1
> ODTU12 > ODU2 > OTU2
STM-1 ≡ VC-4 > STM-16 > OPU1 > ODU1 > ODTU12 > ODU2 > OTU2
STM-4 ≡ 4xVC-4 > STM-16 > OPU1 > ODU1 > ODTU12 > ODU2 > OTU2
STM-16 Mapping
In this case the native STM-16 does not need any multiplexing, but is only
wrapped into an ODU1 as usual:
STM-16 > OPU1 > ODU1 > ODTU12 > ODU2 > OTU2
OTM-0.1 Mapping
The FE is mapped via GFP-F mode into 1xVC-4 of the destination STM-16:
FE > GFP-F > 1xVC-4 > STM-16 > OPU1 > ODU1 > ODTU12 > ODU2 > OTU2
GE > GFP-F > VC-4-7v > STM-16 > OPU1 > ODU1 > ODTU12 > ODU2 > OTU2
1.3 Variants
This unit has been introduced in Marconi MHL 3000 Release 6.0. No other
variant exists.
2 Function Description
The block diagram in Figure 4 shows the main functions of the unit.
0 Mapping of various client signals into ODU1 and then ODU1 multiplex
into ODU2
• The E1 Daughter Board manages the 16 E1 channels. The board has the
task to map the 16 E1 into two STM-1 that correspond to two interfaces of
the HyPHY20G device. The 16 electrical links are directly connected to the
Line Interface Unit (LIU) device that, via a proper bus, communicate with
the ADM chip for providing: TU mapping of the PDH interfaces into STM-1
SDH Interfaces and ADD/DROP capability. A CPLD is used to interface
the microprocessor of the mother board with the daughter board devices
(that means LIU and ADM devices).
Note: The LIU device ensures the short and medium haul applications
that means a 24 dB of cable loss attenuation for T1 hierarchy and
a 22 dB of cable loss attenuation for E1 hierarchy (electrical Line
according to ITU G.703, line impedance 120
fixed).
0 OTU1 (up to 8)
0 OC-3/12/48 or STM-1/4/16
• 2 XFP modules for OTU-2 / OTU-2e. They are DWDM Tunable XFP
modules.
• A Power Supply section provides the card with all the required voltage rails.
16 16 x I2C Bus
Client
SFP Data Bus µP Bus
I2C Bus CPLD
SCC/FCC µP
FPGA
SFP
Section
µP Bus
SFP
2
SFP
2 x I2C Bus
Backplane
SFP PCIe FW
SFP
SFP
20G
XFP
SFP Multi-Rate 10Gb/s
Multi-Protocol XFP
PHY 4
2
LIU ADM
DDR QDR
QDR TIMING
DDR
CPLD
DDR QDR
1V
1.2V
1.5V
1.8V
POWER
To µP 3.3V SUPPLY
5V
-5.2V
SFP Modules converts the client signals into an electrical signal that is directly
transmitted to the HyPHY20G by standard SFI Interfaces. The framer performs
all main add/drop and multiplexing/demultiplexing functionalities that are:
• Add/Drop and Muxponder. The supported client signals are listed in Table 6
The processed signal is then sent to the 2 Line Optical Interfaces based on
DWDM Tunable XFPs.
Most of the Timing structure is integrated in the HyPHY20G Framer, which only
needs a 155.52Mhz clock to operate all supported mapping/demapping and
multiplexing/demultiplexing functions.
2.1.1 FPGA
The Companion Field Programmable Gate Array (FPGA) properly interfaces
the HyPHY20 Framer through PCIe Interface. HyPHY20 internal registers are
replicated internally by the FPGA to make them visible to uP bus. The FPGA
also manages extraction/insertion of GCC channels (maximum 4) from/to PCIe
Interface, while providing serial channels on the uP side for their management.
The FLASH memory is organized in order to contain two different Banks (1 and
2) in which to store two application software and two configuration bitstreams
(for FPGA).
Note: The FLASH memory contains also the boot software for the card, but
this bank cannot be managed by the User.
Bank #1 is used only for recovery in case that Bank #2 goes corrupted during
dynamic upgrade. The SW cannot change it.
2.1.3 CPLD
The Complex Programmable Logic Device (CPLD) is a non volatile device
there is a internal flash memory, loaded at the board factory) to control of the
Optical Modules; in particular:
I2C The CPLD handles the I2C interface from the µP to the
16 SFP and 2 XFP, by avoiding address conflicts and
managing clock stretching feature.
LED The µP set the 16 SFP LEDs and 2 XFP LEDs by the
CPLD.
3 Dimensions
4 Power
5 Physical Interfaces
Both the client and the WDM interface are accessed via optical front panel
connectors (LC-UPC).
Due to the XFP/SFP orientation on the front panel of the unit, the following
patch cords have to be used to allow the rack doors closure:
Client Interfaces
Each client interface is ‘hot pluggable’ without affecting the other clients. Hot
configurability (for example the client signal type) of each client ports results in
no change in the line data rate.
The client signals are managed by using both gray and colored SFP modules:
Line Interfaces
The line signals are managed by using both gray and colored SFP modules:
Power (PWR) 1xGreen colored LED. Lit when all on-board power
supplies are on and functioning correctly
Note: The ALS feature is managed via software. ALS software management
cannot be disabled.
Glossary
AC MF
Active Module Fail
ALM OTH
Alarm Optical Transport Hierarchy
ALS OTU-n
Automatic Laser Shutdown Optical Transport Unit -n
APS PCIe
Automatic Protection Switch HyPHY20
CPLD PWR
Complex Programmable Logic Device Power
DF SC
Data Fabric Shelf Controller
ESCON SDH
Enterprise Systems Connection Synchronous Digital Hierarchy
FE SF
Fast Ethernet Signal Failure
FEC SFP
Forward Error Correction Small Form-factor Pluggable
FICON SM
Fibre Connection Service Module
FPGA SM10G
Field Programmable Gate Array 10 Gigabit Service Module
GE STM-n
Gigabit Ethernet Synchronous Transport Module -n
HW TDM
Hardware Time Division Multiplexing
JTAG TS
Joint Test Action Group Time Slots
LIU
Line Interface Unit
LTU
Line Termination Unit
Reference List
[1] Marconi MHL 3000 - Pluggable Modules Safety Rules, 3/124 46-CSA
113 62 Uen