ISSN 2319-8885

Vol.06,Issue.22
June-2017,
Pages:4483-4489
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Design of FIR Filter using Rounding Based Approximate (ROBA) Multiplier

SHABHANA BEGUM1, M. VIJAYA KUMAR2
1
PG Scholar, Dept of ECE, Gudlavalleru Engineering College, Gudlavalleru, AP, India.
2
Assistant Professor, Dept of ECE, Gudlavalleru Engineering College, Gudlavalleru, AP, India.

Abstract: The increasing complexity of the DSP systems demanding higher computational performance in its architecture. But
the traditional DSP arithmetic has limits in terms of speed of calculations. More over in some applications speed is more
important than accuracy. In order to further enhance performance, approximate arithmetic circuits are designed with some loss of
accuracy to reduce energy consumption and increase the speed. These approximate circuits have been considered for error-
tolerant applications. In this paper, we propose an FIR filter based on Rounding Based Approximate (ROBA) Multiplier. In this
multiplier the operands are rounded to the nearest exponent of two. This approximation will lead to simplification of
multiplication operation thus reducing area and increasing speed. As the multiplier is the slowest element in the system, it will
affect the performance of the overall FIR filter. The proposed ROBA multiplier based FIR filter was compared with HAAM and
DRUM multiplier based FIR filters. The results shown significant reduction in the power and area of the FIR filter with
proportional improvement in the multiplier speed. The Filter was implemented and tested using Virtex 5 FPGA at an operating
voltage of 1.0V using Xilinx ISE environment.

Keywords: Approximation, Energy Efficiency, Multiplication, Digital Signal Processing, Finite Impulse Response(FIR), ROBA
Multiplier.

I. INTRODUCTION In IIR filter by using feedback problems will raise but in

In the field of electronic industry digital filters are used
extensively. The noise ranges gradually increases by using
analog filters for better noise performance can be obtained
by using digital filters compared to analog filters. At every
intermediate step in digital filter transformation able to
perform noiseless mathematical operations. Our design
includes the optimization of bit width and hardware
resources without any impact on the frequency response and
output signal precision. Addition (or subtraction),
Multiplication (normally of a signal by a constant)Time
Delay i.e. delaying a digital signal by one or more sample
periods are three basic mathematical operations used in
digital filters. The coefficients are multiplied by fixed-point
constants using additions, subtractions and shifts in a
multiplier block. In VLSI Signal Processing two types of
digital filters are most widely used one is FIR (finite impulse
response)and the other is IIR(infinite impulse response).FIR
as indicates that the impulses are finite in this filter and
phase is kept linear in order to noise distortions and no
feedback is used for such a filters. As compared to IIR, FIR
is very simple to design. Such type of FIR filters are used in
DSP processors for high speed. In Digital Signal Processing
Multiplication and addition is of times required. A high
speed addition is done by parallel prefix adder and the better
version of truncated multiplier with fewer components
makes the reduction in delay. In Digital Signal Processing,
FIR filters define less number of bits which are designed by
using finite precision.
FIR filters limited bits are efficient in which there is no
feedback. Using fractional arithmetic we can implement FIR
filters.The multipliers play a significant role in arithmetic
operations in DSP filtering applications. Multiplication is a
hardware intense operation, and the main areas of interest
are higher speed, lower cost, and less VLSI area. Two
significant yet often conflicting design criteria are power
consumption and propagation delay. Considering these
constraints, the development of low power multiplier is of
great interest. In this paper, we focus on proposing a high-
speed low power/energy yet approximate multiplier
appropriate for error resilient DSP applications. The
contributions of this paper can be summarized as follows:
1. Presenting a new scheme for ROBA multiplication by
modifying the conventional multiplication approach;
2. Describing three hardware architectures of the proposed
approximate multiplication scheme for sign and
unsigned operations. The proposed FIR filter consists of
approximate multiplier, which is also area efficient, is
constructed by modifying the conventional
multiplication approach at the algorithm level assuming
rounded input values.
II. LITERATURE SURVEY
R. Hegde and N. R. Shan hag in 2001 proposed a framework
for energy efficient digital signal processing [15]. The
supply voltage is scaled further, which is the critical voltage
required to fix the critical path delay to the throughput. This

Copyright @ 2017 IJSETR. All rights reserved.

 SHABHANA BEGUM, M. VIJAYA KUMAR
introduction of input-dependent errors leads to degrade in
the algorithmic performance, which is compensated through
the Algorithmic Noise Tolerance (ANT) schemes. A
prediction based error-control scheme is proposed to the
filter algorithm performance and the presence of errors
computations. The CMOS technology reduction in energy
dissipation has made possible due to energy-efficient design
techniques at all possible levels of design hierarchy.
V. K. Chippa et.al.in 2010 proposed scalable effort hardware
design as an approach to tap the reservoir of algorithmic
recover and translate it into highly efficient hardware
implementations [14]. The basic idea of the scalable effort
design is to identify mechanisms at each level of design
abstraction like circuit, architecture and algorithm that can
be used to varying the computational effort. A second major
idea of the scalable effort design approach is that fully based multiplication section is activated to multiply the MSBs.
on the potential of algorithmic recover requires synergistic
cross layer optimization of scaling mechanisms are identified
at different levels of design abstraction.
C. H. Chang and R. K. Satzoda in 2010 proposed to ignore
the least significant columns in the partial product (pp) bit
matrix obtained from an n-bit multiplication [13].A small
amount of additional hardware is added to compensate for
the truncation errors. This method achieves lower average
and spread of errors by means of adaptive pseudo carry
compensation and a constant bias that is independent of
supply. By especially the symmetry of the multiplexer-based
array multiplier the partial product bits are generated by the multiplier is then used to build larger multipliers with error
multiplexers. The truncated multiplier can be assembling in a
carry-save adder format to reduce the area and improve the
speed over than other truncated array multipliers.
Approximate Multipliers:
Approximation can be performed using different
techniques such as allowing some timing violations (e.g.,
voltage over scaling or over-clocking) and function
approximation techniques (e.g., modifying the Boolean
function of a circuit) or a mixture. Approximate multiplier
designs mainly use three approximation approaches:
 Approximation in generating the partial products.
 Applying truncation in the partial product tree.
 Using approximate adders &compressors to
accumulate the partial products.
P. Kulkarni et.al. Proposed multiplier architecture for 2x2
inaccurate multiplier done by Karnaugh map simplification
for generating approximate partial products[10].It is an
approximate 2x2 multiplier block by altering one entry in the
K-Map of a 2x2 multiplier. Based on the 2x2 block, larger
under designed multipliers (UDMs) can be built. This
multiplier design introduces error in generating partial
products while the adder tree remains accurate.
H. R. Mahdiani proposed multiplier called Broken-Array
Multiplier (BAM)[12].It is very similar to the structure of an
array multiplier. The BAM operates by omitting some carry-
save adders in an array multiplier in both horizontal and
vertical directions.
International Journal of Scientific Engineering and Technology Research
Volume.06, IssueNo.22, June-2017, Pages: 4483-4489
F. Farshchi, M. S. Abrishami Based on BAM, a Broken-
Booth Multiplier (BBM) was presented [5]. Compared to
BAM, BBM uses modified Booth algorithm to generate
partial products and only omits carry-save adders to the right
of a vertical line. BBM has a smaller power-delay-product
(PDP) than BAM.
K. Khaing Yin, G. Wang Ling, and Y. KiatSeng proposed
Error-Tolerant Multiplier. (ETM) is divided into a
multiplication part for the MSBs and a non-multiplication
part for the LSBs[11]. A NOR gate based control block is
used to deal with two cases: a) If the product of the MSBs is
zero, then the multiplication section is activated to multiply
the LSBs without any approximation b) If the product of the
MSBs is nonzero, the non-multiplication section is used as
an approximate multiplier to process the LSBs, while the
K. Bhardwaj, P. S. Mane proposed approximate Wallace tree
multiplier [4]. It is power and area efficient multiplier.
AWTM is based on a bit-width aware approximate
multiplication algorithm and Carry-in Prediction technique is
employed which significantly reduces the critical path delay.
BAM, BBM, ETM, AWTM multipliers uses approximation
in the partial product tree. This compressor is used in a
bottom-up tree topology to implement a high-speed, area-
efficient and power-aware approximate multiplier. An
inaccurate 4-bit Wallace multiplier based on a newly
designed (4:2) approximate compressor. The inaccurate 4-bit
detection and correction circuits. This multiplier is referred
to as Inaccurate Compressor based Multiplier (ICM).
III. PROPOSED APPROXIMATE MULTIPLIER
A. ROBA Multiplier
The main idea behind the proposed approximate multiplier
is to make use of the ease of operation when the numbers are
two to the power n (2n). To elaborate on the operation of the
approximate multiplier, first, let us denote the rounded
numbers of the input of A and B by Ar and Br, respectively.
The multiplication of A by B may be rewritten as
A*B=((Ar-A)*(Br-B))+(Ar*B)+(Br*A)-(Ar*Br) (1)
The key observation is that the multiplications of Ar × Br,
A r × B, and Br × A may be implemented just by the shift
operation. The hardware implementation of (Ar − A) × (Br −
B), however, is rather complex. The weight of this term in
the final result, which depends on differences of the exact
numbers from their rounded ones, is typically small. Hence,
we propose to omit this part from (2), helping simplify the
multiplication operation.Hence, to perform the multiplication
process, the following expression is used:
A*B=(Ar*B)+(Br*A)-(Ar*Br) (2)
Thus, one can perform the multiplication operation using
three shift and two addition/subtraction operations. In this
approach, the nearest values for A and B in the form of 2n
 Design of FIR Filter using Rounding Based Approximate (ROBA) Multiplier
should be determined. When the value of A (or B) is equal to multiplier leads to near-zero average error. As a result, our
the 3 × 2(p-2)(where p is an arbitrary positive integer larger unbiased design promotes errors to cancel each other rather
than one), it has two nearest values in the form of 2n with than accumulate in the final result of the computation. A
equal absolute differences that are 2p and 2p−1. While both dynamic and fast bit selection scheme to reduce the size of
values lead to the same effect on the accuracy of the the multiplier while introducing a bounded unbiased error to
proposed multiplier, selecting the larger one (except for the the multiplication result. Assuming each operand has n bits,
case of p = 2) leads to a smaller hardware implementation our design uses two leading one detector (LOD) circuit
for determining the nearest rounded value and hence, blocks to dynamically locate the most significant ‘1’ in each
it is considered in this paper. It originates from the fact that of the two operands as illustrated in Figure 2. For each
the numbers in the form of 3 × 2 (p-2) are considered as do operand, the location of the most significant ‘1’ is then used
not care in both rounding up and down simplifying the to select the following k-2 consecutive number of bits based
process, and smaller logic expressions may be achieved if on the required accuracy. Here, k is a designer-defined value
they are used in the rounding up. It should be noted that which specifies the bandwidth used in the core accurate
contrary to the previous work where the approximate result multiplier. To reduce the error, we approximate the value of
is smaller than the exact result, the final result calculated by the remaining lower bits to equal its expected value. If the
the ROBA multiplier may be either larger or smaller than the leading one is detected at index t, where ,
exact result depending on the magnitudes of Ar and Br then the value of the remaining t-k+2 lower bits is between 0
compared with those of A and B, respectively. Note that if and 2 t-k+2 -1. Assuming a uniform distribution for the values
one of the operands (say A) is smaller than its corresponding of the operands, then the expected value is almost equal to
rounded value while the other operand (say B) is larger than 2(t-k+1). Thus, we unbias the approximation of the last t-k + 2
its corresponding rounded value, then the approximate result bits of the number with ‘1’ placed at bit location t-k + 1 (the
will be larger than the exact result. This is due to the fact highest bit) and zeros for the rest of the indexes from index
that, in this case, the multiplication result of (Ar − A) ×(Br − t-k down to index 0 as illustrated in Figure 2. Finally, these
B) will be negative. Since the difference between (2) and (3) least t- k + 1 zero bits are truncated leading to k-bits as
is precisely this product, the approximate result becomes illustrated in Figure 3. These k-bit operands are then
larger than the exact one. Finally, it should be noted the forwarded to the inputs of a k*k accurate multiplier. The
advantage of the proposed ROBA multiplier exists only for result of this multiplication will then be shifted, using a
positive inputs because in the two’s complement barrel shifter, according to the location of the two leading
representation, the rounded values of negative inputs are not ones to generate the final approximate result.
in the form of 2n..Hence, we suggest that, before the
multiplication operation starts, the absolute values of both
inputs and the output sign of the multiplication result based
on the inputs signs be determined and then the operation be
performed for unsigned numbers and, at the last stage, the
proper sign be applied to the unsigned result.

Fig2. A general example of the approximation process.

(a)Original number. (b) Number after biasing. (c) Final
approximated input.
Fig 1. Block diagram for the hardware implementation of
the proposed multiplier.

IV. COMPARISON OF ROBA MULTIPLIER WITH

OTHER APPROXIMATE MULTIPLIERS
A. DRUM: Dynamic Range Unbiased Multiplier
DRUM multiplier used for approximate multiplication
applications. This multiplier dynamic nature enables the
multiplier to “zoom in” on the most significant digits of the
numbers, all while making the multiplier highly scalable and Fig 3. A numeric example of the DRUM multiplier (n=16,
configurable. Since a typical computation involves a large k=6) (a) The input numbers (b) Approximate inputs. (c)
number of multiplications, the unbiased nature of our Result before shifting (d)Approximate result.(e) Accurate
result.
International Journal of Scientific Engineering and Technology Research
Volume.06, IssueNo.22, June-2017, Pages: 4483-4489
 SHABHANA BEGUM, M. VIJAYA KUMAR
The hardware design of DRUM multiplier is shown in
Fig4. The hardware design is composed of two parts: a
steering logic and an arithmetic logic. The steering logic is
responsible for dynamically selecting the right range of the
input operands and feeding them to the arithmetic logic, and
afterwards positioning the calculated result from the
multiplier in the right index. Therefore the steering logic is
compromised of LOD blocks, encoders, multiplexers, and a
barrel shifter, while the arithmetic logic is conveniently a
small multiplier. Wallace-Tree multiplier as the core
multiplier due to its higher utilization in applications. One Fig 5. The architecture of 4:2 Counter.
key benefit of this architecture is that it does not restrict
designers from using their own preferred designs as the
smaller core multiplier. The significantly smaller arithmetic
logic justifies the addition of steering logic, which overall
leads to significant power and area savings compared to an
accurate multiplier. In the special case where the leading ‘1’
is within the least significant k bits, then our steering logic
forwards the least k bits directly to the multiplier.

Fig 6. A 4x4 wallace multiplier with 4:2 counter.

C. Building larger multipliers:

Fig 4. Block diagram DRUM Multiplier.
Larger multipliers are easily built by using inaccurate
4x4 wallace multipliers. Figure 7 shows an example of
building a 32x32 multiplier consisting of inaccurate 4X4
wallace multipliers. The 32x32 multiplication is decomposed
to three additions of 16x16multiplication results. Each 16x16
multiplication is decomposed to three 8x8 multiplication
results. Finally each 8x8 multiplication is decomposed to
three additions of 4x4 multiplication results.Note that adding
three partial products in the blocks can be reduced to adding
two partial products by using full adders (3:2 counters).
Then these two partial products are added by a normal adder.

B. HAAM (High Accurate Approximate Multiplier):

The main concept of HAAM multiplier is to replace
XOR gate with 2:1 MUX in inaccurate 4:2 compressor. Then
the new 4:2 compressor will have shorter delay. The layers
of the Wallace multiplier are reduced by an inaccurate 4:2
counter, so the delay and power of the Wallace multiplier
can be reduced. In order to reduce the delay of an inaccurate
4:2 counter as shown in figure 5. X1 to X4 are inputs. Sum
and carry are the outputs. Note that the error occurs when all
four summands are’1’ and the output 111 2 is reduced to 102.
This error is intentionally generated to achieve a simplified
algorithm. This inaccurate 4:2 counter can be used to build
an inaccurate 4X4 wallace multiplier as shown in figure 6.
An ordinary Wallace multiplier reduces the adding stages
from three stages to two stages, but it can reduce the adding
stages from four to two stages by using inaccurate 4:2
counter to further reduce the delay and the power. Note that
an inaccurate 4:2 counter is used to give the sum of partial
product becoming ‘1’is ¼, so the error of the inaccurate 4:2
counter occurs with a probability of (1/4) 4=1/256, which is
very low.
Fig 7. Building larger multipliers from smaller blocks.
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Volume.06, IssueNo.22, June-2017, Pages: 4483-4489
 Design of FIR Filter using Rounding Based Approximate (ROBA) Multiplier
V. FIR FILTER IMPLEMENTATION C. Parallel Prefix Adders (PPA)
In the FIR system, the impulse response is of finite duration, Parallel-Prefix adders perform parallel addition i.e. most
this means that it has a finite number of nonzero terms. The important in microprocessors, DSPs, mobile devices and
response of the FIR filter depends only on the present and other high speed applications. Parallel-Prefix adder reduces
past input samples. logic complexity and delay thereby enhancing performance
with factors like area and power. Parallel Prefix Adders
A. Normal FIR filter: (PPA) is designed by considering carry look adder as a base.
The conventional design of the FIR filter is shown in Parallel prefix computation carries out three necessary or
Figure 8.The implementation of an FIR requires three basic vital steps:
building blocks: Multiplication, Addition and Signal delay. 1. Computation of carry generation & carry propagation
FIR filter can be expressed as signals by using no. of input bits.
2. Calculating all the carry signals in parallel that is called
prefix computation.
3. Evaluating total sum of given inputs.
Where N represents the filter order, y [n] is the output
signal and bk represents the set of filter coefficients. If x[n] is
the input signal applied, x [n - k] terms are referred as taps or
tapped delay lines. In the conventional design, present a
simple structure of multiplier for FIR filters. It performs
multiplication by generating partial products. If the
multiplier digit is a 1, the multiplicand is simply copied
down and represents the product. If the multiplier digit is a 0
the product is also 0. Therefore the area and delay will
increase. It affects the performance of the FIR filter.

Fig 10. Parallel Prefix Adder mechanism

The process or three step that is carried out in the parallel

prefix addition is as follows:
1. Computation of carry generation, propagation signals:
Previous carry is calculated to the next bit is called
propagate signal and generate is to generate the carry bit
below are the signals:
Fig 8. Block diagram of FIR filter. Gi = Ai . Bi
Pi = Ai ⨁ Bi
B. FIR Filter Using ROBA multiplier 2. Calculation of all carry signals:
As the multiplier is the slowest element in the system, it Gi:j = Gi:k +Pi:k . Gk-1:
will affect the performance of the FIR filter. So, ROBA Pi:j = Pi:k . Pk-1:j
multiplier is suggested since it reduces area and it is faster
than other conventional multipliers. 3. Calculation of Final Sum:
Si = Pi ⨁ Gi-1:0

There are various types of Parallel-Prefix adders some of

which are discussed in this paper. Kogge-Stone adder, Brent-
Kung adder, Ladner-Fischer adder, Han-Carlson adder,
S.Knowles adder, Sklansky Conditional-Sum adder are the
few Parallel-Prefix adders. From all of the above adders
Kogge-Stone is the one that is widely and efficiently used.

D. Kogge-Stone adder
Kogge-Stone adder is a parallel-prefix form carry look
ahead adder. Kogge-Stone adder was developed by [3] Peter
M. Kogge and Harold S. Stone which they published in1973.
KS adder is a fast adder design as it generate carry signal in
O(log2 n) time and has the best performance in VLSI
implementations. KS adder has large area with minimum
fan-out which increases its performance. Kogge-Stone adder
is widely used in high performance 32-bit, 64-bit, and 128-
Fig9.Block diagram of FIR filter using ROBA Multiplier. bit adders as it reduces the critical path to great extent. In
International Journal of Scientific Engineering and Technology Research
Volume.06, IssueNo.22, June-2017, Pages: 4483-4489
 SHABHANA BEGUM, M. VIJAYA KUMAR
fig.3 each vertical stage produce propagate and generate bits.
Generate bits are produced in the last stage and XORed with
initial propagate and generate bits to produce sum.

Fig 13. Simulation result of FIR using ROBA multiplier

When compared the results of various approximate

Fig 11. Illustration of 16bit Kogge Stone Adder.
E. FIR filters using HAAM and DRUM multipliers:
In the proposed paper, in addition to the FIR using
ROBA multiplier we also implemented FIR using HAAM
and DRUM multipliers. HAAM and DRUM multipliers
algorithms are explained in the section IV. The further
details can be found from references [3][7].In the HAAM
and DRUM based FIR filter implementation the normal
multiplier is replaced with approximate HAAM and DRUM
multipliers. The results related to these FIR filters are
discussed in section VI.
VI. Results
Figure 12 shows Simulation result for ROBA multiplier
and figure 13 shows the implemented FIR filter using
proposed multiplier. The simulations are performed by using
Xilinx ISE simulator and virtex 5 FPGA.
multipliers with respect to area, delay and power the
following observations are made. From the table 1 the
number of LUTs occupied by ROBA multiplier were very
small when compared with the other approximate
multipliers. This is due to the multiplication process has
been significantly simplified by rounding the values to the
nearest power of two. Even though this results a small error
in the output value the area of the multiplier has been
drastically reduced. This reduced area results faster
multiplication and lower power consumption which is more
suitable for error tolerant DSP applications.
Table1: Comparison of ROBA multiplier with other
approximate multipliers

Next the FIR filter was implemented using various

approximate multipliers. These FIR filters were compared
with respect to area and power. Clearly the table 2 shows
that FIR filter with ROBA multiplier has occupied less area
and a fractional reduction in the total power consumption.
The reduced area and power are due to the fact that the
ROBA multiplier uses a good approximation technique
which uses less number of components to perform the
multiplication operation. As the number of components are
reduced the area as well as the power were also reduced. The
performance of various FIR filters with respect to power are
Fig 12. Simulation result of ROBA multiplier. shown in Fig 14 & 15.
International Journal of Scientific Engineering and Technology Research
Volume.06, IssueNo.22, June-2017, Pages: 4483-4489
 Design of FIR Filter using Rounding Based Approximate (ROBA) Multiplier
Table 2. Comparison of FIR filters using approximate
multipliers
Fig 14. Frequency vs power @ 1.2V.
Fig 15. Voltage vs power @ 80MHz.
VII. CONCLUSION
An approximate multiplier (ROBA) based FIR filter
implementation was proposed in the paper. The results show
that the proposed multiplier shows better performance in
terms of area, power and delay. The rounding based
approximation resulted in reduced area of the FIR filter
when compare to other approximations. Moreover reduced
area resulted in less delay an power consumption. The
system shows 40% speed improvement an occupying only
1/5thof the area of other approximate multipliers. The above
results were obtained after simulating the fir filter on Virtex Systems, Volume: 9, Issue: 6, pp:813 – 823, Dec. 2001.
5 FPGA using Xilinx ISE simulator at an operated volage of
1.0V.
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Volume.06, IssueNo.22, June-2017, Pages: 4483-4489
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