Combinational Logic

VLSI Circuit Design

Outline

• Pass Transistors
• Transmission Gates
• Pseudo nMOS Logic
• Tri-state Logic
• Dynamic Logic
• Domino Logic
Pass Transistors & Transmission Gates
Device Transmission of Transmission of
‘1’ ‘0’
nMOS poor good

pMOS good poor

A S S’ Vout
VSS 1 0 VSS (strong) due to nMOS
VDD 1 0 VDD (strong) due to pMOS
VSS 0 1 Z
VDD 0 1 Z

• Transmission gate is non-restoring – noise on A passes to Y

Pass Transistors & Transmission Gates
• nMOS pass transistor • pMOS pass transistor

▫ Vin=VDD ▫ Vin=VSS
▫ VG=VDD ▫ VG=VSS
▫ Vout  VDD – Vtn ▫ Vout  |Vtp|
▫ Not VDD – degraded 1 ▫ Not VSS – degraded 0
 Pass Transistors & Transmission Gates
• 2 input MUX

Y=AS’+BS
S=0, Y=A
S=1, Y=B

4 transistors 6 transistors
(2 to invert S)

• XOR
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

A=0, Y=B
A=1, Y=B’
Pass Transistors & Transmission Gates
• AND
A B Y
0 0 0
0 1 0
1 0 0
1 1 1

A=0, Y=A
A=1, Y=B

• OR
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

A=0, Y=B
A=1, Y=A
 Pseudo NMOS Logic (Ratioed logic)
• Single PMOS in pull-up network – gate
connected to VSS
• PMOS always in ON state
• Less transistors than CMOS, smaller area
• For N inputs, only requires (N+1) MOS
• NMOS logic array acts as a large switch Fig 1 General structure of a
pseudo-nMOS logic gate
between the output f and ground
• However, since the PMOS is always biased
on, VOL can never achieve the ideal value of
0 V – static power dissipation
• A simple inverter using pseudo-NMOS is
shown: Figure 2

Fig 2 Pseudo-nMOS inverter

Pseudo NMOS Logic (Ratioed logic)
• The design of nMOS array of pseudo-nMOS is the same as in
standard CMOS
▫ Smaller simpler layouts, and interconnect is much simpler
▫ Sizes need to be adjusted to ensure proper electrical
coupling to the next stage
▫ Resize in physical design – PMOS having ¼ strength
compared to NMOS (1/2 the effective width)

(a) NOR2 (b) NAND2 (c) Layout

Tri-state Logic (0,1,Z)
• A tri-state circuit produces the usual 0 and 1 voltages, but also
has a third high impedance Z (or Hi-Z)
▫ Useful for isolating circuits from common bus lines
▫ In Hi-Z case, the output capacitance can hold a voltage
even though no hardwire connection exists

(a) Symbol and operation (b) Tristate Inverter (c) Tri-state layout
Tri-state Logic

(a) EN = 0, f = Z (a) EN = 1, f = Data

Output isolated from both Normal operation
power supply and ground

• A non-inverting circuit (a buffer) can be obtained by adding a

regular static inverter to the input
 Dynamic Logic Circuits
• A dynamic logic gate uses clocking and charge
storage properties of MOSFETs to implement
logic operations
▫ Provide a synchronized data flow
▫ Result is valid only for a short period of time
▫ Less transistors, and may be faster than static
cascades

• Based on the circuit in Figure 3

▫ The clock  drives a complementary pair of
transistors Mn and Mp
▫ Precharge phase   0 , pMOS is ON, Vout high
▫ Evaluation phase   1, pMOS is OFF

Figure 3 Basic dynamic logic gateC

Dynamic Logic Circuits

Dynamic Inverter

Dynamic NOR
 Dynamic Logic Circuits
• During evaluation, dynamic gates
require monotonically rising inputs
▫ Start LOW, remain LOW
▫ Start LOW, rise HIGH
▫ Start HIGH, remain HIGH
▫ Cannot start HIGH and fall LOW

Fig 4 Dynamic logic gate example

Dynamic Logic Circuits
• Monotonicity problems
• Dynamic gates produce monotonically falling outputs during
evaluation
• Illegal for one dynamic gate to drive another
 Dynamic Logic- Charge sharing
• The origin of the charge sharing problem is the
parasitic node capacitance C1 and C2
▫ When clock   1 , and the capacitor voltage V1
and V2 are both 0 V at this time, the total
charge is Q  CoutVDD
▫ The worst-case charge sharing condition is
when the inputs are at (a, b, c) = (1, 1, 0)
Vout  V2  V1  V f (When the current flow ceases)
Charge sharing circuit
▫ The principle of conservation of charge
 Q  CoutV f  C1V f  C2V f
 (Cout  C1  C2 )V f
 Cout 
 Q  (Cout  C1  C2 )V f  CoutVDD    1
 Cout  C1  C2  Cout  C1  C2
 Cout 

 Vf   VDD V f  VDD
 Cout  C1  C2 
Domino Logic Circuits
• Follow dynamic stage with
inverting state gate
▫ Dynamic/static pair is called
Domino gate
▫ Produces monotonic outputs
▫ Non-inverting
▫ Useful in cascade operation
Domino Logic Circuits

Domino AND gate Domino OR gate

Layout for domino
AND gate