Académique Documents
Professionnel Documents
Culture Documents
JK FlipFlop:
entity JK_FF is
PORT( J,K,CLOCK: in std_logic;
Q, QB: out std_logic);
end JK_FF;
VHDL code for Rising Edge D Flip-Flop with Asynchronous Reset High Level:
Library IEEE; architecture Behavioral of
USE IEEE.Std_logic_1164.all; RisingEdge_DFlipFlop_AsyncResetHigh is
entity begin
RisingEdge_DFlipFlop_AsyncResetHigh is process(Clk,sync_reset)
port( begin
Q : out std_logic; if(sync_reset='1') then
Clk :in std_logic; Q <= '0';
sync_reset: in std_logic; elsif(rising_edge(Clk)) then
D :in std_logic Q <= D;
); end if;
end end process;
RisingEdge_DFlipFlop_AsyncResetHigh; end Behavioral;
VHDL code for Rising Edge D Flip-Flop with Asynchronous Reset Low Level:
Library IEEE; architecture Behavioral of
USE IEEE.Std_logic_1164.all; RisingEdge_DFlipFlop_AsyncResetLow is
entity begin
RisingEdge_DFlipFlop_AsyncResetLow is process(Clk,sync_reset)
port( begin
Q : out std_logic; if(sync_reset='0') then
Clk :in std_logic; Q <= '0';
sync_reset: in std_logic; elsif(rising_edge(Clk)) then
D :in std_logic); Q <= D;
end end if;
RisingEdge_DFlipFlop_AsyncResetLow; end process;
end Behavioral;
VHDL code for Falling Edge D Flip-Flop with Asynchronous Reset High Level:
Library IEEE; begin
USE IEEE.Std_logic_1164.all; process(Clk,sync_reset)
entity begin
FallingEdge_DFlipFlop_AsyncResetHigh is if(sync_reset='1') then
port( Q : out std_logic; Q <= '0';
Clk,D :in std_logic; elsif(falling_edge(Clk)) then
sync_reset: in std_logic); Q <= D;
end end if;
FallingEdge_DFlipFlop_AsyncResetHigh; end process;
architecture Behavioral of end Behavioral;
FallingEdge_DFlipFlop_AsyncResetHigh is
VHDL code for Falling Edge D Flip-Flop with Asynchronous Reset Low Level:
Library IEEE; architecture Behavioral of
USE IEEE.Std_logic_1164.all; FallingEdge_DFlipFlop_AsyncResetLow is
entity begin
FallingEdge_DFlipFlop_AsyncResetLow is process(Clk,sync_reset)
port( begin
Q : out std_logic; if(sync_reset='0') then
Clk :in std_logic; Q <= '0';
sync_reset: in std_logic; elsif(falling_edge(Clk)) then
D :in std_logic); Q <= D;
end end if;
FallingEdge_DFlipFlop_AsyncResetLow; end process;
end Behavioral;
Applications of flipflops:
1. Used as a memory element
2. Used to eliminate key debounce
3. Used as a delay element
Counters in VHDL:
VHDL code for a 4-bit Up-Counter:
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity upcounter is
Port(clock, resetn,EN : in std_logic;
Q : out std_logic_vector (3 downto 0));
End upcounter;
Architecture behaviour of upcounter is
Signal Count : std_logic_vector (3 downto 0);
Begin
Process (clock, resetn)
Begin
If resent = ‘0’ then count <= “0000”;
Elsif (clock’event and clock = ‘1’) then
If EN = ‘1’ then count <= count+1;
Else
count <= count;
end if;
end if;
end process;
Q<= count;
End behaviour;