Systems with Digital Integrated Circuits

The MOS transistor

Dr. Sorin Hintea

Basis of Electronics Departament
 Summary

N channel MOS transistors

Electric parameters and characteristics

Circuits components calculation

Enhancement channel pMOS transistors

Depletion channel MOS transistors

Systems with Digital Integrated Circuits - The MOS transistor 2

 The MOS transistor

MOS = metal oxid semiconductor is a four-terminal semiconductor device

which is the elementary building block of integrated circuits.

p channel (pMOS) and n channel (nMOS)

4-terminal devices: S G D S G D

gate G metal poly poly

oxide ox ox

drain D n n p p
semiconductor

source S p-type substrate n-type substrate

bulk B B B

The basic structure of a MOS transistor is illustrated in figure and consists of a

silicon substrate with either p- or n-type doping, which is the transistor body (B),
two implant regions with complementary doping, which are the source (S) and the
drain (D) respectively, and in-between is the transistor gate (G).
The transistor gate consists of a layer of dielectric, e.g. silicon dioxide, grown on
top of the silicon substrate and a conductor layer of polysilicon (polycrystalline
silicon ) deposited above.
Systems with Digital Integrated Circuits - The MOS transistor 3
 The MOS transistor

Symbols for MOS transistors:

p channel (pMOS) and n channel (nMOS)

4-terminal symbols: gate G drain D source S bulk (substrate) B

3-terminal symbols: gate G drain D source S (in digital electronics the bulk terminals
of the nMOS and pMOS transistors are implicitly connected to the negative and positive
supply respectively); the arrows are illustrating the source terminal

3-terminal symbols: gate G drain D source S (the arrows are omitted and only a
bubble on the transistor gate differentiates between the nMOS and pMOS transistors
respectively

Systems with Digital Integrated Circuits - The MOS transistor 4

 The nMOS transistor – OFF and ON state

Unbiased MOS
Small positive
Gate voltage higher than

transistor → the pn voltage (VG) smaller the threshold voltage (Vth) →
junctions are unbiased than the threshold electrons are attracted
→ the transistor voltage (Vth) applied to underneath the gate and an
terminals are the gate → Leads to the inversion layer populated with
connected to zero formation of the electrons is created → the
potential→ no current depletion region channel is formed →
flowing through the underneath the gate → fundamental condition for
device the depletion region is conduction
extended under the gate
The transistor conducts
The transistor is blocked

Systems with Digital Integrated Circuits - The MOS transistor 5

 The nMOS transistor – OFF and ON state

The overdrive voltage is defined as

The linear region
Vod = VGS – Vth

Small positive voltage between the n+
implants (VDS < Vod )→ movement of the
electrons in the channel → current between the Which is the drain and
two terminals which is the source?

A linear dependency of the drain current with
The current flows from drain
VDS is however true only for values of VDS below
VOD. to source

Transistor in triode (linear) region

Systems with Digital Integrated Circuits - The MOS transistor 6

 The nMOS transistor – saturation region
VDS=VOD
VGS>VTh
S D
poly
ox
n n

p-type substrate
pinch-off

VB=0V

The overdrive voltage is defined as

High positive
Vod = VGS – Vth
voltage between the

Small positive voltage between the n+ n+ implants n+ (VDS
implants (VDS < Vod )→ movement of the electrons > Vod ) → the
in the channel → current between the two terminals transistor is in
saturation

Transistor in triode (linear) region

The current flow
Which is the drain and which is the source? nevertheless remains
approximately constant
The current flows from drain to source
with VDS

Systems with Digital Integrated Circuits - The MOS transistor 7

 The nMOS transistor – operation regions

3 operating regions

VGS < Vth → IDS = 0 → blocked

VGS > Vth → VDS < Vod → linear

 VDS 
2
I D = β n ⋅ (VGS − Vth ) ⋅VDS − 
 2 

VDS2/2 is ignored → linear dependency

I D = β n ⋅ (VGS − Vth ) ⋅ VDS

VGS > Vth → VDS > Vod → saturation

βn
⋅ (VGS − Vth )
2
ID =
2
Systems with Digital Integrated Circuits - The MOS transistor 8
 The nMOS transistor – operation regions

Operation region Gate-source Channel present Drain-source Equivalent

voltage voltage large-signal
model

nMOS

cutoff VGS < Vthn no n.a.

linear VGS > Vthn yes VDS < Vod

saturation VGS > Vthn yes VDS > Vod

Systems with Digital Integrated Circuits - The MOS transistor 9

 The MOS transistor – factor β

Factor β → gain factor
Oxide capacitance Cox

εox W W W Cox =
ε ox
β = µ ⋅ ⋅ = µ ⋅ Cox ⋅ = K ⋅
tox L L L tox

W,L – transistor width and length
εox – oxide permittivity

Factor K εox
tox – oxide thickness

K = µ ⋅ Cox = µ ⋅
tox

µ – charge mobility

Charge: nMOS → electrons,
pMOS → holes

For the same W/L

µn > µ p βn > β p

Systems with Digital Integrated Circuits - The MOS transistor 10

 Channel resistance

The transistor ON resistance

In linear region the transistor acts as a resistance

The channel resistance:

VDS 1 L
Ron = = =
I DS β ⋅ (VGS − VT ) µ ⋅ Cox ⋅ W ⋅ (VGS − VT )

For transistors with small resistance and short switching time the width W must be
large.

the above relation is used for resizing transistors in order to improve the delay time

when need a smaller resistance, they have to increase the ratio W/L and considering
values as 2/1, 4/1, 8/1

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 Channel resistance

The resistor

The resistance of a conductive element is given by:

L ρ L
R on = ρ ⋅ = ⋅ = Rs ⋅ L
A t W

ρ [Ω·m] → material resistivity

t [m] → material thickness

L [m] → material length

W [m] → material width

RS [Ω/m]→ (surface) resistance per unit length

Systems with Digital Integrated Circuits - The MOS transistor 12

 Electrical resistances

The surface resistance for various materials in CMOS technology

Material Rs [Ω /m]

Metal 0,03
Diffusion 10 → 50
Polysilicon 15 →100
n channel 104
p channel 2,5⋅104

Systems with Digital Integrated Circuits - The MOS transistor 13

 The enhancement pMOS transistor - operation

pMOS transistor consists of p-type source and drain regions with an n-type body.

In the pMOS transistors the carriers are the holes (positive carriers)

The mobility of holes in silicon is typically lower than that of electrons. This means
that pMOS transistors provide less current than nMOS transistors of comparable size
and hence are slower.
µn = 2 ⋅ µ p βn = 2 ⋅ β p R p = 2 ⋅ RN

The symbols µn and µp are used to distinguish mobility of electrons and of holes in
nMOS and pMOS transistors, respectively.

The mobility ratio µn / µp is typically 2–3;

we will generally use 2 for examples

The symbol for the pMOS transistor
has a bubble on the gate

Systems with Digital Integrated Circuits - The MOS transistor 14

 The enhancement pMOS transistor - operation

pMOS transistors behave in the same way as nMOS,

but with the changed signs of all voltages and currents

The I-V characteristics are in the third quadrant,
as shown in the figure

|VGS| < |Vth| → ID = 0 → blocked

|VGS| > |Vth| → |VDS| < |Vod| → linear

 | VDS |2 
ID = β p ⋅ (| VGS | − | Vth |)⋅ | VDS | − 
 2 

|VDS|2/2 is ignored → linear dependency

βp
ID = ⋅ (| VGS | − | Vth |)2
2

|VGS| > |Vth| → |VDS| > |Vod| → saturation

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 The CMOS technology

CMOS technology uses pairs of n channel (nMOS) and p channel (pMOS)

nMOS transistor is built in the p substrate and for pMOS device a n-well is created
in order to act as a bulk for the p+ difused regions

The transistor dimensions are the dimensions of the conducting channel

The transistor length (L) measures the distance in-between the drain and source
implants where the channel is created, and the transistor width (W) measures the
wideness of the channel.

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 The depletion MOS transistor

An n or p region situated under the gate is doped during the fabrication process →
initial channel

The transistor is ON even VGS = 0. This is necessary in the NMOS technology where
a depletion NMOS transistor is used as a load with the gate and source tied together.

For VGS < Vth (of for pMOS |VGS| < |Vth|) the channel is depleted and the transistor is
blocked

The effect of the initial channel is the translation of the transfer characteristics
towards negative values (or for pMOS towards positive values)

Systems with Digital Integrated Circuits - The MOS transistor 17

 The depletion MOS transistor

The effect of the initial channel is the translation of the transfer characteristics
towards negative values (or for pMOS towards positive values)

ID
nMOS pMOS

Vth

VGS
blocked

depletion
nMOS

depletion
pMOS

Systems with Digital Integrated Circuits - The MOS transistor 18

 Bibliografie

Rabaey J.M., Chandrakasan A., Nikolic B. Digital Integrated Circuits. A design perspective.
Prentice Hall, 2003.

Weste N.H.E, Harris D. CMOS VLSI Design. A Circuits and Systems Perspective. Pearson
Addison Wesley, 2005. http://www3.hmc.edu/~harris/cmosvlsi/4e/

Willy M. C. Sansen – Analog Design Essentials, Springer, 2006

H. Kaeslin, “Digital Integrated Circuit Design From VLSI Architecture to CMOS Fabrication”,
Cambridge University Press, 2008.

Ercegovac, M., Lang T., Moreno J. Introduction to Digital Systems. John Wiley &Sons Inc,
New-York, 1999

Sorin Hintea, Mihaela Cirlugea, Lelia Festila. Circuite Integrate Digitale. Editura UT Press,
Cluj-Napoca, 2005

Sorin Hintea. Tehnici de proiectare a circuitelor digitale VLSI. Casa Cartii de Stiinta. Cluj-
Napoca, 1998

Paul Farago, Botond Kirei, Gabor Csipkes, Sorin Hintea. "Descrierea in VHDL a sistemelor
cu circuite integrate digitale - Indrumator de proiectare si simulare, editura UT Press, Cluj-
Napoca, 2014

Systems with Digital Integrated Circuits - The MOS transistor 19