Phase-Locked Loop

H R Pota
June 6, 2005

1 Introduction
Phase-locked loop (PLL) is a feedback loop which locks two waveforms with same frequency but shifted in phase. The funda-
mental use of this loop is in comparing frequencies of two waveforms and then adjusting the frequency of the waveform in the
loop to equal the input waveform frequency. A block diagram of the PLL is shown in Figure 1. The heart of the PLL is a phase
comparator which along with a voltage controlled oscillator (VCO), a filter and an amplifier forms the loop. If the two frequen-
cies are different the output of the phase comparator varies and changes the input to the VCO to make its output frequency equal
to the input waveform frequency. The locking of the two frequencies is a nonlinear process but linear approximation can be used
to analyse PLL dynamics.
In getting the PLL to lock the proper selection of the filter is essential and it needs some attention. If the filter design is
understood from control theory point-of-view then the design becomes quite simple. In this short note we will discuss only the
fundamentals of the PLL and how you can use nonlinear simulation and linearised approximation to get a better understanding
of the PLL.

Input Phase vp Low-pass volp vo

Amplifier
Detector Filter

R
cos(ω0 t + ko vo dt)
VCO

Figure 1: Basic Phase-Locked Loop

1.1 Multiplier as Phase Comparator

Modern PLLs have digital phase comparator but there are PLLs with analog phase comparators too. They are made up of a simple
multiplier and a low-pass filter. The output of the multiplier is made up of two periodic waveforms—one has the frequency of
the difference of the frequencies of the two input sinusoid and the other wave’s frequency is their sum. The former is obtained
by passing the output of the multiplier through a low-pass filter.
Let the input to the multiplier be vim sin(ωi t) and vom cos(ωo t + φ(t)) then the output voltage vp is

vp = vim sin(ωi t) × vom cos(ωo t + φ(t))

vim vom
= (sin((ωi − ωo )t − φ(t)) + sin((ωi + ωo )t + φ(t))) (1)
2
This output vp is passed through a low-pass filter and if the two frequencies ωi and ωo are close together then the output of the
filter is a function of the phase difference between the two input waveforms given by
vim vom
volp = (sin((ωi − ωo )t − φ(t))) . (2)
2
The output volp is a function of the instantaneous phase difference (ωi t − (ωo t + φ(t))) between the two waveforms.

1.2 The Locking Action

To understand the locking mechanism it’s best to do simulations and plot signals at different points in the loop. The simulation
is discussed in Section 3. Here we give a plausible explanation of how the PLL locks.
Let’s look at the output of the low-pass filter volp (Figure 1) as given by equation (2) and consider that φ(t) = 0 and ωi > ωo .
For a short while this will result in a positive value of volp . This positive value will increase the output frequency of the VCO
bringing ωi and ωo closer. Since the output volp is a sinusoid after its phase value exceeds 180 degrees ((ωi − ωo )t > π) things
will go the wrong way around but since the difference between the two frequencies is lesser it will not pull the two frequencies
as much apart as brought together during the time the phase was less than 180 degrees. This cycle will repeat and in every cycle
the two frequencies will keep coming closer together and finally they will lock. A symmetrical cycle starting with a negative
value for volp will pull the two frequencies together when ωi < ωo .
From equation (2) we see that if ωi is equal to the free running VCO frequency then the output of the low-pass filter should
be zero. This means φ(t) in equation (2) should be zero. What if the output of the VCO is vom sin(ωo t + φ(t)) instead of the
cos function as in equation (2)? Then for the PLL to lock when the input frequency is equal to the free running VCO frequency,
the phase difference φ(t) between the two waves has to be 90 degrees. Why?

2 Linearised PLL
To analyse the behaviour of a PLL we can linearise it about the locking frequency obtained with zero input voltage to the
VCO. This frequency is also known as free running frequency of the VCO. The linear model then only deals with the change in
frequencies about this lock frequency.
The linear approximation to the PLL is shown in Figure 2. The block F (s) in Figure 2 is the low-pass filter to get a signal
proportional to the difference in frequency (and phase) of the two waveforms. Looking from the phase comparator point-of-view,
the output of the multiplier and low-pass filter is a signal equal to the sine of the phase difference between the two input signals.
So our linear approximation is valid only when the phase difference is small.

ωi 1 φi+ vosc
F (s) KD V/rad A
s
−

φo 1 ωo
KO rad/s
V
s

Figure 2: Linear Phase-Locked Loop Block Diagram

To analyse the PLL in Figure 2, let’s write the transfer function

Vosc (s) KD AF (s)

= . (3)
Ωi (s) s + KD AF (s)Ko

For
1
F (s) =
1 + ωsc
Vosc (s) KD A
= . (4)
Ωi (s) s(1 + ωsc ) + KD AKo

2.1 Lock Range

Let the VCO output frequency be ωo for zero input voltage. We need to know what is the range of input signal frequencies for
which the output will lock and this range is called the lock range of the PLL.
To calculate the lock range we need to know the phase difference for which the phase comparator works. Some phase
comparators work for only a 90 degree range and there are others which work for a full 360 degrees. Some PLL schemes do
frequency dividing and thereby enable a comparison over very large phase range. For the digital phase comparator discussed
later, the input phase range is 90 degrees. In this case the lock range is
π
KD AKo .
2
This is the maximum frequency variation that can be had within the loop.

2.2 Filter Design

For a simple low-pass filter F (s), it can be seen that the second-order closed-loop system will have underdamped poles if
KD AKo is large and ω1 small. A quick root-locus sketch should clarify this point. We need large KD AKo for a large lock
range but that makes the system underdamped. One solution is to have a zero in the filter F (s) which damps the system [1], [2],
[3].

2
 For practical reasons of attenuating the out of bandwidth signals, the cut-off frequency of the low-pass filter is kept as low as
possible (this may vary with different applications). A low cut-off and a high KD AKo results in underdamped response which
can be improved by using a compensating network as shown in the simulink implementation next.

3 Simulink Implementation
Now let’s see how PLL can be simulated using simulink. We will compare the nonlinear simulation with linearised approxima-
tion. We first look at a step change in frequency and see how the PLL tracks it and then we look at demodulation of a frequency
modulated signal. We will also use the linearised approximation to design an appropriate filter F (s) to improve PLL perfor-
mance. The design of the filter is a constrained problem because the gain at high frequency needs to be really small otherwise
the sum-frequency signal will pass through and hinder the locking.

3.1 Step Change in Frequency

To see how the PLL locks in, it will help to see some simulations of a simple PLL. In Figure 3 a step change of 10 Hz in
input signal frequency is applied, the output of the nonlinear simulation is seen in Figure 4 and the response for the linearised
approximation as given by equation (3) is shown in Figure 5.

Vout

To Workspace

bf(s)
200
Sine Wave 50k Hz af(s)
Product Filter Gain Scope

1
s
Integrator

2*pi*49990
cos
49990Hz
Trigonometric Product1
Function
0.1
Clock

Figure 3: Simulink Block Diagram of a PLL (Step Change in Frequency)

3.2 Scicos simulation

Scicos is a simulink like simulation application which is a part of the freeware and matlab like package scilab. It’s a wonderful
program, very powerful, easy to install. It comes as a compact 15Mbyte executable file with heaps of help features.
The output of the PLL simulation using the scicos block shown in Figure 6 is the same as the one shown in Figure 4.

3.3 Compensator and Filter Simulation

To improve the performance the following compensator is cascaded with the low-pass filter

s2 /ωn2 + 2ζs/ωn + 1
.
(s/ω1 + 1)(s/ω2 + 1)

The values for the parameters used in both the simulations are given in the matlab script below.
The step response with this comparator is shown in Figure 7 and Figure 8.

Matlab Script
%Fri 27 May 2005
%pll filter design and linear analysis

3
 VCO Input Voltage − (Nonlinear Simulation) VCO Input Voltage (Linear Simulation)
70 80

60 70

60
50

50
Voltage (V)

Voltage (V)
40
40
30
30

20
20

10 10

0 0
0 0.02 0.04 0.06 0.08 0.1 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
Time (s) Time (s)

Figure 4: PLL Output (Non-linear Simulation) Figure 5: PLL Output (Linearised Model)

pll

write to
output file
sinusoid
* num(s)
generator 200 MScope
* den(s)
Product
num(s)
Trig. Function +
cos den(s)
+

*
*

Product 49990

Figure 6: Scicos Block Diagram of a PLL (Step Change in Frequency)

4
 VCO Input Voltage − (Nonlinear Simulation) VCO Input Voltage (Linear Simulation)
70 80

60 70

60
50

50
Voltage (V)

Voltage (V)
40
40
30
30

20
20

10 10

0 0
0 0.02 0.04 0.06 0.08 0.1 0 0.02 0.04 0.06 0.08 0.1
Time (s) Time (s)

Figure 7: PLL Output with Compensator (Non-linear) Figure 8: PLL Output with Compensator (Linearised)

%run it before NoClockpll but make sure af and bf are what’s needed.
%the simulink file is NoClockpll
ko=200;
[bf,af]=butter(1,2*pi*20,’s’);
for 1 > 2
w1=2*pi*30; w2=2*pi*40;
wn=2*pi*10; zeta=0.99;
af=conv(af,conv([1/w1 1],[1/w2 1]));
bf=conv(bf,[1/wnˆ2 2*zeta/wn 1]);
end;
figure(1); rlocus(bf,[af 0]);
figure(1);step(ko*bf,[[af 0] + ko*[0 bf]]);
xlabel(’Time’); ylabel(’Voltage (V)’);
title(’VCO Input Voltage (Linear Simulation)’);
figure(2);rlocus(bf,[af 0])

%code to plot the output from NoClockpll

if 1 > 2
figure(3);plot(Vout.time,Vout.signals.values);grid;
xlabel(’Time (s)’); ylabel(’Voltage (V)’);
title(’VCO Input Voltage (Nonlinear Simulation’);
end

3.4 FM Demodulation
Demodulation of FM signals can be done using PLLs. A simulink block diagram to demodulate FM signals is shown in Figure 9.
In [1, p. 165] it says:
The distinction between PM (phase modulation) and FM (frequency modulation) is artificial; both might be
termed angle modulation and treated in a unified manner. In this chapter, the term “PM” implies small phase
deviation, with a remanent carrier present, whereas “FM” has no such implications. The distinction is more apparent
in the modulator and demodulator configurations than in the signals themselves.

The parameters for simulation are: input waveform has a frequency of sin(2π10000t + sin(2π100t)) (the carrier frequency
is 10000 Hz, the modulating signal is sin(2π100t); the free oscillating frequency of the VCO is 10000 Hz.
From the block diagram in Figure 2 the transfer function between the input phase φi and output phase φo is

Φo (s) KD AKo
= . (5)
Φi (s) s(1 + ωs1 ) + KD AKo

Parameters for this simulation are: KD A = 1 and Ko = 500.

5
 Sine Wave 100 Hz

2*pi*f0
sin
10000Hz
Trigonometric Product3
Function1 0.1
Clock1

bf(s)
ko
af(s)
Product Low−Pass Filter Gain Scope

1
Vout
s
To Workspace Integrator

2*pi*f0

10000Hz1
Product2

cos 0.1

Trigonometric Clock2
Function

Figure 9: Simulink Block Diagram of a PLL (Frequency Modulation)

Narrowband Loop filter

The first simulation is done for a sinusoidal phase modulating signal sin(2π100t) with a first-order filter with cut-off frequency
at 10 Hz. The output phase for nonlinear and linearised simulation is shown in Figures 10 and Figures 11. From the transfer
function in (5) the steady-state gain for the sinusoidal input at 100 Hz can be calculated by substituting s = 2π100 and
ωi = 2π10 which gives a gain of 0.08, about twice the gain seen in Figure 10. The linear approximation near the resonance
frequency is not very accurate. In nonlinear system the damping is more than in linearised approximation. But still a good idea
of the bandwidth, etc., can be obtained from the linear approximation. The step-response of the linearised PLL shows that there
are oscillations and the settling time is about 0.1 s, this can also be seen in the nonlinear simulation in Figure 10.

%Fri 27 May 2005

%pll filter design and linear analysis
%run it before pll simulink run but make sure af and bf are what’s needed.
%the simulink file is pll
%Frequency Modulating signal is sin(2*pi*100 t)
%
ko=500; f0=10000;
[bf,af]=butter(1,2*pi*10,’s’);
clsys=tf(ko*bf,[[af 0] + ko*[0 bf]]);
[ystep,tstep]=step(clsys);
figure(1);plot(tstep,ystep); grid on;
xlabel(’Time (s)’); ylabel(’Voltage (V)’);
title(’VCO Input Voltage (Linear Simulation)’);
figure(2);rlocus(bf,[af 0])
figure(4);bode(clsys);

%code to plot the output from pll

if 1 > 2
%figure(3);plot(Vout.time,Vout.signals.values);grid;
figure(3);plot(Vout.time(1:1:end),Vout.signals.values(1:1:end));grid;
xlabel(’Time (s)’); ylabel(’Voltage (V)’);
title(’VCO Input Voltage - Narrow Band (Nonlinear Simulation)’);
end

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 VCO Input Voltage − (Nonlinear Simulation) VCO Input Voltage (Linear Simulation)
0.25 1.6

0.2 1.4

1.2
0.15

1
Voltage (V)

Voltage (V)
0.1
0.8
0.05
0.6

0
0.4

−0.05 0.2

−0.1 0
0 0.05 0.1 0.15 0.2 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18
Time (s) Time (s)

Figure 10: Frequency Modulation (Non-linear) Figure 11: Frequency Modulation (Linearised)

VCO Input Voltage − (Nonlinear Simulation) VCO Input Voltage (Linear Simulation)
1.5 1.5

0.5 1
Voltage (V)

Voltage (V)

−0.5 0.5

−1

−1.5 0
0 0.02 0.04 0.06 0.08 0.1 0 1 2 3 4 5 6 7 8 9
Time (s) Time (s) −3
x 10

Figure 12: Frequency Modulation - Broadband (Nonlinear) Figure 13: Frequency Modulation - Broadband (Linearised)

Broadband Loop filter

The next simulation is done for the same sinusoidal phase modulating signal sin(2π100t) but with a first-order filter with cut-off
frequency at 200 Hz and Ko = 5000. This makes the loop bandwidth larger than the pervious example. The output phase for
nonlinear and linearised simulation is shown in Figures 12 and Figures 13. From the transfer function in (5) the steady-state gain
for the sinusoidal input at 100 Hz can be calculated by substituting s = 2π100 and ωi = 2π200 which gives a gain of 1.57,
close to the gain seen in Figure 10. The step-response of the linearised PLL shows that there are oscillations and the settling time
is about 0.1 s, this can also be seen in the nonlinear simulation in Figure 10.

4 Frequency Synthesis
There are several applications which need sinusoids of a precise frequency; radio and television broadcast systems and mobile
telephones being the most visible applications. The devices which output sinusoid at a preset frequency, from within a range of
frequencies, is called a frequency synthesiser. In this section we discuss a simple frequency synthesiser using the phase-locked
loop concepts.
In most frequency synthesisers, a square wave of the desired frequency is input and a sinusoid of that frequency is synthesised
at the output. It is well-known that feedback is one of the most important techniques of making the system output follow
a reference input. Here the interest is in making frequencies of the two waveforms identical. Instantaneous comparison of
the frequencies of two waveforms is not possible—frequency can only be measured after one time-period. To overcome this
limitation a scheme shown in Figure 14 is used. The method is quite simple. The reference square wave and the inverted signum

7
of the output sinusoid are multiplied and then averaged. Although these two operations are hard to perform in hardware but
there do exist circuits which can perform these operations close to the ideal. It is shown below that the output of the averager is
positive if the reference signal frequency is higher than the output sinusoid and vice-versa. This increases or decreases the VCO
input and accordingly adjusts the output sinusoid frequency. To generate the required input to the VCO, the input reference and
the fedback voltage are locked with a fixed phase difference hence the name phase-locked loop.

vr
va vosc
× Averager VCO

vo

Inverter signum

Figure 14: Phase-Locked Loop

Figure 15 shows the transfer functions for the equivalent blocks in Figure 14.

vr KD va R vosc
× A cos(ω0 t + k0 va dt)
s
VCO

vo

Inverter signum

Figure 15: Phase-Locked Loop (Analytically speaking)

4.1 Phase Comparator

The operation of phase comparator when the frequencies of the output and input signals are the same can be understood from
Figure 16. The output of the multiplier is a waveform twice the frequency of the input signal and odd. This wave is fed to an
averager whose output is zero. This equilibrium state holds till the input signal or the output frequency changes.

vr vo
1
| | | | | | | t

−1

vr × −vo
1
A1 A3
| | | | | | | t
A2 A4
−1

Figure 16: 90 Degrees Out of Phase

4.2 Frequency Tracking and Phase Lock

When the frequency of the input signal is greater than the output, the two waveforms and the output of the multiplier is shown
in Figure 17. From the output of the multiplier it can be seen that the output of the averager will be positive because the areas

8
above the horizontal axis are larger than the areas below. This increase in the input to the voltage controlled oscillator incrases
the output frequency and this continues till the two frequencies are equal.

vr vo
1
| | | | | | | t

−1

vr × −vo
1
A1 A3
| | | | | | | t
A2 A4
−1

Figure 17: Decrease in the Frequency of the Output Signal

When the output frequency is greater than the input signal frequency, the waveforms are as shown in the Figure 18. From the
figure we can see that the input to the VCO decreases and this decreases the output frequency.

vr vo
1
| | | | | | | t

−1

vr × −vo
1
A1 A3
| | | | | | | t
A2 A4
−1

Figure 18: Increase in the Frequency of the Output Signal

5 Links
All the scripts mentioned in the article are linked from:
http://www.ee.adfa.edu.au/staff/hrp/teaching/Electronics4/docs/PLL/index.html

References
[1] Floyd M. Gardner. Phaselock Techniques. John Wiley & sons, Brisbane, 2nd edition, 1979.
[2] Paul R. Gray and Robert G. Meyer. Analysis and Design of Analog Integrated Circuits. John Wiley and Sons, Brisbane, 3rd
edition, 1993.
[3] Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, and Robert G. Meyer. Analysis and Design of Analog Integrated Circuits.
John Wiley and Sons, Brisbane, 4th edition, 2001. ISBN: 0-471-32168-0.