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AMC1301, AMC1301S
SBAS667E – APRIL 2016 – REVISED MARCH 2018
3.3 V or AMC1301
Gate 5.0 V
Driver VDD1 VDD2 3.3 V or 5.0 V
Reinforced Isolation
GND1 GND2
Gate
Driver
HV-
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AMC1301, AMC1301S
SBAS667E – APRIL 2016 – REVISED MARCH 2018 www.ti.com
Table of Contents
1 Features .................................................................. 1 9.1 Overview ................................................................. 18
2 Applications ........................................................... 1 9.2 Functional Block Diagram ....................................... 18
3 Description ............................................................. 1 9.3 Feature Description................................................. 18
9.4 Device Functional Modes........................................ 19
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 4 10 Application and Implementation........................ 20
10.1 Application Information.......................................... 20
6 Pin Configuration and Functions ......................... 4
10.2 Typical Applications .............................................. 20
7 Specifications......................................................... 5
10.3 Do's and Don'ts .................................................... 24
7.1 Absolute Maximum Ratings ...................................... 5
11 Power Supply Recommendations ..................... 25
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5 12 Layout................................................................... 26
12.1 Layout Guidelines ................................................. 26
7.4 Thermal Information .................................................. 5
12.2 Layout Example .................................................... 26
7.5 Power Ratings........................................................... 5
7.6 Insulation Specifications............................................ 6 13 Device and Documentation Support ................. 27
7.7 Safety-Related Certifications..................................... 7 13.1 Documentation Support ....................................... 27
7.8 Safety Limiting Values .............................................. 7 13.2 Related Links ........................................................ 27
7.9 Electrical Characteristics........................................... 7 13.3 Receiving Notification of Documentation Updates 27
7.10 Insulation Characteristics Curves .......................... 9 13.4 Community Resources.......................................... 27
7.11 Typical Characteristics .......................................... 10 13.5 Trademarks ........................................................... 27
13.6 Electrostatic Discharge Caution ............................ 27
8 Parameter Measurement Information ................ 17
13.7 Glossary ................................................................ 27
8.1 Timing Diagrams ..................................................... 17
9 Detailed Description ............................................ 18 14 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Changed VDD1 to VDD2 in test conditions of IDD2 and PDD2 parameters of Electrical Characteristics table ........................ 8
• Changed VDD2 to VDD1 in conditions of Gain Error Histogram figures ............................................................................. 12
• Changed Features bullet from "Safety and Regulatory Approvals" to "Safety-Related Certifications" .................................. 1
• Changed Simplified Schematic figure in Device Information table......................................................................................... 1
• Changed section title from "Regulatory Information" to "Safety-Related Certifications" ....................................................... 7
• Changed VCM test conditions in Electrical Characteristics table............................................................................................. 7
• Added VIN footnote to Electrical Characteristics table ........................................................................................................... 7
• Changed VIN test conditions in Electrical Characteristics table .............................................................................................. 7
• Changed VIN units in Electrical Characteristics table ............................................................................................................. 7
• Changed common-mode rejection ratio test condition in Electrical Characteristics table...................................................... 7
• Changed RIN parameter information in Electrical Characteristics table.................................................................................. 7
• Changed output noise equation in Electrical Characteristics table ........................................................................................ 8
• Deleted "Safety and" from Insulation Characteristics Curves section title ............................................................................ 9
• Changed Using the AMC1301 for Current Sensing in Frequency Inverters figure in Application Information..................... 20
• Changed Zener-Diode Based, High Side Power Supply figure in Power Supply Recommendations ................................. 25
• Added a paragraph and changed the formatting of the Related Documentation section ................................................... 27
DWV Package
8-Pin SOIC
Top View
VDD1 1 8 VDD2
VINP 2 7 VOUTP
VINN 3 6 VOUTN
GND1 4 5 GND2
Not to scale
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
GND1 4 — High-side analog ground
GND2 5 — Low-side analog ground
High-side power supply, 3.0 V to 5.5 V.
VDD1 1 —
See the Power Supply Recommendations section for decoupling recommendations.
Low-side power supply, 3.0 V to 5.5 V.
VDD2 8 —
See the Power Supply Recommendations section for decoupling recommendations.
VINN 3 I Inverting analog input
VINP 2 I Noninverting analog input
VOUTN 6 O Inverting analog output
VOUTP 7 O Noninverting analog output
7 Specifications
7.1 Absolute Maximum Ratings (1)
MIN MAX UNIT
Supply voltage, VDD1 to GND1 or VDD2 to GND2 –0.3 7 V
Analog input voltage at VINP, VINN GND1 – 6 VDD1 + 0.5 V
Input current to any pin except supply pins –10 10 mA
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed
circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as
inserting grooves and ribs on the PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier are tied together, creating a two-pin device.
(1) Input, output, or the sum of input and output power must not exceed this value.
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that
of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
(1) Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage VCM for normal
operation. Observe analog input voltage range as specified in Absolute Maximum Ratings.
Copyright © 2016–2018, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: AMC1301
AMC1301, AMC1301S
SBAS667E – APRIL 2016 – REVISED MARCH 2018 www.ti.com
500 1300
VDD1 = VDD2 = 3.6 V 1200
VDD1 = VDD2 = 5.5 V
1100
400
1000
900
300 800
PS (mW)
IS (mA)
700
600
200 500
400
300
100
200
100
0 0
0 50 100 150 200 0 50 100 150 200
TA (°C) D043
TA (°C) D044
Figure 1. Thermal Derating Curve for Safety-Limiting Figure 2. Thermal Derating Curve for Safety-Limiting
Current per VDE Power per VDE
3.8 3.8
3.4 3.4
3 3
VCMov (V)
VCMov (V)
2.6 2.6
2.2 2.2
1.8 1.8
1.4 1.4
1 1
3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125
VDD1 (V) D001
Temperature (°C) D002
–55°C ≤ TA < 40°C valid for the AMC1301S only
Figure 4. Common-Mode Overvoltage Detection Level Figure 5. Common-Mode Overvoltage Detection Level
vs High-Side Supply Voltage vs Temperature
50 50
40 40
Devices (%)
Devices (%)
30 30
20 20
10 10
0 0
-200
-175
-150
-125
-100
-200
-175
-150
-125
-100
-75
-50
-25
25
50
75
100
125
150
175
200
-75
-50
-25
25
50
75
100
125
150
175
200
0
D003 D004
VOS (PV) VOS (PV)
VDD1 = 3.3 V VDD1 = 5 V
Figure 6. Input Offset Voltage Histogram Figure 7. Input Offset Voltage Histogram
200 200
vs VDD1
150 vs VDD2 150
100 100
50 50
VOS (PV)
VOS (PV)
0 0
-50 -50
-100 -100
Device 1
-150 -150 Device 2
Device 3
-200 -200
3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125
VDDx (V) D005
Temperature (°C) D006
–55°C ≤ TA < 40°C valid for the AMC1301S only
Figure 8. Input Offset Voltage vs Supply Voltage Figure 9. Input Offset Voltage vs Temperature
60 60
50 50
Devices (%)
Devices (%)
40 40
30 30
20 20
10 10
0 0
0.5
1.5
2.5
-3
-2.5
-2
-1.5
-1
-0.5
0.5
1.5
2.5
-3
-2.5
-2
-1.5
-1
-0.5
3
D007 D008
TCVOS (PV/qC) TCVOS (PV/qC)
VDD1 = 3.3 V VDD1 = 5 V
Figure 10. Input Offset Drift Histogram Figure 11. Input Offset Drift Histogram
0 -60
-65
-20
-70
-75
-40
CMRR (dB)
CMRR (dB)
-80
-60 -85
-90
-80
-95
-100
-100
-105
-120 -110
0.001 0.01 0.1 0.5 2 3 5 10 20 100 1000 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125
fIN (kHz) D009
Temperature (°C) D011
–55°C ≤ TA < 40°C valid for the AMC1301S only
Figure 12. Common-Mode Rejection Ratio Figure 13. Common-Mode Rejection Ratio
vs Input Frequency vs Temperature
60 -23
-25
40
-27
20
-29
0
IIB (PA)
IIB (PA)
-31
-20 -33
-35
-40
-37
-60
-39
-80 -41
-0.5 0 0.5 1 1.5 2 2.5 3 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
VCM (V) D012
VDD1 (V) D013
Figure 14. Input Bias Current Figure 15. Input Bias Current
vs Common-Mode Input Voltage vs High-Side Supply Voltage
-31
-40
-33
-50
-35
-60
-37
-39 -70
-41 -80
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125 0.01 0.1 1 10 100 1000
Temperature (°C) Input Signal Frequency (kHz) D015
D014
–55°C ≤ TA < 40°C valid for the AMC1301S only
Figure 16. Input Bias Current vs Temperature Figure 17. Normalized Gain vs Input Frequency
50 50
40
Devices (%) 40
Devices (%)
30 30
20 20
10 10
0 0
0.05
0.15
0.25
0.1
0.2
0.3
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
0
0.05
0.15
0.25
0.1
0.2
0.3
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
D016 D017
EG (%) EG (%)
VDD1 = 3.3 V VDD1 = 5 V
Figure 18. Gain Error Histogram Figure 19. Gain Error Histogram
0.3 0.3
0.25 vs VDD1 0.25 Device 1
vs VDD2 Device 2
0.2 0.2 Device 3
0.15 0.15
0.1 0.1
0.05 0.05
EG (%)
EG (%)
0 0
-0.05 -0.05
-0.1 -0.1
-0.15 -0.15
-0.2 -0.2
-0.25 -0.25
-0.3 -0.3
3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125
VDDx (V) D018
Temperature (°C) D019
–55°C ≤ TA < 40°C valid for the AMC1301S only
Figure 20. Gain Error vs Supply Voltage Figure 21. Gain Error vs Temperature
80 80
70 70
60 60
Devices (%)
Devices (%)
50 50
40 40
30 30
20 20
10 10
0 0
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
10
15
20
25
30
35
40
45
50
0
5
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
10
15
20
25
30
35
40
45
50
0
5
D020 D021
TCEG (ppm/qC) TCEG (ppm/qC)
VDD1 = 3.3 V VDD1 = 5 V
Figure 22. Gain Error Drift Histogram Figure 23. Gain Error Drift Histogram
5 0.03
VOUTN 0.025
4.5 VOUTP
0.02
4
0.015
3.5
0.01
Nonlinearity (%)
3 0.005
VOUT (V)
2.5 0
2 -0.005
-0.01
1.5
-0.015
1
-0.02
0.5 -0.025
0 -0.03
-350 -250 -150 -50 50 150 250 350 -250 -200 -150 -100 -50 0 50 100 150 200 250
Differential Input Voltage (mV) D022
Differential Input Voltage (mV) D024
Figure 24. Output Voltage vs Input Voltage Figure 25. Nonlinearity vs Input Voltage
0.03 0.03
0.025 vs VDD1 0.025
vs VDD2
0.02 0.02
0.015 0.015
0.01 0.01
Nonlinearity (%)
Nonlinearity (%)
0.005 0.005
0 0
-0.005 -0.005
-0.01 -0.01
-0.015 -0.015
-0.02 -0.02 Device 1
Device 2
-0.025 -0.025 Device 3
-0.03 -0.03
3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125
VDDx (V) D025
Temperature (°C) D026
–55°C ≤ TA < 40°C valid for the AMC1301S only
THD (dB)
THD (dB)
-85 -85
-90 -90
-95 -95
-100 -100 Device 1
-105 -105 Device 2
Device 3
-110 -110
3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125
VDDx (V) D027
Temperature (°C) D028
–55°C ≤ TA < 40°C valid for the AMC1301S only
Figure 28. Total Harmonic Distortion vs Supply Voltage Figure 29. Total Harmonic Distortion vs Temperature
80 80
vs VDD1
75 77.5 vs VDD2
70 75
65 72.5
SNR (dB)
SNR (dB)
60 70
55 67.5
50 65
45 62.5
40 60
0 50 100 150 200 250 300 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
|VINP - VINN| (mV) D029
VDDx (V) D030
Figure 30. Signal-to-Noise Ratio vs Input Voltage Figure 31. Signal-to-Noise Ratio vs Supply Voltage
80 10000
Input Referred Noise Density (nV/—Hz)
77.5
75
1000
72.5
SNR (dB)
70
67.5
100
65
Device 1
62.5 Device 2
Device 3
60 10
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125 0.01 0.1 1 10 100 1000
Temperature (°C) D031
Frequency (kHz) D032
–55°C ≤ TA < 40°C valid for the AMC1301S only
Figure 32. Signal-to-Noise Ratio vs Temperature Figure 33. Input-Referred Noise Density vs Frequency
-20 -20
-40 -40
PSRR (dB)
PSRR (dB)
-60 -60
-80 -80
-100 -100
-120 -120
0.001 0.01 0.1 1 10 100 1000 0.001 0.01 0.1 1 10 100 1000
Ripple Frequency (kHz) D033
Ripple Frequency (kHz) D042
vs VDD1 vs VDD2
Figure 34. Power-Supply Rejection Ratio Figure 35. Power-Supply Rejection Ratio
vs Ripple Frequency vs Ripple Frequency
4 3.8
50% - 10%
3.5 3.4 50% - 50%
50% - 90%
3 3
Rise/Fall Time (Ps)
2.6
2.5
2.2
2
1.8
1.5
1.4
1
1
0.5 0.6
0 0.2
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
Temperature (°C) D034
VDD2 (V) D035
–55°C ≤ TA < 40°C valid for the AMC1301S only
Figure 36. Output Rise and Fall Time vs Temperature Figure 37. VIN to VOUT Signal Delay
vs Low-Side Supply Voltage
3.8 1.49
50% - 10%
3.4 50% - 50% 1.48
Output Common-Mode Voltage (V)
2.6
1.45
2.2
1.44
1.8
1.43
1.4
1.42
1 1.41
0.6 1.4
0.2 1.39
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
Temperature (°C) D036
VDD2 (V) D010
–55°C ≤ TA < 40°C valid for the AMC1301S only
Figure 38. VIN to VOUT Signal Delay vs Temperature Figure 39. Output Common-Mode Voltage
vs Low-Side Supply Voltage
BW (kHz)
1.44 200
1.43
1.42
180
1.41
1.4
1.39 160
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
Temperature (°C) D037
VDD2 (V) D038
–55°C ≤ TA < 40°C valid for the AMC1301S only
Figure 40. Output Common-Mode Voltage vs Temperature Figure 41. Output Bandwidth vs Low-Side Supply Voltage
190 8.5
IDD1 vs VDD1
8 IDD2 vs VDD2
200
7.5
7
210
6.5
BW (kHz)
IDDx (mA)
220 6
5.5
230
5
4.5
240
4
250 3.5
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
Temperature (°C) D039
VDDx (V) D040
–55°C ≤ TA < 40°C valid for the AMC1301S only
Figure 42. Output Bandwidth vs Temperature Figure 43. Supply Current vs Supply Voltage
8.5
IDD1
8 IDD2
7.5
7
6.5
IDDx (mA)
6
5.5
5
4.5
4
3.5
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C) D041
–55°C ≤ TA < 40°C valid for the AMC1301S only
VINP - VINN
0V
VOUTN
90%
10%
VOUTP
tr tf
0.5 V
0V
50% - 10%
VOUTN
90%
50%
10%
VOUTP
9 Detailed Description
9.1 Overview
The AMC1301 is a fully-differential, precision, isolated amplifier. The input stage of the device consists of a fully-
differential amplifier that drives a second-order, delta-sigma (ΔΣ) modulator. The modulator uses the internal
voltage reference and clock generator to convert the analog input signal to a digital bitstream. The drivers (called
TX in the Functional Block Diagram) transfer the output of the modulator across the isolation barrier that
separates the high-side and low-side voltage domains. The received bitstream and clock are synchronized and
processed by a fourth-order analog filter on the low-side and presented as a differential output of the device, as
shown in the Functional Block Diagram.
The SiO2-based, double-capacitive isolation barrier supports a high level of magnetic field immunity, as described
in ISO72x Digital Isolator Magnetic-Field Immunity. The digital modulation used in the AMC1301 and the isolation
barrier characteristics result in high reliability and common-mode transient immunity.
VDD1 VDD2
AMC1301 Isolation
Band-Gap Barrier Band-Gap
Reference Reference
VINP VOUTP
Retiming and
+ Data 4th-Order
û -Modulator TX RX Active
± Low-Pass
Filter
VINN VOUTN
CLK
RX TX Oscillator
GND1 GND2
Figure 47. Typical Negative Clipping Output of the Figure 48. Typical Failsafe Output of the AMC1301
AMC1301
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
R1 AMC1301
Gate Driver
5.1 V
VDD1 VDD2 3.3 V
Reinforced Isolation
C1 C2 C4 C5
D1 10 F 0.1 F 0.1 F 2.2 F TMS320
GND1 GND2 C/F28x
RSHUNT
R2
To Load VINN VOUTP
C3 ADC
VINP VOUTN
R3
Gate Driver
HV-
Figure 49. Using the AMC1301 for Current Sensing in Frequency Inverters
VIN
VOUTP
VOUTN
The high linearity and low temperature drift of offset and gain errors of the AMC1301, as shown in Figure 51,
allows design of motor drives with low torque ripple.
0.03
0.025
0.02
0.015
0.01
Nonlinearity (%)
0.005
0
-0.005
-0.01
-0.015
-0.02
-0.025
-0.03
-250 -200 -150 -100 -50 0 50 100 150 200 250
Differential Input Voltage (mV) D024
3.3 V
or 5 V
R1
R2
R4 R5
VINP
IIB
+
R3 RIN û -Modulator
±
VINN
GND1
VCM = 2 V
60
40
20
IIB (PA) 0
-20
-40
-60
-80
-0.5 0 0.5 1 1.5 2 2.5 3
VCM (V) D012
R1 AMC1301
Gate Driver 800
5.1 V 3.3 V or
VDD1 VDD2
5.0 V
Reinforced Isolation
Z1 C1 C2 C4 C5
1N751A 10 F 0.1 F 0.1 F 2.2 F
GND1 GND2
RSHUNT
To Load VINN VOUTP
ADS7263
14-Bit ADC
VINP VOUTN
Gate Driver
HV-
12 Layout
VINP VOUTP
To Filter
AMC1301
or ADC
VINN VOUTN
GND1 GND2
LEGEND
Copper Pour and Traces
High-Side Area
Low-Side Area
Via to Ground Plane
Via to Supply Plane
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 22-Mar-2018
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
AMC1301DWV ACTIVE SOIC DWV 8 64 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 AMC1301
& no Sb/Br)
AMC1301DWVR ACTIVE SOIC DWV 8 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 AMC1301
& no Sb/Br)
AMC1301SDWV ACTIVE SOIC DWV 8 64 Green (RoHS CU NIPDAU Level-3-260C-168 HR -55 to 125 AMC1301S
& no Sb/Br)
AMC1301SDWVR ACTIVE SOIC DWV 8 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -55 to 125 AMC1301S
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
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of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 22-Mar-2018
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• Automotive: AMC1301-Q1
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Feb-2019
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Feb-2019
Pack Materials-Page 2
PACKAGE OUTLINE
SEATING PLANE
11.5 0.25
PIN 1 ID TYP 0.1 C
AREA
6X 1.27
8
1
5.95 2X
5.75 3.81
NOTE 3
4
5
0.51
8X
0.31
7.6 0.25 C A B
A B 2.8 MAX
7.4
NOTE 4
0.33
TYP
0.13
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0.46
0.36
0 -8
1.0
0.5 DETAIL A
(2) TYPICAL
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
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EXAMPLE BOARD LAYOUT
8X (0.6) SYMM
6X (1.27)
(10.9)
4218796/A 09/2013
NOTES: (continued)
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EXAMPLE STENCIL DESIGN
8X (1.8) SYMM
8X (0.6)
SYMM
6X (1.27)
(10.9)
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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