1.Design of BCD to 7 Segment Display Decoder Circuit.

The designing of BCD to seven segment display decoder circuit mainly involves four steps namely
analysis, truth table design, K-map and designing a combinational logic circuit using logic gates.
The first step of this circuit design is an analysis of the common cathode seven segment display. This
display can be constructed with seven LEDs in the form of H. A truth table of this circuit can be designed
by the inputs combinations for every decimal digit. For instance, decimal number ‘1’ would control a
blend of b & c.

The second step is the truth table design by listing the display input signals-7, equivalent four-digit
binary numbers as well as decimal number.
The designing of the truth table for the decoder mainly depends on the kind of display. Already we have
discussed above that is, for a common cathode display, the decoder output must be high in order to
blink the segment.

The tabular form of a BCD to 7-segment decoder with a common cathode display is shown below. The
truth table consists of seven o/p columns equivalent to each of the seven segments. For example, the
column for a-segment illustrates the various arrangements for which it is to be light up. Thus ‘a’-
segment is energetic for the digits like 0, 2, 3, 5, 6, 7, 8 & 9.

X Y Z W a b c d e f g
Digit
1
0 0 0 0 0 0 0 0 0 0 0

1
0 0 0 1 1 0 0 1 1 1 1

0
2 0 0 1 0 0 0 1 0 0 1

3
0 0 1 1 0 0 0 0 1 1 0

0
4 0 1 0 0 1 0 0 1 1 0

5
0 1 0 1 0 1 0 0 1 0 0

0
6 0 1 1 0 0 1 0 0 0 0

7
0 1 1 1 0 0 0 1 1 1 1

0
8 1 0 0 0 0 0 0 0 0 0
 0
9 1 0 0 1 0 0 0 0 1 0

By using the above truth table, for every output function, the Boolean expression can be written.

a = F1 (X, Y, Z, W) = ∑m (0, 2, 3, 5, 7, 8, 9)

b = F2 (X, Y, Z, W) = ∑m (0, 1, 2, 3, 4, 7, 8, 9)

c = F3 (X, Y, Z, W) = ∑m (0, 1, 3, 4, 5, 6, 7, 8, 9)

d = F4 (X, Y, Z, W) = ∑m (0, 2, 3, 5, 6, 8)
e = F5 (X, Y, Z, W) = ∑m (0, 2, 6, 8)

f = F6 (X, Y, Z, W) = ∑m (0, 4, 5, 6, 8, 9)

g = F7 (X, Y, Z, W) = ∑m (2, 3, 4, 5, 6, 8, 9)
The third step in this design mainly involves designing the K-map (Karnaugh’s map) for every output
expression as well as then shortening them to get inputs logic combination for every output.
Simplification of Karnaugh -Map
The simplification of k-map of the common cathode 7 segment decoder can be done in order to plan the
combinational circuit. From the above K-map simplification, we can get the output equations like these

a = X+Z+YW+Y’W’
b = Y’+Z’W’+ZW
c= Y+Z’+W
d = Y’W’+ZW’+YZ’W+Y’Z+X
e= Y’W’+ZW’
f= X + Z’W’+YZ’+YW’
g = X+YZ’+Y’Z+ZW’
The final step of this is a designing of a logic circuit using the above k-map equations. A combinational
circuit can be built by using 4-inputs namely A, B, C, D and outputs on display like a, b, c, d, e, f, g. The
operation of the above logic circuit can be understood with the help of truth table only. Once all the i/ps
are connected to small logic.
 BCD to Seven
Segment Decoder Circuit

Then the combinational logic circuit’s output will drive each and every one of output LEDs apart from
‘g’ to transmission. Therefore the number ‘0’ will be exhibited. Similarly, for all another grouping of the
input switches, the same process would take place.

Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’ selection lines
and single output line. One of these data inputs will be connected to the output based on
the values of selection lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and ones.
So, each combination will select only one data input. Multiplexer is also called as Mux.
4x1 Multiplexer
4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output
Y. The block diagram of 4x1 Multiplexer is shown in the following figure.
One of these 4 inputs will be connected to the output based on the combination of inputs
present at these two selection lines. Truth table of 4x1 Multiplexer is shown below.

Selection Lines Output

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

From Truth table, we can directly write the Boolean function for output, Y as
$$Y={S_{1}}'{S_{0}}'I_{0}+{S_{1}}'S_{0}I_{1}+S_{1}{S_{0}}'I_{2}+S_{1}S_{0}I_{3}$$
We can implement this Boolean function using Inverters , AND gates & OR gate. The circuit
diagram of 4x1 multiplexer is shown in the following figure.
We can easily understand the operation of the above circuit. Similarly, you can implement
8x1 Multiplexer and 16x1 multiplexer by following the same procedure.
Implementation of Higher-order Multiplexers.
Now, let us implement the following two higher-order Multiplexers using lower-order
Multiplexers.

 8x1 Multiplexer
 16x1 Multiplexer
8x1 Multiplexer
In this section, let us implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1 Multiplexer.
We know that 4x1 Multiplexer has 4 data inputs, 2 selection lines and one output. Whereas,
8x1 Multiplexer has 8 data inputs, 3 selection lines and one output.
So, we require two 4x1 Multiplexers in first stage in order to get the 8 data inputs. Since,
each 4x1 Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by
considering the outputs of first stage as inputs and to produce the final output.
Let the 8x1 Multiplexer has eight data inputs I7 to I0, three selection lines s2, s1 & s0 and
one output Y. The Truth table of 8x1 Multiplexer is shown below.

Selection Inputs Output

S2 S1 S0 Y

0 0 0 I0
 0 0 1 I1

0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 I7

We can implement 8x1 Multiplexer using lower order Multiplexers easily by considering the
above Truth table. The block diagram of 8x1 Multiplexer is shown in the following figure.

The same selection lines, s1 & s0 are applied to both 4x1 Multiplexers. The data inputs of
upper 4x1 Multiplexer are I7 to I4 and the data inputs of lower 4x1 Multiplexer are I3 to I0.
Therefore, each 4x1 Multiplexer produces an output based on the values of selection lines,
s1 & s0.
The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is
present in second stage. The other selection line, s2 is applied to 2x1 Multiplexer.

* If s2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs I3 to
I0 based on the values of selection lines s1 & s0.
 * If s2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I7 to
I4 based on the values of selection lines s1 & s0.

Therefore, the overall combination of two 4x1 Multiplexers and one 2x1 Multiplexer
performs as one 8x1 Multiplexer.
16x1 Multiplexer
In this section, let us implement 16x1 Multiplexer using 8x1 Multiplexers and 2x1
Multiplexer. We know that 8x1 Multiplexer has 8 data inputs, 3 selection lines and one
output. Whereas, 16x1 Multiplexer has 16 data inputs, 4 selection lines and one output.
So, we require two 8x1 Multiplexers in first stage in order to get the 16 data inputs. Since,
each 8x1 Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by
considering the outputs of first stage as inputs and to produce the final output.
Let the 16x1 Multiplexer has sixteen data inputs I15 to I0, four selection lines s3 to s0 and
one output Y. The Truth table of 16x1 Multiplexer is shown below.

Selection Inputs Output

S3 S2 S1 S0 Y

0 0 0 0 I0

0 0 0 1 I1

0 0 1 0 I2

0 0 1 1 I3

0 1 0 0 I4

0 1 0 1 I5

0 1 1 0 I6

0 1 1 1 I7

1 0 0 0 I8

1 0 0 1 I9

1 0 1 0 I10

1 0 1 1 I11
 1 1 0 0 I12

1 1 0 1 I13

1 1 1 0 I14

1 1 1 1 I15

We can implement 16x1 Multiplexer using lower order Multiplexers easily by considering
the above Truth table. The block diagram of 16x1 Multiplexer is shown in the following
figure.

The same selection lines, s2, s1 & s0 are applied to both 8x1 Multiplexers. The data inputs
of upper 8x1 Multiplexer are I15 to I8 and the data inputs of lower 8x1 Multiplexer are I7 to
I0. Therefore, each 8x1 Multiplexer produces an output based on the values of selection
lines, s2, s1 & s0.
The outputs of first stage 8x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is
present in second stage. The other selection line, s3 is applied to 2x1 Multiplexer.

If s3 is zero, then the output of 2x1 Multiplexer will be one of the 8 inputs Is7 to
I0 based on the values of selection lines s2, s1 & s0.

If s3 is one, then the output of 2x1 Multiplexer will be one of the 8 inputs I15 to
I8 based on the values of selection lines s2, s1 & s0.
Therefore, the overall combination of two 8x1 Multiplexers and one 2x1 Multiplexer
performs as one 16x1 Multiplexer.

Types of Multiplexers:
Multiplexing is the process by which multiple analog signals and data streams are output as one signal. Because
the output is a compressed version of the input, multiplexing is an effective and inexpensive way to transmit and
share information via telecommuting or a computer network. Often, the medium through which the multiplexed
signal is transmitted can be shared, such as a telephone wire that transmits multiple phone calls. Once the stream
reaches its destination, a process called demultiplexing returns the data stream to its original, decompressed state.
The device that enacts multiplexing is called a multiplexer.

There are several different types of multiplexers, in this article we talk about the following:

 Time Division Multiplexer

 Statistical Multiplexer
 Inverse Multiplexer
 Space Division Multiplexer
 Frequency Division Multiplexer
 Wavelength Division Multiplexer

Because multiplexers operate by taking several signals and converting them into one, they are switches with
multiple input feeds and one output. As a result of the compressed output, a multiplexer can make use of only one
device or transmitter, such as a power line or an A/D converter.

Time Division Multiplexer (TDM)

A time division multiplexer (TDM) is sometimes applicable in telecommunications or signal processing to select
pieces of multiple digital (and sometimes analog) signals and compile them into one signal—a pulse amplitude
modulated (PM) wide-angle signal—and then transmit each piece of the larger signal in an individual time slot, so
as to restrict interference. Although the transmission appears simultaneous, each piece of the signal is taking a
turn.

Statistical Multiplexer

When it comes to other telecommunications, digital video, and computer network applications, sometimes a
statistical multiplexer is helpful. This type of multiplexer bundles variable bit rate data signals into one, bandwidth
signal. However, the bandwidth is divided so that larger bitrates have more space than smaller bit-rates. This
enables the real time transmission of different streams at the same time, without compromising the video or audio
quality of larger streams.

Inverse Multiplexer

An inverse multiplexer essentially does the opposite of the Statistical Multiplexer: it employs multiple channels to
transmit one signal, by breaking the signal into smaller bits.
In addition to statistical and time division multiplexers, several other kinds of multiplexers employ different
methods to transmit signals:

Space Division Multiplexing

In space division multiplexing, the various data streams are spaced out across the same wire or medium to limit
interference.

Frequency Division Multiplexing (FDM)

In frequency division multiplexing, each piece of data is transmitted at a different level of frequency across the
same bandwidth—each signal occupies a different part of the bandwidth simultaneously.

Wavelength Division Multiplexer (WDM)

Fiber optic communications require a different kind of multiplexer called a wavelength division multiplexer. Like
the other multiplexers, a WDM depends on a shared medium, in this case a fiber optic cable. However, inside the
cable each individual signal is transmitted using an individual wavelength. In certain applications, the wavelengths
cans transfer data in either direction, from the multiplexer to the demultiplexer and the other way around. Inside
the fiber optical cable, it is not uncommon to have as many as 16 different wavelengths transmitting signals
simultaneously.

Multiplexers are, by nature, cost effective. Because the output of a multiplexer can be connected to a shared
device, and the input portal for a demultiplexer need only have a single input, the number of additional devices is
greatly minimized. Using separate channels for each uncompressed stream would be more expensive than the
transfer of data in compressed form, as in a multiplexer. Sometimes a machine or a piece of equipment will have
both a multiplexer and a demultiplexer, in which case they are both referred to as the “multiplexer” because
they work together to transmit data back and forth.

Block Diagram: Truth Table:

Logic Diagram:
Truth Table:
Circuit Diagram of 4 to 16 Decoder:
4.

6.What is a decoder? Construct a 4×16 decoder with two 3×8 decoders.

Draw and explainthe relevant logic.
A decoder is a combinational circuit constructed with logic gates. It is the reverse of the encoder. A decoder
circuit is used to transform a set of digital input signals into an equivalent decimal code of its output. For ‘n’
inputs a decoder gives 2^n outputs. In this article, we will discuss on 4 to 16 decoder circuit design using 3
to 8 decoder.
An encoder is a combinational circuit that changes a set of signals into a code. For ‘2^n’ inputs an encoder
circuit gives ‘n’ outputs.

Block diagram of a decoder:

3 to 8 Decoder
This decoder circuit gives 8 logic outputs for 3 inputs. The circuit is designed with AND and NAND
combinations. It takes 3 binary inputs and activates one of the eight outputs.

Block Diagram:

Circuit Diagram:
The decoder circuit works only when the Enable pin is high.
Truth Table:

Circuit Design of 4 to 16 Decoder Using 3 to 8 Decoder:

A decoder circuit of the higher combination is obtained by adding two or more
lower combinational circuits. 4 to 16 decoder circuit is obtained from two 3 to 8
decoder circuits or three 2 to 4 decoder circuits.
When two 3 to 8 Decoder circuits are combined the enable pin acts as the input
for both the decoders. When enable pin is high at one 3 to 8 decoder circuits then
it is low at another 3 to 8 decoder circuit.
We know that 3 to 8 Decoder has three inputs A2, A1 & A0 and eight outputs,
Y7 to Y0. Whereas, 4 to 16 Decoder has four inputs A3, A2, A1 & A0 and sixteen
outputs, Y15 to Y0.The parallel inputs A2, A1 & A0 are applied to each 3 to 8
decoder. The complement of input, A3 is connected to Enable, E of lower 3 to 8
decoder in order to get the outputs, Y7 to Y0. These are the lower eight min
terms. The input, A3 is directly connected to Enable, E of upper 3 to 8 decoder in
order to get the outputs, Y15 to Y8. These are the higher eight min terms.

An Encoder is a combinational circuit that performs the reverse operation of Decoder.It

has maximum of 2^n input lines and ‘n’ output lines, hence it encodes the information
from 2^n inputs into an n-bit code. It will produce a binary code equivalent to the input,
which is active High. Therefore, the encoder encodes 2^n input lines with ‘n’ bits.

Priority Encoder –A 4 to 2 priority encoder has 4 inputs : Y3, Y2, Y1 & Y0 and 2 outputs : A1 & A0. Here, the
input, Y3 has the highest priority, whereas the input, Y0 has the lowest priority. In this case, even if more
than one input is ‘1’ at the same time, the output will be the (binary) code corresponding to the input, which
is having higher priority.

The truth table for priority encoder is as follows :

The above two Boolean functions can be implemented as :

Drawbacks of Normal Encoders –

1. There is an ambiguity, when all outputs of encoder are equal to zero.
2. If more than one input is active High, then the encoder produces an output, which may
not be the correct code.
So, to overcome these difficulties, we should assign priorities to each input of encoder.
Then, the output of encoder will be the ( code corresponding to the active High inputs,
which has higher priority.
Uses of Encoders –
1. Encoders are very common electronic circuits used in all digital systems.
2. Encoders are used to translate the decimal values to the binary in order to perform the
binary functions such as addition, subtraction, multiplication, etc.
3. Other applications especially for Priority Encoders may include detecting interrupts in
microprocessor applications.

9.Implement a 5-to-32-line decoder with four 3-to-8-line decoders with

enable and a 2-to- 4-line decoder.

1.Design a 4-bit binary adder-subtractor circuit with

basic gates.
4-bit binary Adder-Subtractor
In Digital Circuits, A Binary Adder-Subtractor is one which is capable of both addition and
subtraction of binary numbers in one circuit itself. The operation being performed depends upon
the binary value the control signal holds. It is one of the components of the ALU (Arithmetic Logic
Unit).
This Circuit Requires prerequisite knowledge of Exor Gate, Binary Addition and Subtraction, Full
Adder.
Let’s consider two 4-bit binary numbers A and B as inputs to the Digital Circuit for the operation
with digits
A0 A1 A2 A3 for A
B0 B1 B2 B3 for B
The circuit consists of 4 full adders since we are performing operation on 4-bit numbers. There is a
control line K that holds a binary value of either 0 or 1 which determines that the operation being
carried out is addition or subtraction.

As shown in the figure, the first full adder has control line directly as its input(input carry C0), The
input A0 (The least significant bit of A) is directly input in the full adder. The third input is the exor
of B0 and K (S in fig But do not confuse it with Sum-S). The two outputs produced are
Sum/Difference (S0) and Carry (C1).
If the value of K (Control line) is 1, th output of B0(exor)K=B0′(Complement B0). Thus the
operation would be A+(B0′). Now 2’s complement subtraction for two numbers A and B is given by
A+B’. This suggests that when K=1, the operation being performed on the four bit numbers is
subtraction.
Similarly, If the Value of K=0, B0 (exor) K=B0. The operation is A+B which is simple binary
addition. This suggests that When K=0, the operation being performed on the four bit numbers is
addition.
Then C0 is serially passed to the second full adder as one of it’s outputs.The sum/difference S0 is
recorded as the least significant bit of the sum/difference. A1, A2, A3 are direct inputs to the
second, third and fourth full adders. Then the third input is the B1, B2, B3 EXORed with K to the
second, third and fourth full adder respectively. The carry C1, C2 are serially passed to the
successive full adder as one of the inputs. C3 becomes the total carry to the sum/difference. S1,
S2, S3 are recorded to form the result with S0.
For an n-bit binary adder-subtractor, we use n number of full adders.
Example:
Let’s take two 3 bit numbers A=010 and B=011 and input them in the full adder with both values of
control lines.
For K=0:
B0(exor)K=B0 and C0=K=0 Thus,
Thus from first full adder A = 010 = 2
= A0+B0 B = 011 = 3
= 0+1 Sum(Difference) = 1111 = -1
= 1,
S0=1
C1=0
Similarly,
S1=0 with C2=1
S2=1 and C2=0
Thus,
A = 010 =2
B = 011 = 3
Sum = 0101 = 5
For K=1
B0(exor)K=B0' and C0=k=1
Thus
S0=1 and C1=0
Similarly
S1=1 and C2=0
S3=1 and c3=1
 1. Write an HDL behavioral description of a 16X1 multiplexer.
A 16x1 multiplexer is a digital circuit which has 16 inputs, 1 output and 4 selection lines. Output of the
multiplexer is derived by the 4 selection lines i.e. the input is transferred to the output depending on the
value of the selection lines.

In the codes given below x is a 16 bits input, s is a 4 bits input which will work as 4 selection lines and y
is the output of 1 bit. Simple If ELSE statement is used in the program in which the different values of s
are compared and depending on the match the corresponding input is transferred to the output pin.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux161 is
Port ( x : in std_logic_vector(15 downto 0);
s : in std_logic_vector(3 downto 0);
y : out std_logic);
end mux161;

architecture mux of mux161 is

begin
process(x,s)
begin
y<=x(11);
if(s="0000")then
elsif(s="1100")then
y<=x(0);
y<=x(12);
elsif(s="0001")then
elsif(s="1101")then
y<=x(1);
y<=x(13);
elsif(s="0010")then
elsif(s="1110")then
y<=x(2);
y<=x(14);
elsif(s="0011")then
else
y<=x(3);
y<=x(15);
elsif(s="0100")then
end if ;
y<=x(4);
end process ;
elsif(s="0101")then
end mux;
y<=x(5);
elsif(s="0110")then
y<=x(6);
elsif(s="0111")then
y<=x(7);
elsif(s="1000")then
y<=x(8);
elsif(s="1001")then
y<=x(9);
elsif(s="1010")then
y<=x(10);
elsif(s="1011")then

2.Verilog Behavioral Program for Multiplexers

 8X1 MULTIPLEXER :

module eight_to_onemux(s,p,q);
input[2:0]s;
input[7:0]p;
output q;
reg q;
always@(s or p)
begin
case(s)
3'b000:q=p[0];
3'b001:q=p[1];
3'b010:q=p[2];
3'b011:q=p[3];
3'b100:q=p[4];
3'b101:q=p[5];
3'b110:q=p[6];
3'b111:q=p[7];
endcase
end
endmodule

16X1 MULTIPLEXER :
module multiplexer(s,p,q);
input[3:0]s;
input[15:0]p;
output q;
reg q;
always@(s or p)
begin
case(s)
4'b0000:q=p[0];
4'b0001:q=p[1];
4'b0010:q=p[2];
4'b0011:q=p[3];
4'b0100:q=p[4];
4'b0101:q=p[5];
 4'b0110:q=p[6];
4'b0111:q=p[7];
4'b1000:q=p[8];
4'b1001:q=p[9];
4'b1010:q=p[10];
4'b1011:q=p[11];
4'b1100:q=p[12];
4'b1101:q=p[13];
4'b1110:q=p[14];
4'b1111:q=p[15];
endcase
end
endmodule

3.Verilog
Save Code for 4x16 Decoder
Share

module decoder_4x16 (d_out, d_in);

output [15:0] d_out;

input [3:0] d_in;
parameter tmp = 16'b0000_0000_0000_0001;

assign d_out = (d_in == 4'b0000) ? tmp :

(d_in == 4'b0001) ? tmp<<1:
(d_in == 4'b0010) ? tmp<<2:
(d_in == 4'b0011) ? tmp<<3:
(d_in == 4'b0100) ? tmp<<4:
(d_in == 4'b0101) ? tmp<<5:
(d_in == 4'b0110) ? tmp<<6:
(d_in == 4'b0111) ? tmp<<7:
(d_in == 4'b1000) ? tmp<<8:
(d_in == 4'b1001) ? tmp<<9:
(d_in == 4'b1010) ? tmp<<10:
(d_in == 4'b1011) ? tmp<<11:
(d_in == 4'b1100) ? tmp<<12:
(d_in == 4'b1101) ? tmp<<13:
(d_in == 4'b1110) ? tmp<<14:
(d_in == 4'b1111) ? tmp<<15: 16'bxxxx_xxxx_xxxx_xxxx;

endmodule

4.Write an HDL dataflow description of a 4-bit adder subtractor of unsigned

numbers.
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
ENTITY add_sub IS
PORT ( A, B : IN std_logic_VECTOR (3 DOWNTO 0); -- 4-bit Data
M : IN std_logic; -- M = 0 ADD ; M =1 SUB
S : OUT std_logic_vector ( 3 DOWNTO 0); -- sum or difference
C : OUT std_logic); -- Carry / Borrow
END add_sub; -- end of entity
ARCHITECTURE dataflow OF add_sub IS
SIGNAL BM : std_logic_VECTOR (3 DOWNTO 0);
signal sum : std_logic_VECTOR ( 4 downto 0);
Begin
BM <= NOT B;
SUM <= ('0'&A) + ('0'&B) WHEN M = '0' ELSE ('0'&A)+('0'&BM)+"0001";
S <= SUM (3 downto 0 );
C <= SUM (4);
End dataflow;
5.Behavioral description of 16:1 MUX.