The Bosch Process

Brian Vanderelzen
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Bosch Process Overview
– U.S. Patent #5,501,893
– Assigned to Robert Bosch Gmbh
– 8/5/94
– A mechanism for anisotropically etching silicon in
a plasma environment
– The mechanism employs alternating a semi-
isotropic etch step with a polymerizing step
– Initial chemistry involved SF6 & Ar for the etch,
CHF3 & Ar for the polymerization
– The Bosch process offers significant advantages
over prior art including repeatability, etch rate,
selectivity, and aspect ratio

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Bosch Process Overview (Cont.)

• Processed licensed initially by STSystems, Inc. who

continued to advance the process in conjunction with
Bosch
• Process currently licensed by a wide variety of
Semiconductor tool manufacturers
• A primary enabler of MEMS technology
• Enables very deep etching in silicon with high
selectivity
– Depths > 1mm
– Rates > 10 microns per minute
– Aspect ratios > 50:1
– Selectivities
• >50:1 Photoresist mask
• >200:1 SiO2 mask

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4
Anatomy of a directional etch

• Reactive Ion Etching is a bit of a misnomer. Etching

is primarily done by neutral reactive species. This
chemical component is more or less isotropic.
• In order to achieve anisotropy, there must be some
form of resistance to the chemical component
• A delicate balance must then be achieved such that
the chemical etch can only proceed where the
directional physical ion bombardment overcomes this
etch resistance

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5
Mechanisms of Anisotropy

• Generally etch resistance is referred to as

passivation – an etch resistant layer deposited during
the etch
– Polymer forming gas – fluorocarbons
– O2 to form etch resistant oxide
– Self passivating etchants such as HBr
• Reacted species exhibit low volatility
• Require physical bombardment to be released from the
surface

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6
Limitations of Single Step Process
• Passivation inhibits vertical etching at the same time that it
prevents lateral etch, resulting in slow etch rates
• Passivating chemistry often reacts with the etch mask reducing
selectivity
– Fluorocarbons etch oxide
– O2 etches photoresist
• The physics of deposition is significantly different than that of
etch
– As aspect ratio increases, the demands of each change
independently and frequently in opposite directions
– Low pressures and high bias voltage improves directionality,
allowing ions to reach the bottom of narrow trenches. These
same parameters reduce efficiency and conformality of
deposition.

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7
Do the Two Step

• The Bosch Process overcomes these limitations by

segregating the etch and passivation into
independently controllable steps
• The typical process alternates a highly chemical SF6
based etch step with a teflon-like polymer forming
passivation step
• The passivation step conformally coats all surfaces
• The etch may then only proceed where the energetic
ions break through this passivation
• Typical step times range from 5 to 20 seconds
• The etch step typically exhibits poor anisotropy,
however, by keeping the steps short, one builds an
anisotropic etch from stacked isotropic ‘blocks’

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8
The Etch Step

• Directional ions and non-directional reactive species

etch silicon for several seconds

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9
Passivation

• ICP power breaks down C4F8, with little to no bias

power
• A fluorocarbon polymer precipitates out on all
surfaces

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10
Repeat Etch

• Directional energetic ions break through passivation

on horizontal surfaces
• Reactive neutral species do not etch until silicon is
exposed

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11
Repeat Etch 2

• Repeat isotropic etches stack to form an anisotropic

etch

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12
Scalloping

• The stepped process typically results in a scalloped

sidewall
• This SEM shows typical undercut and scalloping for a
moderately high rate process

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13
Parameter Ramping

• The physics of the process changes with aspect ratio

• It is desirable to ramp parameters as the process
proceeds
• Pressure is routinely decreased with time to allow
gases to get in and out of narrow features and to
increase ion directionality
• Cycle times, gas flows, and power may also be
adjusted as the etch progresses

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14
Issues – Undercut and Scalloping
• Undercut and scalloping are a result of the isotropic nature of
the etch step
• May be reduced by shortening cycle times
• Adding C4F8 or O2 to the etch will increase step anisotropy and
reduce both scalloping and undercut at the expense of
selectivity

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15
Undercut & Scalloping
• Image on left shows scalloping < 20nm
• Image on the right ‘probably’ better
• Results achieved by adding high O2 flow to etch step
• Dramatically reduces PR selectivity – will require hard mask

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16
Issues – ARDE (RIE Lag)
• Etching is highly aspect ratio dependent
• High aspect ratio features tend to etch much slower than small
aspect ratio features
• It is very difficult to optimize an etch for varying feature sizes
– Etches that are optimized for small features tend to widen
large features
– Etches optimized for large features tend to cause etch
stopping or grass in small features

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17
Issues - Notching

Slide courtesy of CMI - Center of MicroNanoTechnology, Ecoles Polytechniques fédérales de Lausanne

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18
Notching Solution – lf pulsing

Slide courtesy of CMI - Center of MicroNanoTechnology, Ecoles Polytechniques fédérales de Lausanne

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19
Issues – Loading and Microloading
• The etch is significantly chemically
limited
• The rate at which gas reaches the
surface determines etch rate
• Thus patterns with large open areas
may etch slower than denser patterns
– Using the same recipe, a wafer with
80% open area may etch as slow
as ¼ the rate of a wafer with 10%
open area
– Etch recipes must be optimized for
specific pattern density
• Local density or microloading also an
issue
– Ideally solved in the design phase

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20
The Modern Bosch Process
• The Bosch process has been developed and improved over the
years primarily in University and R & D type environments
• Tool manufacturers are now working on creating production
ready tools and processes
• Etch rate has seen dramatic increases recently to over 40
microns per minute
• Tools for 200mm and 300mm wafers are now being produced
• Many of typical Bosch process issues have now been resolved
– Etch rates > 40 microns per minute
– Uniformity < 3%
– Aspect ratios near 100:1
– Sidewall roughness < 15nm
– SOI notching greatly improved or eliminated
– ARDE issues greatly reduced

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© Surface Technology Systems plc, January 06
STS Confidential
 Data Storage
Packaging
Advanced
Photonics
Semiconductors
Compound

Recent Process Results

MEMS

© Surface Technology Systems plc, January 06 STS Confidential

 Data Storage
Pegasus: An Enabling Technology

Optical MEMS
switching
Packaging
Advanced

Silicon
Inertial Ink Jet heads
sensors
Photonics

RF MEMS
De-coupling
capacitors
Semiconductors
Compound

Advanced
Packaging

Micro Fluidics
Power
MEMS

‘Lab on a chip’ MEMS Pressure Devices

sensors
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 Data Storage
Packaging
Via SOI
Advanced
Photonics

50µm vias, 200mm wafers

Semiconductors

Etch Characteristic Target Achieved

Compound

Depth (µm) 250 250

Etch Rate (µm/min) >10 10.06
Uniformity (±%) <3 <1
Sidewall Roughness (nm) <200 <186
Profile angle (o) 89 90
MEMS

Notching (nm/edge) <500 ~760

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 Data Storage
Very High Aspect Ratio

Aspect Ratio: 73:1!

Packaging
Advanced

Issues:
- Bowing at top of trench

Process development
still in progress.
Photonics

0.8µm trench, 150mm wafer (note: ¼ piece)

Etch Characteristic Specification Achieved
Semiconductors
Compound

Depth (µm) 100 ~81

Rate (um/min) >3 1.49
Uniformity (±%) 5 2.2
Selectivity Si:SiO2 >50:1 >54:1
Initial mask undercut (nm) <50 <60
MEMS

Sidewall roughness (nm) <50 ~40

Profile (º) 89-90 89.9
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 Data Storage
Packaging
Wafer Level Packaging
Advanced
Photonics

180µm trench, 200mm wafer

Semiconductors
Compound

Etch Characteristic Target Achieved

Depth (µm) 75 75
Etch Rate (µm/min) >10 ~15
Profile angle (o) 55-60
MEMS

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 Data Storage
Packaging
Advanced
Photonics
Semiconductors
Compound

Results of recent work to increase etch rate

MEMS

© Surface Technology Systems plc, January 06 STS Confidential

 Data Storage
Pegasus High Rate Switched Process

Close to practical application

Packaging
Advanced

100µm via
69µm deep
Photonics

etched at 35µm/min
on standard Pegasus
Semiconductors
Compound

(200mm wafer, open

area 10%)
MEMS

© Surface Technology Systems plc, January 06 STS Confidential

 Data Storage
Pegasus High Rate Switched Process

Champion data
Packaging
Advanced

35µm trench
92µm deep
Photonics

etched at 46µm/min
on standard Pegasus
Semiconductors
Compound

(200mm wafer, open

area 1%)
MEMS

© Surface Technology Systems plc, January 06 STS Confidential

 Data Storage
Pegasus High Rate Switched Process

Champion data
Packaging
Advanced

80µm trench
100µm deep
Photonics

etched at 50µm/min
on standard Pegasus
Semiconductors
Compound

(200mm wafer, open

area 1%)
MEMS

© Surface Technology Systems plc, January 06 STS Confidential

 Pole Position in DRIE 
Data Storage
Packaging
Advanced
Photonics
Semiconductors
Compound
MEMS

© Surface Technology Systems plc, January 06 STS Confidential

 STS ASE-SR Process
Capabilities

Prepared for
University of Michigan NNIN Meeting

© Surface Technology Systems plc, January 06

STS Confidential
 Data Storage
Contents

„ Examples of process capability of standard rate system at

University of Michigan
Packaging
Advanced

„ Deep etching at high etch rates

„ High aspect ratio etching
„ Smooth sidewalls
„ Minimising RIE lag
Photonics

„ STS Contact details

Semiconductors
Compound
MEMS

© Surface Technology Systems plc, January 06 STS Confidential

 Deep Etching

© Surface Technology Systems plc, January 06

STS Confidential
 Data Storage
Through Wafer / Deep Etch

„ Main Requirements:
„ High Etch-rate
Packaging
Advanced

„ High Selectivity to Mask

„ Profile Control of >10:1 Aspect Ratio
„ Sidewall Roughness Control
Photonics

Silicon micromachined fuel

Semiconductors

atomiser showing smooth

Compound

sidewalls and base of silicon.

A magnification of the exit hole
is shown top right.
MEMS

© Surface Technology Systems plc, January 06 STS Confidential

 Data Storage
Packaging
Deep Etching
Advanced
Photonics
Semiconductors
Compound
MEMS

Cross-section of a 350µm deep bore through silicon.

Etch rate 2.8µm/min, anisotropy >0.99.
© Surface Technology Systems plc, January 06 STS Confidential
 Data Storage
Through Wafer Etching

Anisotropy >0.99
Selectivity >300:1 to SiO2 mask
Etch Rate » 3 µm/min
Packaging
Advanced

Wafer is 200 µm thick, underlayer is SiO2

Photonics
Semiconductors
Compound
MEMS

© Surface Technology Systems plc, January 06 STS Confidential

 Smooth Sidewalls

© Surface Technology Systems plc, January 06

STS Confidential
 Data Storage
Ramping Gas Flow

Without Parameter Ramping

Packaging
Advanced

Undercut/edge =320nm
Scalloping = 230nm
Photonics

With Parameter Ramping

Semiconductors
Compound

Undercut/edge =100nm
Scalloping = 40nm
MEMS

© Surface Technology Systems plc, January 06 STS Confidential

 High Aspect Ratio Etching

© Surface Technology Systems plc, January 06

STS Confidential
 Data Storage
High Aspect Ratio Via Etch

30 µm via,
Packaging
Advanced

324 µm depth:

Typical results:
90.2°
Photonics

>50:1 Si:PR

Etch rate, depth

Semiconductors

limited by sidewall
Compound

break-down
MEMS

100mm wafer diameter, 5% exposed area,

7 µm photoresist + 3 µm TEOS mask
© Surface Technology Systems plc, January 06 STS Confidential
 Data Storage
Packaging
High Aspect Ratio Via Etch - Breakdown
Advanced
Photonics
Semiconductors
Compound
MEMS

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 Data Storage
High
High Aspect aspect
Ratio ratio vias
Etch
Typical application:
Trench capacitors, trench isolation,
MOS decoupling capacitors in RF
Packaging
Advanced

circuits

Typical requirements:
2-20 µm holes/trenches
Photonics

Up to 100 µm depth
Vertical/positive slope
Smooth sidewalls
Rounded base
Semiconductors
Compound

Results Courtesy of F. Roozeboom, Philips

89.4° profile Typical example:
Selectivity >20:1 Si:Ox; 1.5 µm diameter holes
>10:1 Si:PR >33 µm depth
<80nm scallops; 150 mm wafer diameter
MEMS

<270nm/edge CD loss ~15 % exposed Si area

© Surface Technology Systems plc, January 06 STS Confidential
 RIE Lag

© Surface Technology Systems plc, January 06

STS Confidential
 Data Storage
Reducing RIE Lag

„ Control of RIE lag is difficult however there are some general

process trends which help.
Packaging
Advanced

„ Increase the deposition characteristic

„ The deposition at the base of large features is greater than that in
smaller features.
Photonics

„ Reduce etch rate in larger features

Semiconductors
Compound
MEMS

© Surface Technology Systems plc, January 06 STS Confidential

STS Confidential
 Data Storage
Packaging
Examples of Minimal RIE Lag
Advanced
Photonics
Semiconductors
Compound
MEMS

© Surface Technology Systems plc, January 06 STS Confidential

 Data Storage
If You Need More Information Contact…

Steve Hall
Packaging
Advanced

Mid West Regional Sales Manager

Cell: 608 234 2934
Email: stephen.hall@stsystems.co.uk
Photonics
Semiconductors
Compound
MEMS

© Surface Technology Systems plc, January 06 STS Confidential