1817-SanDiegoCPMTDL Lau Advancedpackaging

3D IC Packaging
3D IC Integration
John H. Lau
ASM Pacific Technology
16-22 Kung Yip Street, Kwai Chung, Hong Kong
852-2619-2757, john.lau@asmpt.com
CPMT Distinguish Lecture, San Diego Chapter, February 23, 2015 1

Contents
 3D IC Packaging (without TSV)
 Stack Chips by Wire Bonding
 Package-on-Package (PoP)
 Chip-to-Chip Interconnects
 Embedded Fan-Out Wafer Level Package (eWLP)
 Infineon, Freescale, TSMC’s eWLP
 Infineon, ASE, Amkor, STATSchippac, STMicroelectroinc’s 3D eWLP
 3D IC Integration
 Memory-Chip Stacking in Production
 Hybrid Memory Cube (HMC)
 Intel’s Knight’s Landing with HMC
 Fujitsu’s Supercomputer with HMC
 Altera’s FPGA with HMC
 Wide I/O DRAM and Wide I/O 2
 High Bandwidth Memory (HBM)
 Samsung’s Widcon Technology for Mobile Products
 2.5D IC Integration
 Xilinx/TSMC’s Interposer
 Altera/TSMC’s Interposer
 ITRI’s Interposer for 3D IC Integration
 Supply Chains and Ownerships for 2.5D/3D IC Integration
 Recent Advances in Package Substrates
 Coreless Substrates
 Thin-Film Layer on Build-up Package Substrate
 Embedded Interposer/Bridge
 3D MEMS and IC Integration
 3D CIS and IC Integration
 Summary and Q&A
2
3D Integration Technologies
Don’t use TSV Use TSV technology
3D IC Packaging 3D IC Integration 3D Si Integration
Full swing production for memories.
Mass
Volume production for mobile
Production products.
Die Active applied R&D is

undertaken by Research
Commercia Stacking Institutes. TSV cost is the key. In
Package
-lization with wire the phase of industrialization.
Maturity
on
bonds
Package
(PoP) Still in upstream research,
technological challenges
Applied Stacking such as KGD, yield & device
architecture and EDA are key
R&D issues.
C2C, C2W,
W2W
Basic/ Stacking
Applied W2W
R&D Stacking
Technology 3
Lau, IEEE-ECTC PDC , 2009
3D IC Packaging
(No TSV)
 Memory Stacked with Wirebonds
 Solder Bumped Flip Chip Assembly
 Package-on-Package (PoP)
 Chip-to-Chip Interconnects
 Embedded Fan-Out Wafer Level
Package (eWLP)
4
Memory Stacked with
Wirebonds
5
Memory chips stacking by die attach and wire
bonding [1994, nCHIP]
Bevel or
Chip 3 Notch
Bond
Memory Chip 2 wires
chips
Die attach Chip 1

material
Substrate
6
Samsung’s Eight-Stack Flash in Apple’s iPhone 4s
SK Hynix’s MLC (Multi Level Cell) 8GB (Gigabyte)

NAND Flash in Apple’s iPhone 5s
FBGA (Fine-pitch
Wire bonding Nand Molding
Ball Grid Array)
Flash chips 7
Amkor’s 3D IC Packaging with Cu Wires
Top
Chip
Cu
Wires
Bottom Chip
Substrate
8
Package-on-Package
(PoP)
9
PoP (Package-on-Package) Format
(Apple A7 Application Processor Chipset)
Apple’s A7 processor Elpida’s 1GB LPDDR3
2-2-2 Build-up package substrate
10
Top-View and Cross Section View of the PoP
(for Mobile DRAM and A8 Processor) inside iPhone 6 Plus
Top-side of the bottom PoP (426-ball)
Elpida’s 1GB LPDDR3

(EDF8164A3PM-GD-F)
Application
Processor
Package Substrate for LPDDR3
Package Substrate for A8 processor
Apple’s application processor

Not-to-scale (POXY99001)
(for Mobile DRAM and Application Processor)
iPhone 6 Plus iPhone 6S

(EDF8164A3PM-GD-F) 2GB LPDDR4
Package Substrate for LPDDR3 Package Substrate for LPDDR4
Package Substrate for A8 processor Package Substrate for A9 processor
A8 application processor A9 application processor

fabricated by 20nm process fabricated by 14/16nm Fin-FET process
Not-to-scale
Samsung’s Next Generation High-End Smartphones
LPDDR3 Exynos
Microprocessor
Conventional Flash chip-set
Solution PCB
ePoP
ePoP (Flash and LPDDR3 ePoP Exynos
Solution combination)
Microprocessor
A 40% PCB saving! PCB

Chip-to-Chip
Interconnects
14
IME’s Stacked Silicon Module Attached on a Substrate
Heat spreader/sink (optional)
Microbump
Mother Chip
Daughter Chip Solder Bump
Rigid or Flex Substrate
Solder Ball
PCB
Chip-to-Chip and Face-to-Face

Lim, Lau, et.al., “Process Development and Reliability of Microbumps”, IEEE/EPTC, 2008, pp. 367-372. Also,
IEEE Transactions on CPMT, 2010, pp. 747-753. 15
SONY's CXD53135GG used a 5-chip stack.
(Wire bonding and solder bump)
Solder
bumps
Wire bonds Face-to-face (Chip-to-chip)
Processor: 250μm. All the other chips: Samsung 2-Gb mobile DDR2 SDRAMs
100 to 125μm a spacer die

Samsung 2-Gb mobile DDR2 SDRAMs
Samsung 1-Gb wide I/O SDRAM
Processor
16
Amkor’s POSSUM™ assembly where the daughter die (e.g.,
memory) is mounted face-to-face with the larger mother die (e.g.,
SoC). The mother die is then flip chip mounted onto a substrate
Cu Pillar
Micro-bumps
Daughter
Die
17
Amkor’s Double POSSUM™ multi-stacked die
configurations without the use of TSVs
Daughter Die
Grandma Die
PCB
Cu Pillar Micro-bumps
Package with SnAg solder caps Mother Die
Substrate
SnAg
Cu
Sutanto, J., “POSSUMTM, “Die Design as a Low Cost 3D Packaging Alternative”, 3D Packaging, Issue No. 25, November 2012, pp. 16-18.
18
Amkor’s POSSUM Package showing Altera’s
FPGA and ASIC
Package 40μm-pitch Cu-pillar + 200μm-pitch Cu-
FPGA ASIC
Substrate solder cap microbumps post + solder
Solder
balls
Heat spreader cap ASIC

FPGA
Package Substrate
Solder balls
Heat spreader cap
FPGA
Package Substrate ASIC
Package
Substrate
FPGA ASIC 40μm-pitch Cu-pillar + 200μm-pitch Cu-

solder cap microbumps post + solder
Xie, J., and D. Patterson, “Realizing 3D IC Integration with Face-to-Face Stacking”, Chip Scale Review, May-June Issue, 2013,19
pp. 16-19.
Lau
Embedded Fan-Out
Wafer Level Package
(eWLP)
20
Infineon’s Embedded Wafer-Level
Ball Grid Array (eWLB)
Test for KGD
Molded reconfigured
wafer
Fan-Out
Redistribution
Area (Mold)
Chip Layer (RDL)
Schematic process flow for a fan-out

wafer-level package
Brunnbauer, et.al., “An Embedded Device Technology Based on a Molded Reconfigured Wafer”, IEEE/ECTC, 2006, pp. 547-551.
21
a) Laminate Carrier, b) Pick and Place, c) Molding, d)
Release Tape, and e) Peal Tape
2-side tape
Infineon picked a
Carrier modified, commercially
available tape, which is
Chip face-down equipped with a thermo-
release layer. It is loosing
its adhesive properties
once it is heated above a
Molding specific temperature,
which is higher than any
processing temperature
before.
Peal tape 22
ECTC2006
Infineon was the First Company to Commercialize its own eWLB
Packaging Technology in an LGE cell-phone in early 2009
Mold Baseband SoC
PCB
RDLs Solder ball
Infineon’s chip is a wireless baseband SoC with multiple integrated

functions (GPS, FM radio, BT…). The same eWLB product has also
been in production in Nokia handsets since 2010.
LGE (wireless baseband), Samsung (baseband modem), and Nokia

(baseband modem and RF transceiver) have used Infineon’s eWLB in
their cell phone products.
Infineon eWLB (wireless operation acquired by Intel in 2011)

Intel RF IC 5 mm x 5 mm x 0.67 mm with 139 I/Os and 0.4mm ball pitch
Intel LTE analog baseband 23
Freescale’s Redistributed Chip Package (RCP)
Place die active side down on substrate and encapsulated

with a silica-filled epoxy molding compound
Remove substrate and turn the whole around
Redistribute signal, power and ground 200mm RCP panel with 82

17mmx17mm 208 I/O packages
Deposit BGA solder balls
A 208 I/O 13mmx13mm PBGA with 0.65mm pitch can

Saw panel into individual package be shrunk to a 9mmx9mm RCP with 0.5mm pitch
Keser, et.al., “The Redistributed Chip Package: A Breakthrough for Advanced Packaging”, IEEE/ECTC, 2007, pp. 286-291.
24
Fan-Out eWLP (Embedded Wafer-Level Packaging)
Solder balls
Pads
RDLs KGD
25
Embedded Fan-Out Wafer Level Package (eWLP) vs.
PBGA (Plastic Ball Grid Array)
Fan-out area
(Molded Compound) Redistribution layer
(RDL)
Face-down Chip
Solder Balls
Underfill Molded Compound Substrate

Face-down Chip
Solder Balls Solder Bumps
Eliminate solder bumps, underfill, and package substrate.

Lower Profile! 26
Companies who are Manufacturing/Working on eWLP
 Infineon’s Embedded Wafer-Level Ball Grid Array (eWLB)
Package licensed by ASE, STATS ChipPAC, NANIUM,
STMicroelectronics
 Freescale’s Redistributed Chip Package (RCP) licensed by
NEPES
 TSMC’s Integrated Fan-Out Wafer-Level Package (InFO-WLP)
 ASE’s 3D Fan-Out Wafer-Level PoP (FOPOP)
 AMKOR’s Wafer-Level Fan-Out (WLFO) Package
 SPIL’s Panel Fan-out (P-FO) Package
 STATSChipPAC’s Embedded Wafer Level PoP (eWLB-PoP)
 PTI (NEPES)’ Fan-Out Wafer-Level Package (FOWLP (RCP))
 J-DEVICES’ Wafer-Level Fan-Out Package (WFOP)
 ADL Engineering’s Panel Wafer-Level BGA Package (pWLP)
 STMicroelectronics’ Embedded Wafer Level LGA (eWLL)
 NANIUM’s Fan-Out Wafer-Level Package (FO-WLP)
 DECA’s Fan-Out Wafer-Level Packaging (FOWLP)
 Embedded Fan-Out Wafer-Level Package (eWLP) 27
TSMC InFO-WLP
(Integrated Fan-Out WLP)
At the TSMC Technology Symposium in San Jose, CA in April

2014, TSMC announced the latest InFO-WLP platforms:
 8mm x 8mm is targeted at RF and WiFi chips
 15mm x 15mm is targeted at application processor and baseband chips
 25mm x 25mm could be applied to GPU and networking chips
28
High-Performance Integrated Fan-Out Wafer Level Packaging
(InFO-WLP): Technology and System Integration
Christianto C. Liu, Shuo-Mao Chen, Feng-Wei Kuo, Huan-Neng Chen, En-Hsiang Yeh,
Cheng-Chieh Hsieh, Li-Hsien Huang, Ming-Yen Chiu, John Yeh, Tsung-Shu Lin, Tzu-Jin Yeh,
Shang-Yun Hou, Jui-Pin Hung, Jing-Cheng Lin, Chewn-Pu Jou, Chuei-Tang Wang,
Shin-Puu Jeng, Douglas C.H. Yu
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan, Email: chris liu@tsmc.com
IEEE/IEDM2012
Thermal Management between PBGA and InFO-WLP of
Baseband Chip Set (TSMC Results)
Transceiver
Baseband
Processor
PBGA
Transceiver
Baseband
Processor
Not-to-Scale
InFO-WLP
Thermal Result between PBGA and InFO-WLP
PBGA  First, omission of the substrate
layer in InFO-WLP reduces both
form factor and chip-to-board
thermal path, the latter especially
vital in applications without heat
sinks where heat primarily travels
towards the board.
 Second, junction-to-ambient
thermal path is reduced with InFO-
Max. Tem = 90.5oC WLP’s more efficient multi-chip
Thermal resistant = 32.5oC/W packaging.
 Third, reduced die separation in
InFO-WLP improves lateral heat
InFO-WLP spreading, as shown by the more
uniform heat distribution among the
dies.
 Overall, thermal resistance of
InFO-WLP technology is about
14% better than conventional MCM
(28.0 versus 32.5 oC/W). Here, the
difference in thermal
resistance translates to a 9.0oC
Max. Tem = 81.5oC reduction in maximum temperature.
Thermal resistant = 28.0oC/W
3D eWLB – Horizontal and Vertical Interconnects for
Integration of Passive Components
M. Wojnowski1, G. Sommer1, K. Pressel2, G. Beer2
1Infineon Technologies AG, Am Campeon 1-12, 85579 Neubiberg, Germany
E-mail: maciej.wojnowski@infineon.com
2Infineon Technologies AG, Wernerwerkstraße 2, 93049 Regensburg, Germany
Through
Encapsulant
Via (TEV)
Chip
Mold
Compound
RDLs
Chip
32
IEEE/ECTC2013
3D IC Packaging: PoP
Through
Encapsulant
Via (TEV)
Chip
Mold
Compound
RDLs
Chip
33
Through Encapsulant Via (TEV)
Laser Drilled
Through Encapsulant Via
(100 - 150µm)
Sputter the Ti/Cu

+ Cu plating
34
STMicroelectronics’ 3D eWLB
Chip 1 Chip 2
Chip 3
Chip 1 Chip 2
35
ASE’s Double Sided 3D FOWLP –
Package on Package (FOPOP)
RDLs MC Top Package
Chip
Through Mold MC Bottom

Via Chip Package
RDLs
SEMICON West 2013 36

AMKOR’s Wafer-Level Fan-Out (WLFO) Package
Wire Bonds Memory Chips
Chip
Solder Redistribution Substrate Through Mold Vias

Bump Layers 37
3D Packaging, November 2012
STATSChipPac’s 3D IC Packaging
38
3D Integration Technologies
Don’t use TSV Use TSV technology
3D IC Packaging 3D IC Integration 3D Si Integration
Full swing production for memories.
Mass
Volume production for mobile
Production products.
Die Active applied R&D is

undertaken by Research
Commercia Stacking Institutes. TSV cost is the key. In
Package
-lization with wire the phase of industrialization.
Maturity
on
bonds
Package
(PoP) Still in upstream research,
technological challenges
Applied Stacking such as KGD, yield & device
architecture and EDA are key
R&D issues.
C2C, C2W,
W2W
Basic/ Stacking
Applied W2W
R&D Stacking
Technology 39
Lau, IEEE-ECTC PDC , 2009
TSV
(Through-Silicon Via)
40
TSV (Through-Silicon Via)
William Shockley (co-invented the transistor) filed a patent, “Semiconductive
Wafer and Method of Making the Same” on October 23, 1958 and was granted
the US patent (3,044,909) on July 17, 1962.
William Shockley
(1956 Nobel laureate)
Deep Pits (Holes),
We call TSV today
41
Intel’s TSV (Through-Silicon Via) for the
Shortest Chip-to-Chip Interconnects
Wirebonds
A four stack
wire-bonded
die package
Wirebonds are replaced by TSVs
Advantages:
 Smaller form-
Wire → TSV
factor
Microbumps  Low power
consumption
Thin chips  Wider bandwidth
 Better
performance
42
Lau, Reliability of 3D IC Interconnects, 2011
3D IC Integration
 Memory chip stacking
 Wide I/O DRAM, Wide I/O 2, or

Hybrid Memory Cube (HMC)
 High Bandwidth Memory (HBM)
43
3D IC Integration (The right thing to do!)
Said the 1965 Nobel Physics laureate, Richard
Feynman at the Gakushuin University (Tokyo) in
1985:
“Another direction of improvement (of computing

power) is to make physical machines three
dimensional instead of all on a surface of a chip
(2D). That can be done in stages instead of all at
once – you can have several layers and then add
many more layers as time goes on.”
Thin
Chip
TSV
Micro
Bumps
44
3D IC Integration (The right thing to do!)
Thin
Chip
TSV
Micro
Bumps
TSVs straight through the same memory chips to:

 enlarge the memory capacity
 lower the power consumption
 increase the bandwidth
 lower the latency (enhance electrical performance)
 reduce the form factor
will be the major applications of 3D IC Integration!
45
Potential Applications of 3D IC Integration
Memory-Chip Wide I/O DRAM Wide I/O Interface
Stacking (Hybrid Memory Cube) (2.5D IC Integration)
 DRAM stacking with  TSV-less chips on
 DRAM or NAND a device-less
Flash stacking TSVs on Logic
Controller with TSVs wafer (interposer)
with TSVs on with TSVs
organic substrate  Over molding the
DRAMs  Underfill is
 Over molding the needed between
DRAMs or NAND chips and the
Flash interposer
Organic Package Substrate
PCB
Underfill is needed between the active/passive TSV interposer and the organic substrate
46
Memory chip stacking
47
Samsung’s 3D Stacking with
TSV (Through Silicon Via)
Thin Chip
TSV
16Gb Flash
memory
(8 x 2Gb)
560μm Micro
bump
8-stack chips (50μm each) connected

Wafer before back-grinding with TSV and microbumps
720μm
560μm
48
Samsung Mass-Produces Industry's First
TSV-based DDR4 DRAM (August 27, 2014)
Server Farm
 The 64GB DDR4 DRAM module consists of 36 DDR4 DRAM chips,

each of which consists of four 4-gigabit (Gb) DDR4 DRAM dies.
 Use Samsung’s 20nm process technology and 3D TSV packaging
technology.
 Perform twice as fast as a module that uses wire bonding
packaging, while consuming approximately half the power.
49
Samsung
Flash interposer
PCB
50
Hybrid Memory Cube
(HMC)
51
Over-Mold Underfill
Microbump DRAMs
TSV Logic
TSV Controller
Organic Substrate
The HMC consortium already has 8 members:
 Micron
DRAM Layers
 Samsung (Memory cube)
 Altera
 ARM
 IBM
 Open-Silicon
 SK Hynix
 Xilinx
Logic Controller
The SPEC was published on April 2, 2013 and is primarily targeted at:
 HPC (high performance computing)
 Networking
 Energy,
 Wireless communications
 Transportation
 Security
 High-end servers
More than 120 adopters! 53
Hybrid Memory Cube (HMC) Architecture
Each DRAM die is divided into 16 "cores" and then stacked. The logic base is at
the bottom, with 16 different logic segments, each segment controlling four (or
eight) DRAMs that sit on top. This type of memory architecture supports more
DRAM I/O pins and, therefore, more bandwidth (as high as 400GB/s). According to
the Hybrid Memory Cube Consortium, a single HMC can deliver more than 15X the
performance of a DDR3 module and consume 70% less energy per bit than DDR3.
2000+ TSVs on each DRAM
54
55
Hybrid Memory Cube
DRAM Layers
(Memory cube)
Logic
Controller
Micron fabricate
the memory cube
56
Hybrid Memory Cube
DRAM Layers
(Memory cube)
Logic
Controller
IBM fabricate the
Logic Controller
57
Micron’s First HMC Sample Shipped
in the Last Week of September 2013
 The hybrid memory cube is a 4-
DRAM (each one with 2000+
TSVs) on a logic controller
(which size is slightly larger
than the DRAMs) with TSVs
 The hybrid memory cube is on
an organic package substrate.
DRAM Stack  The TSV-DRAM is ~50-μm thick.
 The TSV-DRAM is with 20-μm
(tall) Cu pillar + solder cap.
 The memory cube is assembled
one DRAM at a time with
thermal compression bonding.
Package Substrate  The heat dissipation is from
10W to 20W.
 TSV diameter ~ 5 to 6-μm.
 Volume production will be in
next summer.
58
Altera’s Stratix V FPGA with Micron HMC
10/100/1000 Ethernet Connectors
Stratix V FPGA
ATX Form
Factor
Hybrid Memory
Cube (HMC)
ATX Power Supply

Connector
By providing equivalent bandwidth of
greater than eight (8) DDR4-2400 DIMMs
using a single HMC device.
Altera White Paper, “Addressing Next-Generation Memory
Requirements Using Altera FPGAs and HMC Technology”, Altera
Corporation, January 2014. 59
Intel’s “Knight’s Landing” with 8 HMC
Fabricated by Micron (2015 production)
 5X the bandwidth vs.
GDDR5
 Up to 16GB
 One-third the footprint
 Half the energy per bit
 Managed memory stack
for optimal levels of
reliability, availability and
serviceability
60 block
Rik Myslewski, “Intel teams with Micron on next-gen many-core Xeon Phi with 3D DRAM Introduces new 'fundamental building
of HPC systems' with Intel Omni Scale Fabric”, Posted in HPC, June 2014.
Fujitsu’s Tofu2 integrated Components: SPARC64 Xifx
and CPU Memory Board
 Three CPUs
 3 x 8 Hybrid Memory Cubes (HMCs)
32 + 2 core CPU
Hybrid Memory
Cube (HMC)
SPARC64 Xifx
CPU Memory
Board
Yoshida, “SPARC64 Xifx: Fujitsu’s next generation processor for HPC”,
Hot Chips: A Symposium on High Performance Chips, August 11,
2014. 61
Wide I/O DRAM
62
Wide I/O Single Date Rate
JEDEC Standard (JESD229), December 2011
Micron’s Target: 10mmx10mm Max.
Suggestion The minimum determined by contact grid
Memory
Target: 1mm
Cube with
TSVs
TSVs
Face-down
Contact Grid
Face-up
TSVs SoC with TSVs
Solder Balls C4 Bumps

(a)
63
(b)
Wide I/O 2
64
JEDEC Standard - Wide I/O 2
(JESD229-2, Wide I/O 2, August 29, 2014)
40µm
40µm
2880µm 1000µm
120µm
200µm
HIGH Bandwidth
Memory
(HBM)
66
High Bandwidth Memory (HBM) DRAM (Mainly for Graphic applications)
JEDEC Standard (JESD235), October 2013
HBM is designed to support bandwidth from 128GB/s to 256GB/s
Hynix’s
HMC
HBM DRAM
TSV
TSV/RDL Optional
Interposer GPU/CPU/SoC Base Chip
HBM Interface
PCBPCB
Underfill is needed between the interposer and the organic substrate. Also, underfill
is needed between the interposer and the GPU/CPU and the memory cube
67
Memory Stacking with TSVs
Memory Bandwidth Voltage Standard Applications
Structure (GBps) (V)
RDIMMs 153.6 1.2 DDR4 Servers, Cloud, data
center, etc.
Wide IO 2 68.3 1.1 JESD229-2 High-end
smartphones
HMC 160 to 320 1.2 HMC SPEC High-end servers,
networking, graphics,
HPC, FPGA, etc.
HBM 128 to 256 1.2 JESD235 High-end graphics,
networking, HPC, etc.
Samsung’s Widcon
(wide I/O connection)
Technology
69
(for Mobile DRAM and A8 Processor) inside iPhone 6 Plus
Top-side of the bottom PoP (426-ball)

(EDF8164A3PM-GD-F)
Application
Processor
Package Substrate for A8 processor
Apple’s application processor

Not-to-scale (POXY99001)
Mobile Application Processor (AP) Chip Set
(AP + LPDDR3)
(PoP vs. 3D IC Integration)
Wide I/O DRAMs PoP 3D IC Integration

Microbump TSV Wide I/O DRAMs

AP
AP
Package Substrate for AP Package Substrate for AP Chip Set
Samsung’s Widcon Technology

 Very low profile
 Widest memory bandwidth
 Lower power consumption
Samsung’s Widcon Technology vs. PoP
Samsung’s Widcon Technology vs. PoP
2.5D IC Integration
74
Flash interposer
PCB
75
On October 21, 2013 Xilinx and TSMC have jointly announced production release
of the Virtex-7 HT family, what the pair claims is the industry's first heterogeneous
3D ICs in production.
2FPGAs
TSV/RDL Interposer
Transceiver
The Xilinx Virtex-7 HT FPGAs feature up to sixteen, 28Gbps and seventy-two,

13.1Gbps transceivers. In addition to the Virtex-7 HT FPGAs, two other
homogeneous devices in the 3D IC family have been in volume production since
early 2013 – Virtex-7 2000T and Virtex-7 X1140T series.
4 FPGAs
TSV/RDL Interposer
http://press.xilinx.com/2013-10-20-Xilinx-and-TSMC-Reach-Volume-Production-on-all-28nm-CoWoS-based-All-Programmable-3D-IC-Families 76
Xilinx/TSMC’s 2.5D IC Integration with FPGA
Chip Chip
Interposer Metal
Layers
C4 Bumps Metal
Build-up Package Devices Contacts
PTH
Core (Cannot see)

Layers Substrate
Si
Solder
Balls Micro Cu
Bump Pillar
Solder
4RDLs
TSV
Interposer
RDLs: 0.4μm-pitch line width and spacing

Each FPGA has >50,000 μbumps on 45μm pitch
The package substrate is at least (5-2-5) Interposer is supporting >200,000 μbumps
77
Xilinx’s Passive Interposers with TSV and
RDL for Wide I/O Interface in FPGA Products
For better manufacturing
yield (to save cost), a very
large SoC has been sliced
into 4 smaller chips (2011)
(10,000+)
With 4 RDLs
78
Lau Lau, IEEE/ECTC2011 3D IC Integration PDC
Altera/TSMC’s 2.5D IC Integration with FPGA
Chip
Interposer
C4 Bumps
Package
Build-up Layers
Substrate
Solder
Balls
Solder Cu
Pillar
The package substrate is at least (6-2-6)

RDLs
4RDLs on top of
TSV
Interposer the interposer

and there isn’t
any at the bottom
79
2.5D IC Integration (Interposers)
Underfill UBM Cu Pillar
Chip 1 Chip 2 Solder
RDLs RDLs for lateral

(Redistribution communications
layers)
TSV Si
Underfill Interposer
UBM
Solder Bumps
Package Substrate Build-up

Layers
Solder Balls
Not-to-scale 80
Thus, passive TSV/RDL
interposers are for extremely fine-
pitch, high-I/O, high-performance,
and high-density semiconductor
IC applications.
81
Recent Advances in
Package substrates
 Coreless Substrates
 Build-Up Package Substrates

Coreless Substrates
83
Comparison between the Substrate with Build-up
Layers and Coreless Substrate
Conventional Build-up Coreless Package
Package substrate substrate
Chip
Underfill Chip
Bump
Underfil
Build-up Layers l
Bump
Filled Micro Via
Core
Build-up
Build-up Layers
Layers
Build-up Layers Filled Micro Via
Low Profile: Good for mobile products

84
Coreless Substrates
Advantages Disadvantages
Lower cost by eliminating the Larger warpage
core (because of low rigidity)
Better electrical performance New manufacturing
(good high-speed transmission infrastructure is necessary
characteristic)
Higher wiring ability Easier to have laminate
(by eliminating the core) chipping
Smaller form factor Poor solder joint yield
85
Build-up
Package Substrates
86
Development of Organic Multi Chip Package
for High Performance Application
N. Shimizu, W. Kaneda, H. Arisaka, M. Koizumi, S. Sunohara, A. Rokugawa,
and T. Koyama
Shinko Electric Industries Co., Ltd.
36 Kita Owaribe Nagano-shi, 381-0014, Japan
81-26263-4585, noriyoshi_shimizu@shinko.cp.jp
87
Shinko’s 4+(2-2-3) Thin-Film on Build-up Layer Test
Vehicle: 2μm Cu trace and 40μm pitch pad
Thin-Film
layers
Build-up 2μm line width/spacing

layers Core
40μm pad pitch
10μm stack via
100μm PTH 50μm build-

up via
 10μm stack via  10μm stack via

 2μm line width  11.8μm thick pad
 1.9μm spacing  25μm (dia.) Cu pad
 2μm thick Cu
88
Future Package Substrates
In general, a package substrate with 8-build-up-layer (4-2-4) and 20μm
line-width and spacing is more than adequate to support most of the
chips. Thus, interposers are not needed.
Also, in the past 3 years, Substrate Houses have been developing

package substrates with high build-up layers (5-2-5) and fine (12-15μm)
line-width and spacing.
Recently, Shinko’s thin-film layers on build-up layers can make 2μm line
width and spacing and 40μm pad pitch.
All these activities are keeping interposers away from volume

production, except for very niche (such as extremely high-performance,
high-density, and fine-pitch) applications.
89
Embedded
Interposer/Bridge
90
Multi-chips on a TSV interposer Semi-Embedded on
a Substrate/PCB with Stress Relief Gap
TSV
Underfill between the chips and

TSV interposer and the chips
and organic substrate/PCB is
necessary
The advantages of this design are:

(1) Low profile and low cost
(2) Free to use any Moore’s law chips without TSVs
(3) RDLs allow chip -to-chip short interconnect
(4) TSVs can be used for powers, grounds, and some signals
(5) Very reliable (because the stress relief gap reduces the thermal expansion mismatch
between the embedded TSV interposer and the organic substrate/PCB
Lau, J. H., S. T. Wu, and H. C. Chien, “Nonlinear Analyses of Semi-Embedded Through-Silicon Via (TSV) Interposer with Stress Relief Gap Under
Thermal Operating and Environmental Conditions”, IEEE EuroSime Proceedings, Chapter 11: Thermo-Mechanical Issues in Microelectronics,
Lisbon, Portugal, April 2012, pp. 1/6 – 6/6.
ITRI/Unimicron’s Packaging Substrate Having
Embedded Interposer and Fabrication Method
Thereof (US2013/0032390A1)
(Publication Date: Feb. 7, 2013, Filed Date: Aug. 3, 2012)
Intel’s Bridge Interconnect with Air Gap in Package
Assembly (US 2014/0070380A1)
(Publication Date: Mar. 13, 2014, Filed Date: Sept. 11, 2012)
Intel’s Bridge Interconnect with Air Gap in Package
Assembly (US 2014/0070380A1)
Intel Newsroom on Aug 27, 2014
(Publication Date: Mar. 13, 2014, Filed Date: Sept. 11, 2012)
RDL Via Bridge
Chip Chip Chip

Solder
Bumps
Substrate
Solder Balls
Solder Bumps Bridge RDL Air Gap
Embedded Multi-die Interconnect Bridge (EMIB)

3D MEMS and IC
Integration
95
Avago’s FBAR MEMS Filter with TSV
TSV
TSV
CAP
Rx die Tx die Au
TSV TSV
CAP CAP
96
Photo images of the FBAR hermetic package. (a) Cap wafer
with IC device, TSVs, internal connections, and cavity for the
FBAR. (b) FBAR wafer with FBAR, pads, internal connections,
and cavity for IC device
ICP TSV
Pad ICP
TSV Pad
TSV
TSV Pad
Pad
TSV ICP TSV
Pad
Pad
ICP
(a) Cap Wafer (b) FBAR Wafer
97
Top: IC cap wafer to FBAR wafer Au-Au bonding. (b) Cross section
SEM image of the bonded FBAR MEMS package with IC cap
Au Pads
TSV
TSV
IC Cap Wafer
FBAR
Circuit
FBAR Wafer
Au Pads Au
TSV
IC Cap Wafer
Circuit
FBAR
FBAR Wafer
300µm
98
3D CIS and IC
Integration
99
Front-illuminated (FI) CIS. Some of the
lights are blocked (reflected) by the
transistors and metal wirings
Light
Micro Lens
Color Filter
Transistors
and Metal
Wiring
Line of receiving surface
PD
Si-Substrate
100
(TOP) Schematic of Back-illuminated (BI) CIS. (Bottom) Cross section SEM image of a BI-CIS
Light
Micro Lens
Line of receiving
surface Color Filter Backside
PD
Si-substrate
Transistors
and Metal
Wiring
Micro Lens
Line of receiving Color Filter
surface Backside
PD
Si-substrate
101
SONY’s BI-CIS: conventional vs. new 3D stacking
Pixels
Pixels
Circuits
Circuits
Supporting Logic Process
Substrate (Si) Substrate (Si)
Conventional BI-CIS New Stacked BI-CIS
102
3D CIS pixel chip and logic IC integration
103
CIS (insulator) wafer to logic (insulator) wafer bonding
On chip color filter and micro lens

BI-CIS
Process CIS (Si)
Technology
W2W CIS (Insulator)

Bonding Surface
Logic (Insulator)
Logic
Process
Technology
Logic (Si)
50µm
104
TSVs connecting the CIS pixel chip and the
logic circuit chip
On chip color filter and micro lens
CIS (Si)
Logic (Si)
TSV
105
SUMMARY AND RECOMMENDATION
(3D IC Integration)
TSVs straight through the same memory chips to:
 enlarge the memory capacity
 lower the power consumption
 increase the bandwidth
 lower the latency (enhance electrical performance)
 reduce the form factor
will be the major applications of 3D IC Integration!
Memory chip stacking with TSV has been in production for servers by
Samsung.
The Hybrid Memory Cube (HMC) will be used by Intel, Altera, Fujitsu,
etc. this year for high performance products!
The High Bandwidth Memory (HBM) will be used by Hynix, AMD, Nvidia,
etc. for graphic applications.
106
(2.5D IC Integration - Interposers)
 In general, interposers are for extremely high-I/O, high-performance,
high-density, and fine-pitch semiconductor IC applications.
 In general, the build-up package substrates are more than adequate

to support the semiconductor IC chips in high-end smartphones
and an interposer is not necessary.
 Thin-film RDLs on top of the build-up package substrate invented

by Shinko is the right way to go. The industry should strive to
commercialize it.
 Try not to use the interposer unless the build-up package

substrates are not adequate to support the very high I/O, high-
performance, high-density, and fine-pitch chips. Now, with the thin-
film RDLs on top of the build-up package substrate, the high-
volume production of interposer will be pushed out even further.
107
(3D IC Packaging)
3D IC Packaging such as
 Stacked dies with wire bonding
 PoP
have been and will be used for mobile
products such as smartphones and tablets.
3D Chip-to-Chip and Face-to-Face will soon

be used for mid-range performance
applications.
108
(eWLP)
 eWLP is expected to grow substantially in the next few
years.
 Most of the OSATs (the top 6) are developing their eWLP
technologies.
 eWLP package is just right for smaller size of chip.
 eWLP package is just right for smartphones, tablets, and
wearables because it is low profile, light weight, and low
cost.
 eWLP package cannot house very large chips (e.g.,
15mm x 15mm) like the PBGA package.
 eWLP package size cannot be too big (e.g., 45mm x
45mm like the PBGA package.
109
ACKNOWLEDGEMENTS
The author would like to thank his
colleagues at IME, HKUST, ITRI, ASM
and throughout the packaging
community for their useful help,
strong support, and stimulating
discussions.
110
Thank You Very Much for Your
Attention!

111

1817-SanDiegoCPMTDL Lau Advancedpackaging

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3D IC Packaging

CPMT Distinguish Lecture, San Diego Chapter, February 23, 2015 1

Die Active applied R&D is

Die attach Chip 1

SK Hynix’s MLC (Multi Level Cell) 8GB (Gigabyte)

Apple’s A7 processor Elpida’s 1GB LPDDR3

2-2-2 Build-up package substrate

Top-side of the bottom PoP (426-ball)

Elpida’s 1GB LPDDR3

Package Substrate for LPDDR3

Package Substrate for A8 processor

Apple’s application processor

Elpida’s 1GB LPDDR3

Package Substrate for LPDDR3 Package Substrate for LPDDR4

Package Substrate for A8 processor Package Substrate for A9 processor

A8 application processor A9 application processor

A 40% PCB saving! PCB

Daughter Chip Solder Bump

Rigid or Flex Substrate

Chip-to-Chip and Face-to-Face

Wire bonds Face-to-face (Chip-to-chip)

100 to 125μm a spacer die

Samsung 1-Gb wide I/O SDRAM

Heat spreader cap ASIC

Heat spreader cap

Package Substrate ASIC

FPGA ASIC 40μm-pitch Cu-pillar + 200μm-pitch Cu-

Schematic process flow for a fan-out

Mold Baseband SoC

RDLs Solder ball

Infineon’s chip is a wireless baseband SoC with multiple integrated

LGE (wireless baseband), Samsung (baseband modem), and Nokia

Infineon eWLB (wireless operation acquired by Intel in 2011)

Place die active side down on substrate and encapsulated

Remove substrate and turn the whole around

Redistribute signal, power and ground 200mm RCP panel with 82

Deposit BGA solder balls

A 208 I/O 13mmx13mm PBGA with 0.65mm pitch can

Underfill Molded Compound Substrate

Solder Balls Solder Bumps

Eliminate solder bumps, underfill, and package substrate.

At the TSMC Technology Symposium in San Jose, CA in April

Sputter the Ti/Cu

Through Mold MC Bottom

SEMICON West 2013 36

Wire Bonds Memory Chips

Solder Redistribution Substrate Through Mold Vias

Die Active applied R&D is

Wirebonds are replaced by TSVs

 Wide I/O DRAM, Wide I/O 2, or

 High Bandwidth Memory (HBM)

“Another direction of improvement (of computing

TSVs straight through the same memory chips to:

Organic Package Substrate

8-stack chips (50μm each) connected

 The 64GB DDR4 DRAM module consists of 36 DDR4 DRAM chips,

Organic Package Substrate

2000+ TSVs on each DRAM

ATX Power Supply

Hybrid Memory Cube (HMC)

Solder Balls C4 Bumps

Organic Package Substrate

Top-side of the bottom PoP (426-ball)