library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity DFF is

Port ( Q : out STD_LOGIC;

QBAR : out STD_LOGIC;

D : in STD_LOGIC;

CLK : in STD_LOGIC);

end DFF;

architecture Behavioral of DFF is

signal TEMP: STD_LOGIC;

begin

process(Temp,CLK)

BEGIN

if(CLK = '1' AND rising_edge(CLK)) THEN

TEMP<= D;

else TEMP <= TEMP;

End if;

Q <= TEMP;

QBAR <= NOT TEMP;

End Process;

end Behavioral;