Vous êtes sur la page 1sur 8

The figure depicts 8085 pin diagram. 8085 microprocessor has 40 pins.

It uses +5V
supply and runs on maximum frequency of about 3 MHz The pins on 8085 chip can be
grouped into 6 groups:

 Address Bus
 Data Bus
 Control and Status Signals
 Power supply and frequency
 Externally Initiated Signals
 Serial I/O ports

8085 Pin Description


There are bi-directional. They serve as address and data
bus. During the instruction execution, these lines act as
AD0 to AD7
address bus initially and later serve as data bus lines.
Externally Latch is interfaced with these lines.
A8 to A15 These are address bus lines which are uni-directional.
(Address Latch Enable), it is a pulse which holds value 1
when AD-AD7 lines are used as address bus. It takes value
ALE
0 after this. This is used to enable latch connected
externally.
RD' Read signal which is active low.
WR' Write signal which is active low.
This signal specifies whether the operation is a memory
IO/M'
operation(IO/M' = 0) or a I/O operation (IO/M' = 1).
These are status signals which specify kind of operation
being performed by 8085 microprocessor.
S1 S0 Function
S1, S0 0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH
Serial Input Data line. The data on this line is loaded into
SID
accumulator bit-7 whenever a RIM instruction is executed.
Serial Output Data line. The output SOD is set or reset as
SOD
specified by SIM instruction.
Input,Interrupt Request. It is used as a general purpose
interrupt. INTR is enabled and disabled by the software. It
INTR
is disabled by reset and immediately after an interrupt is
accepted.
Output, Interrupt acknowledge; It is used instead of RD
during instruction cycle after an INTR is accepted. It can be
INTA'
used to activate 8259 interrupt chip or some other
interrupt port.
These are three inputs which have same timing as INTR
except they cause internal RESTART to be automatically
RST5.5,RST6.5,RST7.5
inserted. RST 7.5 has highest priority, RST 5.5 has lowest
priority. These interrupts have higher priority than INTR.
Input, TRAP interrupt is a non-maskable restart interrupt. It
TRAP
is unaffected by any mask or interrupt enable. It has
highest priority of any interrupt.
Reset sets the Program Counter (PC) to zero. It resets
interrupt enable and HLDA flip-flops. None of the other
RESET IN (Input)
flags or registers are affected. CPU is held in reset
condition as long as RESET is applied.
Indicates CPU is being reset. It can be used as system
RESET OUT (Output)
RESET. The signal is synchronized to the processor clock.
An output clock pin to drive the clock of the rest of the
CLK OUT
system.
If this signal is high during a read or write cycle, it indicates
that memory or peripheral is ready to send or receive data.
READY (Input)
If READY is low, CPU will wait for READY to go HIGH before
completing the read or write cycle.
HOLD indicates that another MASTER is requesting the use
of Address and Data Buses. The microprocessor (CPU) upon
receiving the Hold request. will relinquish the use of buses
HOLD (input)
as soon as the completion of the current machine cycle.
Internal processing can continue. The processor can regain
the buses only after the Hold is removed.
HOLD ACKNOWLEDGE
It indicates that the CPU has received the Hold request and
HLDA (Output) will relinquish the buses in the next clock cycle. HLDA goes
low after the Hold request is removed. The CPU takes the
buses one half clock cycle after HLDA goes low.
VCC +5V supply
VSS Ground Reference
X1,X2 These signals are inputs from crystal or clock generator.

8085 Bus Concept


The microprocessor MPU performs various operations with peripheral devices or a
memory location by using three sets of communication lines called buses: the address
bus, the data bus and the control bus. And these three combined lines is called as
system bus.
Address bus:
The address bus is a group of 16 lines generally called as A0 – A15 to carry a 16-bit
address of memory location. In a computer system, each peripheral or memory location
is identified by a binary number called an address. This is similar to the postal address
of a house.
The address bus is unidirectional, that means bit flow in only one direction from MPU to
peripheral. MPU carries 16-bit address i.e. 216 = 65,536 or 64K memory locations.

The 8085 Bus Structure


Data Bus:
The data bus is a group of eight bidirectional lines used for data flow in both the
directions between MPH and peripheral devices. The 8 data lines are manipulating 8-bit
data ranging from 00 to FF i.e. (28 = 256) numbers from 0000 0000 -1111 1111
This 8 bit data is called as word length and the register size of a microprocessor and
MPH is called 8–bit microprocessor.
Control bus:
Control bus is having various single lines used for sending control signals in the form of
pulse to the memory and I/O devices. The MPU generates specific control signals to
perform a particular operations. Some of these control signals are memory read,
memory write, I/O read and I/O write.

8085 Architecture and Functional description


The architecture of.8085 is shown in figure given below. The internal architecture of
8085 includes the ALU, timing and control unit, instruction register and decoder, register
array, interrupt control and serial I/O control.
 Processing Unit consists of ALU, Accumulator, Status FLags and Temporary
Register.
 Instruction Unit consists of Instruction register, Instruction Decoder, Timing and
Control Unit.
 Storage and Interface Unit consists of general purpose regsiters, stack pointer
(SP), program counter(PC), Increment/Decrement Register, Address Latch,
Address/Data Latch.
 The other three units are Interrupt Controller, Serial I/O Controller and Power
Supply unit as shown in the figure.

Operations Performed by 8085


The ALU performs the arithmetic and logical operations. The operations performed by
ALU of 8085 are addition, subtraction, increment, decrement, logical AND, OR, EXCL
U8IVE -OR, compare, complement and left / right shift. The accumulator and temporary
register are used to hold the data during an arithmetic / logical operation. After an
operation the result is stored in the accumulator and the flags are set or reset according
to the result of the operation.
FLAG REGISTER: There are five flags in 8085, which are sign flag (8), zero flag (Z),
auxiliary carry flag (AC), parity flag (P) and carry flag (CY). The bit positions reserved
for these flags in the flag register are shown in figure below.

After an ALU operation, if the most significant bit of the result is 1, then sign flag is set.
The zero flag is set, if the ALU operation results in zero and it is reset if the result is
non-zero. In an arithmetic operation, when a carry is generated by the lower nibble, the
auxiliary carry flag is set. After an arithmetic or logical operation, if the result has an
even number of 1 's the parity flag is set, otherwise it is reset. If an arithmetic operation
results in a carry, the carry flag is set otherwise it is reset.
Among the five flags, the AC flag is used internally for BCD arithmetic and other four
flags can be used by the programmer to check the conditions of the result of an
operation.
TIMING & CONTROL UNIT: The timing and control unit synchronizes all the
microprocessor operations with the clock and generates the control signals necessary
for communication between the microprocessor and peripherals. It provides timing and
control signal to the microprocessor to perform operations. Following are the timing and
control signals, which control external and internal circuits −

 Control Signals: READY, RD’, WR’, ALE


 Status Signals: S0, S1, IO/M’
 DMA Signals: HOLD, HLDA
 RESET Signals: RESET IN, RESET OUT

INTERRUPT CONTROL
As the name suggests it controls the interrupts during a process. When a
microprocessor is executing a main program and whenever an interrupt occurs, the
microprocessor shifts the control from the main program to process the incoming
request. After the request is completed, the control goes back to the main program.
There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST
5.5, TRAP.
SERIAL INPUT/OUTPUT CONTROL
It controls the serial data communication by using these two instructions: SID (Serial
input data) and SOD (Serial output data).
ADDRESS BUFFER AND ADDRESS-DATA BUFFER
The content stored in the stack pointer and program counter is loaded into the address
buffer and address-data buffer to communicate with the CPU. The memory and I/O
chips are connected to these buses; the CPU can exchange the desired data with the
memory and I/O chips.
ADDRESS BUS AND DATA BUS
Data bus carries the data to be stored. It is bidirectional, whereas address bus carries
the location to where it should be stored and it is unidirectional. It is used to transfer the
data & Address I/O devices.
INSTRUCTION REGISTER & DECODER: When an instruction is fetched from memory
it is placed in instruction register. Then it is decoded and encoded into various machine
cycles.
REGISTER ARRAY:
 Apart from Accumulator (A-register), there are six general-purpose programmable
registers B, C, D, E, H and L.
 They can be used as 8-bit registers or paired to store l6-bit data. The allowed pairs
are B-C, D-E and H-L.
 The temporary registers W and Z are intended for internal use of the processor and
it cannot be used by the programmer.
 STACK POINTER (SP):
The stack pointer SP, holds the address of the stack top. The stack is a sequence of
RAM memory locations defined by the programmer. The stack is used to save the
content of registers during the execution of a program.

 PROGRAM COUNTER (PC):


The program counter (PC) keeps track of program execution. To execute a program
the starting address of the program is loaded in program counter. The PC sends out
an address to fetch a byte of instruction from memory and increment its content
automatically. Hence, when a byte of instruction is fetched, the PC holds the
address of the next byte of the instruction or next instruction.

 INCREMENT OR DECREMENT REGISTER:


The 8-bit register contents or else a memory position can be increased or decreased
with one. The 16-bit register is useful for incrementing or decrementing program
counters as well as stack pointer register content with one. This operation can be
performed on any memory position or any kind of register.

INSTRUCTION EXECUTION AND DATA FLOW in 8085

 The program instructions are stored in memory, which is an external device.


 To execute a program in 8085, the starting address of the program should be loaded
in program counter.
 The 8085 output the content of program counter in address bus and asserts read
control signal low. Also, the program counter is incremented.
 The address and the read control signal enable the memory to output the content of
memory location on the data bus.
 Now the content of data bus is the opcode of an instruction. The read control signal
is made high by timing and control unit after a specified time.
 At the rising edge of read control signals, the opcode is latched into microprocessor
internal bus and placed in instruction register.
 The instruction-decoding unit, decodes the instructions and provides information to
timing and control unit to take further actions.

Z(8)
TEMP. REG.