Verilog

Share5 Code for Synchronous FIFO

Sr. No. Name of the Pin Direction Width Description
1 Rst_a Input 1 Reset Input
2 Clk Input 1 Clock Input
3 wr_en Input 1 when high write into
fifo
4 rd_en input 1 when high read from
memory
5 Data_in Input 4 Data Input
6 Data_out Output 4 Data output
7 Full Output 1 Fifo status
1 if fifo is full
8 Empty Output 1 Fifo status
1 if fifo is empty

module sync_fifo (data_out,full,empty,data_in,clk,rst_a,wr_en,rd_en);

//---------------parameter declaration
parameter data_width = 4;
parameter address_width = 4;
parameter ram_depth =16;

//--------------input output port declaration

output [data_width-1:0] data_out;
output full;
output empty;
input [data_width-1:0] data_in;
input clk;
input rst_a;
input wr_en;
input rd_en;

//--------------internal register declaration

reg [address_width-1:0] wr_pointer;
reg [address_width-1:0] rd_pointer;
reg [address_width:0] status_count;
reg [data_width-1:0] data_out;
wire [data_width-1:0] data_ram;

//--------------wr_pointer pointing to write address

always @ (posedge clk, posedge rst_a)
begin
if (rst_a)
wr_pointer = 0;
 else
if (wr_en)
wr_pointer = wr_pointer+1;
end
//-------------rd_pointer points to read address
always @ (posedge clk, posedge rst_a)
begin
if (rst_a)
rd_pointer = 0;
else
if (rd_en)
rd_pointer = rd_pointer+1;
end
//-------------read from FIFO
always @ (posedge clk, posedge rst_a)
begin
if (rst_a)
data_out=0;
else
if (rd_en)
data_out=data_ram;
end

//--------------Status pointer for full and empty checking

always @ (posedge clk, posedge rst_a)
begin
if (rst_a)
status_count = 0;
else
if (wr_en & & rd_en & & (status_count! = ram_depth))
status_count = status_count + 1;
else
if (rd_en & & wr_en & & (status_count! = 0))
status_count = status_count - 1;
end // always @ (posedge clk, posedge rst_a)

assign full = (status_count == (ram_depth));

assign empty = (status_count == 0);

memory_16x4 # (data_width, address_width, ram_depth) u1

(.address_1(wr_pointer),.address_2(rd_pointer),.data_1(data_in),.data_2(data_ram),.wr_en1(wr_en),.
rd_en2(rd_en),.clk(clk));

endmodule // sync_fifo
Design 4-bit Linear Feedback Shift Register (LFSR) using Verilog Coding and Verify with Test
Bench
Share8
Linear Feedback Shift Register is a sequential shift register with combinational feedback logic around
it that causes it to pseudo randomly cycle through a sequence of binary values. Feedback around
LFSR's shift register comes from a selection of points in the register chain and constitute either XORing
or XNORing these points to provide point back into the register. The LFSR basically loops through
repetitive sequences of pseudo random values. The maximum length of sequence is (2^n) - 1. Find out
VHDL Code Here.

module lfsr (out, clk, rst);

output reg [3:0] out;

input clk, rst;

wire feedback;

assign feedback = ~ (out[3] ^ out[2]);

always @(posedge clk, posedge rst)

begin
if (rst)
out = 4'b0;
else
out = {out[2:0],feedback};
end
endmodule

RTL view of LFSR is given below. Above code is synthisized by Xilinx Vivado tool.

RTL view of Linear Feedback Shift Register

Test Bench code for above design is given below

`timescale 1ns / 1ps

module lfsr_tb();
reg clk_tb;
reg rst_tb;
wire [3:0] out_tb;

initial
begin
clk_tb = 0;
rst_tb = 1;
#15;

rst_tb = 0;
 #200;
end

always
begin
#5;
clk_tb = ~ clk_tb;
end

lfsr DUT(out_tb,clk_tb,rst_tb);
endmodule

Above Test Bench code is simulated and waveform result is shown below.

Waveform of LFSR Test Bench

VHDL
Share6Code for 8-bit Barrel Shifter
Sr. No. Name of the Pin Direction Width Description
1 d_in Input 8 data input
2 Shift_by Input 3 shift amount
3 Rst_a Input 1 Reset signal
4 Clk Input 1 Clock signal
5 Shift_lt_rt Input 1 ‘0’=shift left
‘1’=shift right
6 P_load Input 1 ‘1’=receive input data
‘0’=discard input data
7 D_out Output 8 Parallel data output
Barrel shifter takes parallel data input and give shifted output either in left or right direction by a specific
shift amount. When shift_by input is “000” it will place input data at the output without shifting. For
specifying shifting direction shift_lt_rt pin is used. When it is ‘0’ the block will perform left shift operation
and when it is ‘1’, it will perform right operation. Find out Test Bench here.
Design Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity barrel_shifter is

port (
d_in : in std_logic_vector(7 downto 0); -- input vector
d_out : out std_logic_vector(7 downto 0); -- shifted output
shift_lt_rt : in std_logic; -- 0=>left_operation 1=>right_operation
shift_by : in std_logic_vector(2 downto 0); -- shift amount
clk : in std_logic; -- clock signal
rst_a : in std_logic; -- reset signal
p_load : in std_logic); -- parallel load

end barrel_shifter;

architecture beh of barrel_shifter is

begin -- beh
p1: process (clk,rst_a,shift_by,shift_lt_rt)
variable x,y : std_logic_vector(7 downto 0);
variable ctrl0,ctrl1,ctrl2 : std_logic_vector(1 downto 0);
begin -- process p1

ctrl0:=shift_by(0) & shift_lt_rt;

ctrl1:=shift_by(1) & shift_lt_rt;
ctrl2:=shift_by(2) & shift_lt_rt;

if(rst_a = '1') then

d_out<="00000000";
elsif(clk'event and clk = '1') then
 if (p_load='0')then
assert(false) report "Parallel load low" severity warning;
elsif(shift_lt_rt='1')then
assert(false) report "right shift" severity warning;
elsif(shift_lt_rt='0')then
assert(false) report "left shift" severity warning;
end if;

if p_load='1' then
case ctrl0 is
when "00"|"01" =>x:=d_in ;
when "10" =>x:=d_in(6 downto 0) & d_in(7); --shift left by 1 bit
when "11" =>x:=d_in(0) & d_in(7 downto 1); --shift right by 1 bit
when others => null;
end case;
case ctrl1 is
when "00"|"01" =>y:=x;
when "10" =>y:=x(5 downto 0) & x(7 downto 6); --shift left by 2 bits
when "11" =>y:=x(1 downto 0) & x(7 downto 2); --shift right by 2 bits
when others => null;
end case;
case ctrl2 is
when "00"|"01" =>d_out<=y ;
when "10"|"11" =>d_out<= y(3 downto 0) & y(7 downto 4); --shift right/left by 4 bits
when others => null;
end case;
end if;
end if;
end process p1;
end beh;
Design
Share5 Round Robin Arbiter using Verilog FSM Coding with Variable Slice Period

Sr. No. Name of the Pin Direction Width Description

1 Clk Input 1 Clock Signal
2 Rst Input 1 Reset Signal
3 Req Input 4 4 Request Signals
4 Grant Output 4 4 Grant Signals

Round-robin (RR) is one of the simplest scheduling algorithms for processes in an operating system.
As the term is generally used, time slices are assigned to each process in equal portions and in circular
order, handling all processes without priority (also known as cyclic executive). Round-robin scheduling
is simple, easy to implement, and starvation-free. Round-robin scheduling can also be applied to other
scheduling problems, such as data packet scheduling in computer networks. In this Arbiter, we have
included one two bit counter. This counter will count no. of clock pulses for grant period of each request
signal. In this if in between of counter, the request signal goes low, then grant will be given to other
respective request signal and we can save that time slice.

module round_robin(clk,rst,req,grant);

output [3:0] grant;

reg grant;
input clk;
input rst;
input [3:0] req;

reg [2:0] state;

reg [2:0] next_state;
reg [1:0] count;

parameter [2:0] s_ideal=3'b000;

parameter [2:0] s0=3'b001;
parameter [2:0] s1=3'b010;
parameter [2:0] s2=3'b011;
parameter [2:0] s3=3'b100;

always @(posedge clk or posedge rst)

begin
if(rst)
state=s_ideal;
else
state=next_state;
end

always @(state,next_state,count)
 begin
case (state)
s0:
begin
if (req[0])
begin
if(count==2'b11)
begin
if (req[1])
begin
count=2'b00;
next_state=s1;
end
else if (req[2])
begin
count=2'b00;
next_state=s2;
end
else if (req[3])
begin
count=2'b00;
next_state=s3;
end
else
begin
count=2'b00;
next_state=s0;
end
end // if (count==2'b11)
else
begin
count=count+2'b01;
next_state=s0;
end // else: !if(count==2'b11)
end // if (req[0])
else if (req[1])
begin
count=2'b00;
next_state=s1;
end
else if (req[2])
begin
count=2'b00;
next_state=s2;
end
else if (req[3])
begin
count=2'b00;
 next_state=s3;
end
else
begin
count=2'b00;
next_state=s_ideal;
end
end // case: s0

s1:
begin
if (req[1])
begin
if (count==2'b11)
begin
if (req[2])
begin
count=2'b00;
next_state=s2;
end
else if (req[3])
begin
count=2'b00;
next_state=s3;
end
else if (req[0])
begin
count=2'b00;
next_state=s0;
end
else
begin
count=2'b00;
next_state=s1;
end
end // if (count==2'b11)
else
begin
count=count+2'b01;
next_state=s1;
end // else: !if(count==2'b11)
end // if (req[1])
else if (req[2])
begin
count=2'b00;
next_state=s2;
end
 else if (req[3])
begin
count=2'b00;
next_state=s3;
end
else if (req[0])
begin
count=2'b00;
next_state=s0;
end
else
begin
count=2'b00;
next_state=s_ideal;
end
end // case: s1

s2:
begin
if (req[2])
begin
if (count==2'b11)
begin
if (req[3])
begin
count=2'b00;
next_state=s3;
end
else if (req[0])
begin
count=2'b00;
next_state=s0;
end
else if (req[1])
begin
count=2'b00;
next_state=s1;
end
else
begin
count=2'b00;
next_state=s2;
end
end // if (count==2'b11)
else
begin
 count=count+2'b01;
next_state=s2;
end // else: !if(count==2'b11)
end // if (req[2])
else if (req[3])
begin
count=2'b00;
next_state=s3;
end
else if (req[0])
begin
count=2'b00;
next_state=s0;
end
else if (req[1])
begin
count=2'b00;
next_state=s1;
end
else
begin
count=2'b00;
next_state=s_ideal;
end
end // case: s2

s3:
begin
if (req[3])
begin
if (count==2'b11)
begin
if (req[0])
begin
count=2'b00;
next_state=s0;
end
else if (req[1])
begin
count=2'b00;
next_state=s1;
end
else if (req[2])
begin
count=2'b00;
next_state=s2;
 end
else
begin
count=2'b00;
next_state=s3;
end
end // if (count==2'b11)
else
begin
count=count+2'b01;
next_state=s3;
end // else: !if(count==2'b11)
end // if (req[3])
else if (req[0])
begin
count=2'b00;
next_state=s0;
end
else if (req[1])
begin
count=2'b00;
next_state=s1;
end
else if (req[2])
begin
count=2'b00;
next_state=s2;
end
else
begin
count=2'b00;
next_state=s_ideal;
end
end // case: s3

default:
begin
if (req[0])
begin
count=2'b00;
next_state=s0;
end
else if (req[1])
begin
count=2'b00;
next_state=s1;
end
 else if (req[2])
begin
count=2'b00;
next_state=s2;
end
else if (req[3])
begin
count=2'b00;
next_state=s3;
end
else
begin
count=2'b00;
next_state=s_ideal;
end
end // case: default
endcase // case (state)
end // always @ (state,next_state,count)

always @(state,next_state,count)
begin
case (state)
s0:begin grant=4'b0001; end
s1:begin grant=4'b0010; end
s2:begin grant=4'b0100; end
s3:begin grant=4'b1000; end
default:begin grant=4'b0000; end
endcase // case (state)
end
endmodule
Design
Share3 8x3 Priority Encoder in Verilog Coding and Verify with TestBench
Priority Encoder allocates priority to each input. Design and Test Bench code of 8x3 Priority Encoder is
given below. Output are set according to priorities of inputs. So if input with higher priority is present
then inputs with lower priorities are ignored and generates output according to highest priority input.
S. Name Direction Width Remark
No.
1. D_in IN 8 bit Input lines
3. D_out OUT 3 bit Output lines

Design Code

module prio_enco_8x3(d_out, d_in);

output [2:0] d_out;

input [7:0] d_in ;

assign d_out = (d_in[7] ==1'b1 ) ? 3'b111:

(d_in[6] ==1'b1 ) ? 3'b110:
(d_in[5] ==1'b1 ) ? 3'b101:
(d_in[4] ==1'b1) ? 3'b100:
(d_in[3] ==1'b1) ? 3'b011:
(d_in[2] ==1'b1) ? 3'b010:
(d_in[1] ==1'b1) ? 3'b001:
(d_in[0] ==1'b1) ? 3'b000: 3'bxxx;

endmodule

Above code is synthesized by Xilinx Vivado and RTL view of Priority Encoder is shown below.

RTL view of Priority Encoder

Test Bench Code

`timescale 1ns/1ps
module prio_enco_8x3_tst;
reg [7:0] d_in;
wire[2:0] d_out;

prio_enco_8x3 u1 (.d_out(d_out), .d_in(d_in) );

initial
begin
d_in=8'b11001100;
#10;
 d_in=8'b01100110;
#10;
d_in=8'b00110011;
#10;
d_in=8'b00010010;
#10;
d_in=8'b00001001;
#10;
d_in=8'b00000100;
#10;
d_in=8'b00000011;
#10;
d_in=8'b00000001;
#10;
d_in=8'b00000000;
# 10;
$stop;
end // initial begin
endmodule
Above design code is simulated using given Test Bench code by Xilinx Vivado and Simulated waveform
is shown below.

Waveform of Priority Encoder

Verilog
Share7 Code for Vending Machine Using FSM
Sr. No. Name of the Pin Direction Width Description
1 Nw_pa Output 1 News Paper Signal
2 Coin Input 2 Only two Coins,
5 =2’b01
10 =2’b10
0 =2’b00
3 Clk Input 1 Clock Signal
4 Rst Input 1 Reset Signal

In this wending machine, it accepts only two coins, 5 point and 10 point. Whenever total of coins equal
to 15 points, then nw_pa signal will go high and user will get news paper. It will not return any coin, if
total of points exceeds 15 points.
Design Code

module vending_machine(nw_pa,clk,coin,rst);

output reg nw_pa;

input [1:0] coin;
input clk,rst;
reg [1:0] state;
reg [1:0] next_state;

parameter [1:0] s0=2'b00;

parameter [1:0] s5=2'b01;
parameter [1:0] s10=2'b10;
parameter [1:0] s15=2'b11;

always @(posedge clk)

begin
if (rst)
state=s0;
else
state=next_state;
end

always @(state,coin)
begin
case (state)
s0:
begin
if (coin==2'b00)
next_state=s0;
else
if (coin==2'b01)
next_state=s5;
else
 if (coin==2'b10)
next_state=s10;
end
s5:
begin
if (coin==2'b00)
next_state=s5;
else
if (coin==2'b01)
next_state=s10;
else
if (coin==2'b10)
next_state=s15;
end
s10:
begin
if (coin==2'b00)
next_state=s10;
else
if (coin==2'b01)
next_state=s15;
else
if (coin==2'b10)
next_state=s15;
end
s15:
begin
next_state=s0;
end
default : next_state=s0;

endcase // case (state)

end // always @ (state,next_state)

always @(state)
begin
case (state)
s0 : nw_pa<=1'b0;
s5 : nw_pa<=1'b0;
s10: nw_pa<=1'b0;
s15: nw_pa<=1'b1;
default: nw_pa<=1'b0;
endcase // case (state)
end

endmodule
Design Traffic Light Controller using Verilog FSM Coding and Verify with Test Bench
Given below code is design code for Traffic Light Controller using Finite State Machine(FSM). In this
clk and rst_a are two input signal and n_lights, s_lights, e_lights and w_lights are 3 bit output signal. In
output signal, "001" represents Green light, "010" represents Yellow light and "100" represents Red
light. On the reset signal, design will enter into north state and start giving output after reset will go low.
Design will turn on Green light for eight clock cycles and Yellow light for four clock cycles. Design will
start with north, then goes into south, then east and finally into west and by this it will keep going.

Sr. No. Name of the Pin Direction Width Description

1 n_lights Output 3 North Lights
(001 = Green,
010 = Yellow, 100 =
Red)
2 s_lights Output 3 South Lights
(001 = Green,
010 = Yellow, 100 =
Red)
3 e_lights Output 3 Eight Lights
(001 = Green,
010 = Yellow, 100 =
Red)
4 w_lights Output 3 West Lights
(001 = Green,
010 = Yellow, 100 =
Red)
5 clk Input 1 Clock Signal
6 Rst_a Input 1 Reset Signal

Design Code
module traffic_control(n_lights,s_lights,e_lights,w_lights,clk,rst_a);

output reg [2:0] n_lights,s_lights,e_lights,w_lights;

input clk;
input rst_a;

reg [2:0] state;

parameter [2:0] north=3'b000;

parameter [2:0] north_y=3'b001;
parameter [2:0] south=3'b010;
parameter [2:0] south_y=3'b011;
parameter [2:0] east=3'b100;
parameter [2:0] east_y=3'b101;
parameter [2:0] west=3'b110;
parameter [2:0] west_y=3'b111;

reg [2:0] count;

always @(posedge clk, posedge rst_a)

begin
if (rst_a)
begin
state=north;
count =3'b000;
end
else
begin
case (state)
north :
begin
if (count==3'b111)
begin
count=3'b000;
state=north_y;
end
else
begin
count=count+3'b001;
state=north;
end
end

north_y :
begin
if (count==3'b011)
begin
count=3'b000;
state=south;
end
else
begin
count=count+3'b001;
state=north_y;
end
end

south :
begin
if (count==3'b111)
begin
count=3'b0;
state=south_y;
end
else
begin
count=count+3'b001;
state=south;
end
 end

south_y :
begin
if (count==3'b011)
begin
count=3'b0;
state=east;
end
else
begin
count=count+3'b001;
state=south_y;
end
end

east :
begin
if (count==3'b111)
begin
count=3'b0;
state=east_y;
end
else
begin
count=count+3'b001;
state=east;
end
end

east_y :
begin
if (count==3'b011)
begin
count=3'b0;
state=west;
end
else
begin
count=count+3'b001;
state=east_y;
end
end

west :
begin
if (count==3'b111)
begin
 state=west_y;
count=3'b0;
end
else
begin
count=count+3'b001;
state=west;
end
end

west_y :
begin
if (count==3'b011)
begin
state=north;
count=3'b0;
end
else
begin
count=count+3'b001;
state=west_y;
end
end
endcase // case (state)
end // always @ (state)
end

always @(state)
begin
case (state)
north :
begin
n_lights = 3'b001;
s_lights = 3'b100;
e_lights = 3'b100;
w_lights = 3'b100;
end // case: north

north_y :
begin
n_lights = 3'b010;
s_lights = 3'b100;
e_lights = 3'b100;
w_lights = 3'b100;
end // case: north_y

south :
 begin
n_lights = 3'b100;
s_lights = 3'b001;
e_lights = 3'b100;
w_lights = 3'b100;
end // case: south

south_y :
begin
n_lights = 3'b100;
s_lights = 3'b010;
e_lights = 3'b100;
w_lights = 3'b100;
end // case: south_y

west :
begin
n_lights = 3'b100;
s_lights = 3'b100;
e_lights = 3'b100;
w_lights = 3'b001;
end // case: west

west_y :
begin
n_lights = 3'b100;
s_lights = 3'b100;
e_lights = 3'b100;
w_lights = 3'b010;
end // case: west_y

east :
begin
n_lights = 3'b100;
s_lights = 3'b100;
e_lights = 3'b001;
w_lights = 3'b100;
end // case: east

east_y :
begin
n_lights = 3'b100;
s_lights = 3'b100;
e_lights = 3'b010;
w_lights = 3'b100;
end // case: east_y
endcase // case (state)
end // always @ (state)
endmodule

Above design code is synthesized by Xilinx Vovado and RTL view of design is shown below.

RTL view of Traffic Light Controller

Test Bench of above code is given below.

`timescale 1ns/1ps
module traffic_control_tb;

wire [2:0] n_lights,s_lights,e_lights,w_lights;

reg clk,rst_a;

traffic_control DUT (n_lights,s_lights,e_lights,w_lights,clk,rst_a);

initial
begin
clk=1'b1;
forever #5 clk=~clk;
end

initial
begin
rst_a=1'b1;
#15;
rst_a=1'b0;
#1000;
$stop;
end
endmodule
Test Bench is simulated using Xilinx Vivado and waveform is shown below