Mixed Signal LSI

Practical design method of

CMOS mixed signal circuits

Kanazawa University
Microelectronics Research Lab.
Akio Kitagawa
0.1 Introduction

2
 Books of reference
• For students who wants to learn the practical CMOS
analog circuit design Note 1
– R. Jacob Baker, CMOS: Circuit Design, Layout, and Simulation,
3rd Edition, ISBN 978-0-470-88132-3, Wiley-IEEE Press (2010)
– R. Jacob Baker, CMOS: Mixed-Signal Circuit Design, 2nd Edition,
ISBN 978-0-470-29026-2, Wiley-IEEE Press (2009)
• Course wares
– http://jaco.ec.t.kanazawa-u.ac.jp/edu/
– http://cmosedu.com/
Note 1:
These books does not cover the RF (Radio-frequency) circuits.
Book of reference for RF circuit design：
- RF Microelectronics, B. Razavi, ISBN 0-13-887571-5, Prentice Hall (1998)
- High-linearity CMOS RF Front-end Circuits, Yongwang Ding, ISBN
0387238018 , Springer (2004) 3
 Growing information technology toward
a real world and an daily life
Keywords: Wireless communication, Energy Harvesting, Sensor integration
An analog mixed signal (AMS) LSI is fundamental to advanced electronic systems.
Regional Information

Disaster
prevention
Distribution
Intelligent system
transport systems
Maintenance of Nursing-care
infrastructure
Cultivation
Conventional cyberspace

Environment
conservation
Medical services
Home safety and
automation Health care
4
The Internet of Everything
 Example of Mixed-Signal LSI
(RF signal generation) PLL DSM (Frequency control)

Other functions logic

(Impedance
LNA Amp., ADC Regulator Image rejection
matching)
Mixer (Analog-to- (Power Decimator
(Frequency Digital supply) Channel filter 5
conversion) conversion) Demodulator
Wave forms in mixed signal circuits
Continuous time (CT) Discrete time (DT)

Continuous time Discrete time

analog circuit analog circuit
Contin-
uous
value (Voltage, Current) (Voltage, Current, Charge)

Time domain Binary

Digital circuit
analog circuit b3
b2
b1
Discrete b0

value DSM
(Pulse width, Delay time)
(Pulse density, bits)
6
DSM: Delta-Sigma Modulation
 A/D partition in mixed-signal LSI
Name of circuit block Function Analog/Digital Remarks
AAF (Anti-Aliasing Filter) Band-limitation Analog feasible only in analog
SF (Smoothing Filter) Transformation from discrete time to Analog feasible only in analog
continuous time
LNA (Low Noise Amp.) Impedance matching Analog feasible only in analog
Mixer Down-conversion and Up-conversion Analog for RF signal
Digital for IF signal
Power supply circuits (e.g. Voltage regulation, DC-DC conversion, Analog
Regulator, Reference Voltage) Voltage/Current reference
ADC (Analog-to-Digital Converter) Analog-to-Digital conversion Analog + Digital
DAC (Digital-to-Analog Converter) Digital-to-Analog conversion Analog + Digital
PLL (Phase Locked Loop) RF frequency synthesis Analog or Digital
DSM (Delta-Sigma Modulator) Digital frequency control of PLL Digital
Memory（Sens-Amplifier, Memory Memory of digital data Analog + Digital
Cell, DLL）
Processor(DSP, MCU) Signal processing, system control Digital

Filter Hardware signal processing Analog for RF signal

Digital for baseband
7
 Digital design flow
Block diagram of system architecture Specification sheet for digital block
PHS PHS 規格値 設計値
DAC Wave DBP 項目 条件 単位
RFU IFU Min. Typ. Max. Min. Typ. Max.
Form I/F 電源電圧 1.8 3.3 3.5 1.8 2.1 3.3 V
GEN 消費電流 ― ― 2.2 mA
User 利得 ― 15 ― dB
Quad DSP
Mode ADC 周波数 300 426 475
Damed I/F 雑音指数（NF） ― 2 ― dB
IFU
1dBｺﾝﾌﾟﾚｯｼｮﾝﾚﾍﾞﾙ ― 0 ― dBm
GPS GPS CLK GPS ｲﾝﾀｾﾌﾟﾄﾎﾟｲﾝﾄ（IIP3） ― 9.6 ― dB
ADC 入力ｲﾝﾋﾟｰﾀﾞﾝｽ ― 50 ― Ω
RFU IFU GEN I/F
出力ｲﾝﾋﾟｰﾀﾞﾝｽ ― 500 ― Ω
端子間ｱｲｿﾚｰｼｮﾝ（OUT→IN） 20 dB
ETC ETC GPS PHS
RFU IFU Correrator I/F

ETC Demed ETC

I/F

HDL (Hardware Description language) Signal flow and transfer function

Logic Synthesis Place and Route Marge to analog blocks

8
 Analog design flow
Block diagram of system architecture Specification sheet for analog block
PHS PHS 規格値 設計値
DAC Wave DBP 項目 条件 単位
RFU IFU Min. Typ. Max. Min. Typ. Max.
Form I/F 電源電圧 1.8 3.3 3.5 1.8 2.1 3.3 V
GEN 消費電流 ― ― 2.2 mA
User 利得 ― 15 ― dB
Quad DSP
Mode ADC 周波数 300 426 475
Damed I/F 雑音指数（NF） ― 2 ― dB
IFU
1dBｺﾝﾌﾟﾚｯｼｮﾝﾚﾍﾞﾙ ― 0 ― dBm
GPS GPS CLK GPS ｲﾝﾀｾﾌﾟﾄﾎﾟｲﾝﾄ（IIP3） ― 9.6 ― dB
ADC 入力ｲﾝﾋﾟｰﾀﾞﾝｽ ― 50 ― Ω
RFU IFU GEN I/F
出力ｲﾝﾋﾟｰﾀﾞﾝｽ ― 500 ― Ω
端子間ｱｲｿﾚｰｼｮﾝ（OUT→IN） 20 dB
ETC ETC GPS PHS
RFU IFU Correrator I/F

ETC Demed ETC

I/F

Circuit schematic with behavior models Signal flow and transfer function

Circuit schematic with Transistors Layout artwork Marge to digital blocks

vｄｄ

M15
5/2
M14
M5 M6
5/2 M8 M9
5/2 5/2
5/2 Vbias 5/2

M3 M4
10.24/2 10.24/2
3.5kΩ 0.5pF 0.5pF
Vout- Vin+ M1 M2 Vin- Vout+
8.56/2 8.56/2

M16
8/2 M10 M7 M11
8/2 8/2 8/2

M17 M18 M12 M13

9
5/2 5/2 5/2 5/2
Vcm

gnd
 CAD software
Analog Circuits Digital Circuits
Schematic Editor Schematic Entry HDL Coding Text Editor

Circuit Simulator Circuit Simulation Logic Simulation HDL Simulator

Layout Editor Layout Artwork Logic Synthesis Logic Synthesis Tool

LPE Tool Layout Parasitic Extraction Timing Simulation HDL Simulator

LVS Tool Layout vs Schematic

(LVS) Place and Route P&R Tool

DRC Tool Design Rule Check Design Rule Check

(DRC) (DRC) DRC Tool

Mixed-signal integration

10
Structure of MOSFET and Bipolar Tr.
MOSFET Bipolar Tr.

base emitter collector

source gate drain

contact L Weff
tOX WB
n-Si n-Si
p-Si
SiO2 p-Si n-Si
n-Si substrate

WE: Emitter Width

Leff
Transition frequency fT depends on Leff. Transition frequency fT depends on WB.
NOTE: The peak transition frequency of bipolar transistor also depends on the base width
WB and the base resistance (small WE is better).
11
 1000
Trends of operating frequency
CMOS 11nm
16nm
High Speed Bipolar
32nm 22nm
45nm
65nm
100 130nm 90nm
Peak Transition frequency (GHz)

Bipolar
180nm

250nm
CMOS Amp., Mixer (20dB)
10
350nm
WLAN 802.11a
CMOS ADC, Small Digital
CDMA
1
Cellular Peak Transition Frequency:
The frequency for the current gain h21 = 1 (0dB)
of the transistor.
0.1
1996 2000 2004 2008 2012 2016 2020

Year ITRS 2008 12

 Performance of ADC architecture
Technology front is limited by GBP of amplifier, switching speed of CMOS-
switch, and process variation of capacitance.
10G

1G
Sampling Frequency (Hz)

HDD DVD
Digital TV
100M Digital IF
VDSL
Flash Digital Camera
10M LAN
ADC Pipeline ADC
ADSL
1M
Motor Servo GSM, PDC

100k
SAR ADC Σ-Δ ADC
10k CD/MD
Celluar Phone
1k
4 6 8 10 12 14 16 18 20 22 24
Resolution (bit) 13
Advantages and disadvantages of
technology scaling
1/Power consumption 1
Integration  2
L
1
Performance (Log)

GBP  1 (for constant IDS)

Speed L
Gain  L1, Supply voltage  L
1

Signal Swing
Dynamic Range   L2
Noise  Mismatch

Scaling (Shrink)
1/(Design Rule) (Log)
14
 Figure of merit (FOM) of analog
circuits
• Before ITRS2004 edition: G  IIP3  f
FOM LNA 
FOM was defined for each ( NF  1)  P
2
category of circuits.  f0  1
FOM VCO   
– LNA: Low noise amplifier  f  L{f }  P
– VCO: Voltage controlled
oscillator FOMPA  Pout  Gp  PAE f 2
– PA: Power amplifier
(2 ENOB0 )  f S
– ADC: Analog-to-Digital FOM ADC 
converter P
– SerDes(SERializer/DESerializer) RB  RMuxDeMux
FOM SerDes 
P
P : Power consumption
IIP3: Third Order Input Intercept Point ENOB0: Effective number of bits
NF : Noise figure fS : Sampling frequency
L: Spurious power RB: Data Rate
RMuxDeMux: Bit count of parallel data 15
PAE: Power efficiency
 Quiz
Which circuit is better for a sensitivity and a signal-to-noise ratio?

12dB 16bit
Sensor Digital output

0dB 18bit
Sensor Digital output

16
 Suggested answer
12dB 16bit

Equivalent gain for LSB

=
0dB 18bit

0dB amplifier = No amplifier (no noise)

Why is the increment of 1bit equivalent with the amplification

of 6dB (2 times)?

17
 Suggested answer
Maximum number of N-bit binary code = 2N -1
Dynamic range of N-bit binary code system = (2N -1)/1
Maximum number of (N+1)-bit binary code = 2N+1 -1
Dynamic range of (N+1)-bit binary code system = (2N+1 -1)/1

Then, the amplitude of signal that is equivalent for the

differential dynamic range between (N+1)-bit and N bit
system is corresponding to (2N+1 -1)/ (2N -1) ≒ 2 ≒ 6.02dB
Note that this calculation is made on a condition of M = 0
(no noise shaping) and OSR = 1 (no oversampling). More
precise analysis is shown in next slide.
18
 Speed = Accuracy = Gain
SNR for quantization noise and ENOB(Effective number of bits)
in oversampling condition
M
SNRmax [dB]  6.02  N  1.76  20  log[ ]  (20  M  10) log OSR
2  M 1
1 M
ENOB[bit ]  1  [(20  M  10) log OSR  20 log( )]
6.02 2  M 1
M : Order of noise-shaping transfer function
OSR: Oversampling ratio
Example
Speed Accuracy Gain
M = 0, OSR = 128, then ENOB = 4.5[bit], ΔSNRmax = 27[dB]
M = 1, OSR = 128, then ENOB = 10.6[bit], ΔSNRmax = 64[dB]
NOTE: The theoretical base will be discussed later. 19