Hsiao-Chin Chen, 2010 CMOS RFIC Design

CMOS RFIC Design

Low Noise Amplifier

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Receiver Architecture

Heterodyne Receiver

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Receiver Architecture (cont.)

Homodyne Receiver

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Receiver Architecture (cont.)

cos(2πfLO2t)

Mixer VGA LPF

ADC
Preselecion LNA
filter
1st LO
0
90 sin(2πfLO2t) DSP

ADC

Mixer
VGA LPF

Low-IF/digital-IF Receiver cos(2πfLO2t)

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Design of LNA
Typical LNA characteristics in heterodyne systems

NF 2 dB
IIP3 -10 dBm
Gain(S21) ~15 dB
Input and Output Impedance (Zin, Zout) 50 ohm
Input and Output Return Loss (S11,S22) -15 dB
Reverse Isolation(S12) 20 dB
Stability Factor(K) >1

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Two-port System

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Scattering Parameters

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Maximum Power Transfer

“Conjugate Impedance”

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Impedance Matching
Expressed by the input return loss defined as
20log(reflection coefficient)

Reflection coefficient: (R0 = 50 ohm)

Z in − R0 ΔR
Γ= Γ=
Z in + R0 2 R0 + ΔR

For a return loss of –15 to –20 dB, ΔR is

about 15 to 9 ohm.
National Taiwan University of Science and Technology
Hsiao-Chin Chen, 2010 CMOS RFIC Design

Smith Chart and S-parameter

m1
freq=4.120GHz
S(1,1)=0.123 / 25.456
impedance = Z0 * (1.243 + j0.134)

m1
S(1,1)

freq (2.000GHz to 6.000GHz)

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

LC Matching Network

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

LC Matching Network (cont.)

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

LC Matching Network
• Π-Network

• T-Network

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Design of LNA (cont.)

Impedance : Choice of input impedance

Noise match: Zs = Zopt

Power match: Zs = Zin*
Voltage gain: Zin = infinity ( low frequency ICs)

1+ |Δ |2 −|S11 |2 −|S22 |2
Stability factors: K=
2|S12 ||S21 |
>1

Δ = S11S22 − S12S21 < 1

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

More on Stability Issue

• A stability factor greater than unity and a delta
smaller than unity are required for unconditional
stability. When the circuit is unconditionally stable,
it does not oscillate with any combination of source
and load impedances.
• Decreasing S12 improves the stability. (The reverse
isolation is better!)
• The K factor as well as the S parameters of the
circuit must be observed over a wide frequency
range. (It is dangerous if you only observe them
over the band of interest!)

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Noisy Two-port Theory

• If Ys=Gs=1/Rs vn I2

iS YS
Noise-free
in V2
Two-Port

F = Fmin +
Rn
GS
[
(GS − Gopt )2 + (BS − Bopt )2 ]
Rn 2
= Fmin + YS − Yopt
GS
2
4rn Γ S − Γ opt
= Fmin +
(1 − Γ ) 1 + Γ
S
2
opt
2

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Noise Parameters
vn I2

iS YS
Noise-free
in V2
Two-Port
Z0 =50 ohm

F = Fmin +
Rn
GS
[ 2 2
]
(GS − Gopt ) + (BS − Bopt ) Γ opt = Z opt − Z 0
Z opt + Z 0
Rn 2 2
= Fmin + YS − Yopt 1 + Γ opt
GS rn = (F50 − Fmin ) 2
2 4 Γ opt
4rn Γ S − Γ opt
= Fmin +
( 2
1 − Γ S 1 + Γ opt) 2

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Optimum Low Noise Match

4rn |Γ S − Γ opt |2
F = Fmin +
(1−|Γ S |2 )|1 + Γ opt |2
2 ω ⎛ω ⎞
Fmin ≈1+ δ γ (1−|c| ) ≈ 1 + 2.3⎜⎜
2
⎟⎟ for MOSFET
5 ωT ⎝ ωT ⎠
Rn
rn =
Z0
γg
Rn = d0
2
g m

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Noise Related Constant ‘ γ ’

Long channel : 2/3

Short Channel:
2/3 X 2~3 Î 4/3 ~ 2

“Complete High-Frequency Thermal Noise

Modeling of Short- channel MOSFETs and Design
of 5.2-GHz Low Noise Amplifier”, Kwyro Lee et al,
IEEE JOURNAL OF SOLID-STATE CIRCUITS,
VOL. 40, NO. 3, MARCH 2005

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

MOSFET Noise Optimization

Note that Cgd should also be considered at high frequency.

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

MOSFET Noise Optimization (cont.)

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

MOSFET Noise Optimization (cont.)

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Blocking and Desensitization

in RF Amplifiers
Internal low-frequency
noise sources will act
VO = a1Vi+a2Vi2+a3Vi3 like unwanted signal
input.
Vi = V1cos ω1t+ V2cos ω2t+ V3cos ω3t
ω1 ~ ω2 and ω1 >> ω3
Interferer V2 is much larger than V1 and V3
VO ~ a1V1cos ω1t + a2V2V3cos(ω2 ± ω3)t + …
„ The desensitization produced by such blocking
mechanism is directly related to the second-order
intermodulation performance of the amplifier.
„ Excessive flicker noise levels in the circuit will tend to
make this phenomenon more pronounced.
National Taiwan University of Science and Technology
Hsiao-Chin Chen, 2010 CMOS RFIC Design

NF Degradation due to Blockers

• The NF degradation due to previously
mentioned blocking desensitization
phenomenon “can not” be predicted by
small signal simulation.
• PSS and PNOISE simulation (Pin=Pinterferer)
• It can be minimized by improving linearity
or say the large signal handling capability
of the amplifier. (ex: source degeneration)
• Reducing the low-frequency gain of the
amplifier is also helpful. (ex: a lower
current mirror ratio)
National Taiwan University of Science and Technology
Hsiao-Chin Chen, 2010 CMOS RFIC Design

CMOS LNA Topology

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Common Source Stage Input Matching:

Brutal Force Solution

Poor noise figure ( > 3dB) (Vn + I n RS ) 2 I n2

NF = 1 + ≈ 1+
4kTRS 4kTGS
4kTG p RS
≈ 1+ ≈ 1+
4kTGS RP
National Taiwan University of Science and Technology
Hsiao-Chin Chen, 2010 CMOS RFIC Design

Common Source Stage Input Matching:

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Resistive Feedback Amplifier

Rf
Vout

Zin RFB
RFB RL Vin Vout
Vin
M1
+
RS Cgs1 V_gs1 gm1Vgs1 RL
RS

vs
vs

RFB +RL 1 Rf
Zin = = 2 2 2
(1− jωRf Cgs1 ) Rf
1+gm1R L sCgs1 1+ω Rf Cgs1
Zin RFB
LG
Vin Vout

+
RS Cgs1 V_gs1 gm1Vgs1 RL

vs

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Wide-Band Input Matching

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

How to determine Rf and LG

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Noise Model for Resistive Shunt-

Shunt Feedback Amplifier
2
i 2n,out i rgo +i lgo +i rsso +i rfbo +i do R g +R lg +R ss i 2rfbo 2
i do
F= ≈ 1+ ≈ 1+ + +
i 2
i 2 RS i 2
iso2
so so so
RFB
R g +R lg +R ss
≡ 1+ +Frfbn +Fdn
RS i 2rfb
LG Rlg elg2 Rg e 2rg
Cgs1 +
RS i 2 vgs1 m ⋅ g m1v gs1 2
m ⋅ i d2 i 2n,out
g _

es2 Rss

e 2rss

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Noise Factor
2
1
mg m1 −
R FB
iso2 =4kTR S Δf ⋅
⎛ L ⎞ R
s 2 Cgs1LG +s ⎜ G +Cgs1R S ⎟ + S +1
⎝ R FB ⎠ R FB
2

4kTΔf s Cgs1LG +s ( mg m1LG +Cgs1R S ) +mg m1R S +1

2
2
i =
rfbo ⋅
R FB ⎛ L ⎞ R
s 2 Cgs1LG +s ⎜ G +Cgs1R S ⎟ + S +1
⎝ R FB ⎠ R FB
γ 2
i 2d0 =4kT g m1Δf ⋅ m
α
2 2
ω ω
s 2 +s( 0,rfbn )+ω20,rfbn s 2 +s( 0,dn )+ω20,dn
R g +R lg +R ss R FB Q rfbn γg Qdn
F ≈ 1+ + ⋅ (Cgs1LG ) 2 ⋅ + m1 ⋅ (Cgs1L G ) 2 ⋅
RS RS mg m1R FB − 1 αR S 1
g m1 −
mR FB

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Noise Factor (cont.)

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Common Source Stage Input Matching:

Inductive Source Degeneration

1 g m Ls
Z in = jωLs + +
jωC gs C gs

g m Ls
Rin =
C gs
1
jω ( Lg + Ls ) + =0
jωC gs

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Inductive Source
Degeneration:

National Taiwan University

(c) of Science and Technology
Hsiao-Chin Chen, 2010 CMOS RFIC Design

Inductive Source Degeneration

• Narrowband matching
• No additional noise generated
• Possible to achieve impedance and noise
matching concurrently
• Large chip area if on-chip inductors used
Æ may use bond-wire

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Device Selection ( narrow band)

D. K. Shaeffer and T. H. Lee, “A 1.5 V, 1.5 GHz CMOS
low noise amplifier,” IEEE J. Solid-State Circuits, vol.
32, no. 5, pp. 745–759, May 1997.

3 1
WOPT = ≈ ≈ 112.4 μm
2ωo LCox RS QL, opt 3ωLCox RS

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Device Selection (broad band)

g m LS 1 g m LS
Z in ≈ s( LG + LS ) + + RS = = 50 Ω LG
C gs sCgs C gs

1
s( LG + LS ) +
Z − RS sCgs LS
S11 = in =
Z in + RS s( L + L ) + 2 ⋅ g m LS + 1
G S
Cgs sCgs
1
s2 +
C gs ( LG + LS ) s 2 + ωo2 s 2 + ωo2
= = 2 =
g m LS 1 s + Bs + ω 2 ω
s + 2⋅
2
⋅s+ o s 2 + o s + ωo2
C gs ( LG + LS ) C gs ( LG + LS ) Q

g m LS 100 1
B ≡ 2⋅ ≈ ωo2 ≡
C gs ( LG + LS ) ( LG + LS ) Cgs ( LG + LS )

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Device Selection (broad band)

− ω 2 + ωo2 20 log S11 ≤ −10 dB
S11 = LG
− ω 2 + jωB + ωo2

− B + B 2 + 36ω O2 B + B 2 + 36ω O2
≤ω ≤ LS
6 6

Δω B 50
Δf = = ≈
2π 6π 3π ⋅ ( LG + LS )

LG + LS ≤ 5.305 nH (4.9 ~ 5.9 GHz, centered at 5.3768 GHz)

g m RL ωo
S 21 =
ωo
⋅ H ( s) Q≡ (LG + LS ) > 0.707 LG + LS ≥ 2.09 nH
s2 + s + ωo2 2 RS
Q

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Common Source Stage Input Matching:

R L2 C L (C L + C F )ω 2 + 1 + g m R L
ℑ{Yin } = C F ω 2
(6.9)
R L2 (C L + C F ) ω 2 + 1
2

C F + g m R L (C L + C F )
ℜ{Yin } = R L C F ω 2
(6.8)
R L2 (C L + C F ) ω 2 + 1
2

With gmRL>>1, CL>>CF and ω ≈ 1/RLCL,

gm C F
Re{Yin } =
2 CL
g m RL
Im{Yin } = C F w(1 + )
2

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Common Gate Stage Input Matching:

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Common Gate Common Source Combination :

Noise Cancellation to Improve NF

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Common Source Stage Input Matching:

Active feedback termination
• Use two stages to increase gain
• Use M3 feedback to provide input resistance
• Have Noise and stability issues

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

CMOS LNA Design Example:

Use a load as amplifying device

g m ,tot = g m1 + g m 2

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Current Reused LNA

Baimei Liu, Chunhua Wang

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Frequency-Scalable SiGe
Bipolar RF Front-end Design
Osama Shana’a et al,
IEEE J. OF SOLID-STATE CIRCUITS,
VOL. 36, NO. 6, JUNE 2001

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Simplified Cascode LNA Circuit

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Bipolar LNA Design

⎛ 1 ⎞ ⎛ VT ⎞
V = 4kT ⎜⎜ rb +
n
2
⎟⎟ = 4kT ⎜⎜ rb + ⎟⎟
⎝ 2gm ⎠ ⎝ 2IC ⎠
• Q1 must be relatively large and biased at a high
current.
• However, increasing size of Q1 leads to a higher
input capacitance.
– noise of Q1 and its following devices can be magnified.
– Voltage gain can be degraded.
• Increasing the base current results in greater base
shot noise.
National Taiwan University of Science and Technology
Hsiao-Chin Chen, 2010 CMOS RFIC Design

Frequency-Scalable SiGe Bipolar

RF Front-end Design
n 2JC ⎛ f2 1 ⎞ n2
NFmin ( J C ) = 1 + + ⎜
(re + rb ) u ⎜ 2 + ⎟⎟ +
β DC VT ⎝ fT β DC ⎠ β DC
Most of the parameters are
bias dependent, i.e., they are
a function of collector current
density. Consequently, it is
useful to plot the minimum
NF versus collector current
very carefully taking the bias
dependencies into account,
as shown in the figure.

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Frequency-Scalable SiGe Bipolar

RF Front-end Design (cont.)
For frequencies well below ft, the optimum current density scales almost
linearly with frequency. In other words, whenever the frequency of interest
is scaled by a factor ε, the optimal current density has to be scaled by the
same factor ε for the scaled device to operate at the optimum NF.

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

Frequency-Scalable SiGe Bipolar

RF Front-end Design (cont.)

„ Find the optimum current density for the best NFmin

„ Vary the device size to achieve 50-ohm Rs,opt
Trade-off:
• Device size too large Æ Current budget
ÆHigh frequency performance degraded
• Device size too small Æ Matching difficulties

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

References
1) Robert G. Meyer and Alvin K. Wong, “Blocking and
Desensitization in RF Amplifiers” IEEE J. OF SOLID-
STATE CIRCUITS, VOL. 30, NO. 8, Aug. 1995.

National Taiwan University of Science and Technology

Hsiao-Chin Chen, 2010 CMOS RFIC Design

National Taiwan University of Science and Technology