RL

2
Field-Effect Transistors

2.1 BASIC PRINCIPLES OF JFET

The eld-effect transistor (FET) is an electric-eld (voltage) operated transistor, developed
as a semiconductor equivalent of the vacuum-tube device, called the pentodes. FET’s are
classied mainly into two types:

• The junction eld-effect transistor (JFET)

• The metal-oxide semiconductor eld-effect transistor (MOSFET or MOST).

2.1.1 Structure of the JFET

Figure 2.1 shows the structure of an N-channel JFET. As shown in the gure, an N-channel
JFET consists of an N region of silicon into which two P++ regions are diffused. The N region
is called a channel because it permits current ow as in a conducting channel. The ends of the
channel are metallized and external leads are taken out to form the source (S) and drain (D)
terminals of the FET. The two P++ regions are usually shorted together to form the gate (G)
terminal. We notice that immediately after the P++ regions are diffused into the N channel,
depletion layers are formed about the P++ regions, as shown in Fig. 2.1.

Gate

PP++ Depletion layer

Source Drain

N channel

Fig. 2.1 Structure of JFET.

 Field-Effect Transistors

we have forwarded bias between the source and the gate (+VGS) and reverse bias between
the gate and the drain (−VDG). Due to the forward bias between the source and the gate, the
depletion layer in this region is thin. However, due to the reverse bias, there exists a larger
depletion layer between the gate and the drain, as shown in Fig. 2.3.
Now, let the supply voltage VDD be increased in steps of, say, 1 volt each. We nd that
as the drain-source voltage gets increased, the drain attracts more and more electrons, and
ID increases correspondingly. The increase in ID results in the increase in the reverse bias
between the gate and the drain. We nd that the depletion layer between gate and drain gets
wider and wider as the reverse bias is increased.

Drain Characteristics
Figure 2.4 shows the drain characteristics, a plot between drain-source voltage VDS and drain
current ID, with the gate-source voltage VGS kept constant. Initially, we x VGS at 0 V, and
vary VDS in steps of 1 volt each, as stated above, and note the corresponding values of ID.
The resulting values are tabulated, and using the tabulated values, the characteristic for
VGS = 0 is plotted, as shown in Fig. 2.4.
Consider the region OA in the characteristic. We nd that ID increases linearly with VDS.
This is due to the fact that as VDS increase more and more electrons get attracted by the drain
resulting in an increase in ID. We also notice that the increase in ID results in an increase in
the depletion width between drain and gate. The increase in ID continues until the point A is
reached, at which point, all the electrons emitted from the source are attracted by the drain
and ID reaches its maximum value. At point A, the maximum value of ID produces maxi-
mum drop in the channel, which in turn produces maximum reverse bias between the drain
and gate terminals. This results in the channel getting almost pinched-off.

C
I D mA
3 B
VGS = 0V
2 A VGS = −2V
VGS = − 4V
1 VGS = −6V
0 VDS
0 10V
Early voltage, −VA

Fig. 2.4 Drain characteristics of JFET.

At pinch-off, the channel cannot completely close; for, if the channel closes, the ow of
ID would stop completely. But, if the ow of ID stops completely, then the entire depletion
layer will disappear. This will open up the channel and ID will ow again. This conrms the
theory that the channel cannot get completely pinched-off.
 Basic Communication and Information Engineering

P ++ Wider depletion layer

S N D
Channel pinch-off

Fig. 2.5 Channel at pinch-off.

ID is a maximum at pinch-off, as shown in Fig. 2.5. This is similar to the situation in a river
where a constriction in the path blocks the ow of water. We notice that to maximize the
current ow through a constriction, the velocity of the ow has to be increased proportion-
ately. This is true in the case of the FET too. Thus, we nd that at pinch off the velocity of
the electrons is increased to maximize the drain-current ow. This drain current is called the
saturation drain current and is designated as IDSS.

In the region AB of the characteristics shown in Fig. 2.4, the current remains more or less
constant. This is because at point A itself, all the electrons emitted from the source would
have reached the drain, and current becomes a maximum. Therefore, even if VDS is increased
ID cannot increase.

Now, we refer to the point B in the curve. At this point, the reverse voltage is so high that
avalanche breakdown will occur. At this point, the current suddenly rises to a very high
value, which unless limited by a suitable resistor, will destroy the device. The breakdown
region is marked as region BC in Fig. 2.4.

Let us now x VGS at –2 V. The experiment is repeated by varying VDS and noting the
corresponding values of ID, as before. By applying an external reverse bias between gate
and source, a depletion region is created between drain and gate. This depletion region is
dependent only on the gate-supply voltage and is totally independent of the drain-current
ow.

Now, if we apply VDD, as before ID would start owing again, and the whole story
described above repeats. We now nd that the VDS-ID curve for VGS = −2 V is similar
to, and almost parallel to that for VGS = 0 V. However, the current in this case is less
than that in the previous case. This is because of the depletion region already formed as
a result of the reverse bias between the gate and the source, which reduces the channel
width.

The experiment is repeated for various values of VGS. The results are tabulated and the char-
acteristics are drawn as shown in Fig. 2.4. We nd that, as VGS is increased in the negative
direction, i.e., −2 V, −4 V, etc., the drain current gets reduced proportionately. Ultimately, at
a large negative value of VGS, the channel will be completely cut-off or closed so that no
drain current can ow. This is called the cut-off condition. Complete channel cut-off is pos-
sible because, in this case, it is the external gate-source voltage that brings in the channel
cut-off, and not by the drain current as in the case where VGS is zero.
 Field-Effect Transistors

Mutual or Transfer Characteristic

The transfer curve is plotted by keeping VDS constant at a particular value, say 5 V, and by
varying VGS and noting the corresponding value of ID. As shown in Fig. 2.6, we nd that the
curve is almost linear. We also nd that at VGS = −VP, the channel is completely cut-off or
pinched-off. For a typical JFET, like BFW 10, VP = −8 V.

4 mA

ID

0 mA
VP = −8 −VGS 0V

Fig. 2.6 Transfer or mutual characteristic of JFET.

The slope of the transfer curve is called the mutual conductance and is dened as
⎡ ΔI ⎤
gm = ⎢ D ⎥ (2.1)
⎣ ΔVGS ⎦VDS =constant

Amplification Characteristic
We can also plot the amplication characteristic of the JFET, which is the plot between VDS and
−VGS, with ID kept constant. This is shown in Fig. 2.7. The slope of the characteristic is known
as the amplication factor μ of JFET. Mathematically, amplication factor is dened as:
⎡ ΔV ⎤
μ = − ⎢ DS ⎥ (2.2)
⎣ ΔVGS ⎦ I D =constant
The negative sign in the equation indicates that the variation in VDS is opposite to the vari-
ation in VGS. Amplication factor represents the maximum amount of amplication that the
device is capable of producing.

I D = constant VDS V

−VGS V

Fig. 2.7 Amplication characteristic.

 Basic Communication and Information Engineering

2.1.3 Relation among μ, gm, and rd

From the denitions, we nd that there exists a denite relation among the JFET parameters
μ, gm, and rd. From experiments, we nd that

iD = f (vDS, vGS) (2.3)

where we have used instantaneous total values of drain current, drain-source voltage, and
gate-source voltage. By instantaneous total value, we mean the variable DC value. As an
example, we express

vDS = VD + vds (2.4)

where vDS is the variable DC, VDS is pure DC, and vds is pure AC. Using Taylor’s expan-
sion, Eq. (2.3) may be written as
⎛ ∂i ⎞ ⎛ ∂i ⎞
ΔiD = ⎜ D ⎟ ΔvDS + ⎜ D ⎟ ΔvGS (2.5)
⎝ ∂vDS ⎠ ⎝ ∂vGS ⎠

where ∆vDS is a small change in vDS, ∆vGS is a small change in vGS, and ∆iD is the cor-
responding change in iD. Equation (2.3) suggests that the total variation in the value of the
drain current iD is equal to the sum of the variations in iD due to the variations in vDS and
vGS. We now dene the following terms:
∂iD
ΔvGS = 0 = rd (drain resistance) (2.6)
∂vDS

∂iD
ΔvDS = 0 = gm ( transfer conductance) (2.7)
∂vGS

Using the above in Eq. (2.5), we get

1
ΔiD = ΔvDS + g m ΔvGS (2.8)
rd

Now, by differentiating Eq. (2.4), we get

∆vDS = ∆VD + ∆vds (2.9)

In Eq. (2.9), ∆VD = 0 since VD = constant. Hence

∆vDS = ∆vds (2.10)

This means that the change in the variable DC value vDS is equal to the variation in the AC
value vds. Since vds is a variable value, we conclude that

∆vDS = vds (2.11)

 Basic Communication and Information Engineering

2.2 BASIC PRINCIPLES OF MESFET

The MESFET (metal-semiconductor eld-effect transistor) is an FET structure constructed

by depositing aluminium over an FET structure to form a metal-semiconductor Schottky-
barrier junction. The device is usually made of GaAs because of its high electron mobility,
and is used as a microwave transistor.
Figure 2.9(a) shows the structure of a GaAs MESFET. It consists of a substrate made of
semi-insulating (undoped) GaAs over which a N +-type (medium-doped) epitaxial layer of
GaAs is formed. Over this layer, in the centre of the device aluminium is deposited to form
the metal-semiconductor Schottky gate. The drain and source contacts are similarly formed
using gold-germanium or gold-tellurium alloy contacts.

S G D
I D mA
Al VGS = 0 V
VGS = − 0.5 V
N epitaxial layer
Depletion layer VGS = −1 V

GaAs Substrate VGS = −2 V

VDS V

Fig. 2.9(a) Structure of MESFET. Fig. 2.9(b) Drain characteristics.

2.2.1 Working Principles of MESFET

MESFET is a modication of the conventional JFET (junction eld-effect transistor) dis-
cussed above with a metal-semiconductor junction replacing the semiconductor-semiconduc-
tor junction of the JFET. As in the case of the JFET, here also we apply a reverse bias
between the gate and the source (i.e., the gate is made negative with respect to the source),
and a forward bias between the drain and source (source made negative with respect to
drain).
When the drain is positive with respect to the source, drain current starts owing from drain
to source, and this develops a depletion region between the source and the drain, as shown in
Fig. 2.9(a). This is similar to the depletion region formed under the drain and the source in
the conventional JFET. The larger the drain voltage, the larger the drain current, and hence
the larger the depletion region under the drain, as shown. This will tend to pinch-off the
channel when the drain current reaches a maximum, as in the case of the regular JFET.
The drain-current ow is also dependent on the gate-source reverse bias which forms its
own depletion region between the gate and the source. The larger the reverse bias, the larger
its effect in bringing a pinch-off in the channel, which later becomes cut-off to stop the
drain-current ow.
 Field-Effect Transistors

Figure 2.9(b) shows the drain characteristics of the MESFET. It can be seen that this is simi-
lar to the drain characteristics of the JFET. The device gives maximum current with VGS = 0
and gives zero current when the gate is biased to a large negative value, as shown.
The device with its micro-miniature structure and short channel length is highly suitable for
operation in the microwave region.

2.3 METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT

TRANSISTOR

Figure 2.10 shows the structure of a metal-oxide semiconductor eld-effect transistor (MOS-
FET). The device derives its name from the silicon dioxide (SiO2) layer used for passivating
the surface of the device. Metal-oxide semiconductor eld-effect transistors (or MOSFET’s)
are of two main types. They are the enhancement type and the depletion type. Figure 2.9
shows the structure of the enhancement type.

D G S
Al metallization
SiO 2 layer
N ++ N ++

P substrate

Fig. 2.10(a) Structure of enhancement MOSFET.

2.3.1 Enhancement-type MOS Transistor (EMOSFET)

Figure 2.10(a) shows that EMOSFET consists of a P type substrate over which a thin sur-
face-passivating layer of SiO2 is grown. In this SiO2 layer, two windows are cut and N ++
diffusions are made, as shown. Aluminium metallizations are done in these windows to take
out the source and the drain terminals. Finally, aluminium metallization is also done over the
SiO2 layer in between the source and drain terminals, from which the gate terminal is taken
out.

Working Principles of EMOSFET

For normal amplier operation, the gate of an MOSFET is made positive with respect to its
source, as shown in Fig. 2.10(b). It can be seen that immediately on the application of the
bias a channel of electrons is induced in between the source and drain N ++ diffusions. The
positive voltage on the gate drives the holes away from the region in the substrate under the
gate metallization, leaving the electrons in that region uncovered to form the channel.
A second theory assumes that the device behaves as a capacitor with the gate metalliza-
tion acting as the positive electrode, the source N ++ diffusion the negative electrode, and
 Basic Communication and Information Engineering

the SiO2 layer the dielectric. The capacitance of the device depends on the thickness of the
dielectric.
When the upper plate (gate metallization) is made positive with respect to the lower plate
(source diffusion), a positive-charge accumulation is formed on the upper plate and a nega-
tive-charge accumulation on the lower plate. Since the positive-charge accumulation extends
throughout the length of the gate metallization, the negative-charge accumulation must also
extend to the same distance in the substrate layer below the gate metallization. This results
in the creation (enhancement) of the electron channel in the substrate. We say that a chan-
nel has been induced or enhanced in the substrate, and hence the name enhancement-type
MOS transistor, or EMOSFET. This enhanced channel is also called an inversion layer.
Once the inversion channel is formed, we apply a voltage between the drain and the source,
as shown in Fig. 2.10(c). This drives an anode current between drain and source. Figure 2.11
shows the drain characteristics, which is the plot between VDS and ID, with VGS as the xed
parameter.

S − +
VGG G D

SiO 2 layer
N ++ − − − − − − N ++

Induced-electron (inversion) channel

P substrate

Fig. 2.10(b) Gate biased positively with respect to source.

− + ID
VDD
− +
S VGG G D

N ++ − − − − − − N ++
Electron motion
P substrate

Fig. 2.10(c) Drain-current ow.

Referring to Fig. 2.11, we nd that as VDD, and hence VDS, is increased, ID gets increased
linearly during the initial regions of the curves, just as in the JFET. This is because the higher
the VDS, the more the number of electrons attracted by the drain from the source. However,
 Basic Communication and Information Engineering

P and the N MOSFET’s is called the CMOSFET. The theory of the CMOSFET will be dis-
cussed later.
Figure 2.13(a) shows three symbols used to represent NMOSFET’s, and Fig. 2.13(b) shows
three symbols used to represent PMOSFETs. Of these, those shown in Fig. 2.13(a)(ii) and
2.13(b)(ii) are the currently used symbols.

D D

G G

S S
i ii iii i ii iii

Fig. 2.13(a) Different NMOS symbols. Fig. 2.13(b) Different PMOS symbols.

2.3.2 Depletion-Type MOS Transistor (DMOST)

The depletion-type of MOS transistor is a MOSFET that combines the structure of the
EMOSFET and the JFET. The structure of the DMOSFET is shown in Fig. 2.14. The struc-
ture shown is a modied form of the EMOSFET, with an N channel diffused in between the
source-and-drain N ++ diffusions. So, we nd that the device is a combination of the JFET
with its already diffused N channel, and an EMOSFET with the aluminium gate deposition
over the SiO2 layer. The rest of the structure is similar to the EMOSFET.

− + ID
VDD
− +
S VGG G D

N ++ N ++

N channel
P substrate

Fig. 2.14 Drain-current ow in DMOS FET.

Working principles of the DMOST

The principle of working of the DMOSFET can be explained with the help of Fig. 2.14.
Since the device is a combination of EMOSFET and JFET, this device has two distinct
modes of operation. These are, respectively, the EMOSFET mode and the JFET modes as
already stated.
 Basic Communication and Information Engineering

Figure 2.16 shows the transfer characteristics of DMOSFET. The transfer characteristics
show the JFET and the EMOSFET regions. The curve has a negative-gate bias region rep-
resenting the JFET mode of operation. The positive gate-bias region of the characteristics
represents the EMOSFET region. It may, however, be noted that there is no threshold volt-
age for the DMOST.
Figure 2.17(a) shows the symbol of the N-type DMOSFET and Fig. 2.17(b) shows the sym-
bol of the P-type DMOSFET. It can be seen that the diffused channel is shown clearly in the
symbols.

D
D

G G

S S

Fig. 2.17(a) Symbol of N-type DMOSFET. Fig. 2.17(b) Symbol of P-type DMOSFET.

2.3.3 Complementary MOS Transistor (CMOSFET)

The complementary-type of MOS transistor, generally known as the CMOS transistor, is a
combination of the complementary pair of an NMOS transistor and a PMOS transistor. Ini-
tially, this structure was conceived and developed for high-density, low-power logic gates.
However, the structure has become so popular that it is used in almost all modern logic cir-
cuits, which includes the latest computer chips. Recently, these circuits have also found use
in amplier circuits. Thus we nd that CMOS transistors have become a very widely used
structure.
Figure 2.18(a) shows the circuit of a CMOS inverter, and Fig. 2.18(b) shows its practi-
cal construction, known as the twin-tub well construction. This structure, as stated before,
consists of an NMOS inverter on top of a PMOS inverter. In a P substrate, we rst diffuse
three N ++ regions, as shown. In this structure, two of the N ++ regions are small, and the
third large. The rst two smaller N ++ regions form the NMOST, and the third N ++ region
forms an N well, into which two P++ regions are diffused to form the PMOST. The top sur-
face is then passivated using SiO2 layer, and aluminium metallization is done as shown in
Fig. 2.18(b).
It can be seen that the device has the least amount of power dissipation in switching applica-
tions. This is because, when the PMOS is ON the NMOS is OFF, and vice versa. Therefore,
we nd that, except at switching instants, there is no continuous current path from the posi-
tive terminal of the battery to its negative through the circuit.
In Fig. 2.18(a), we have shown the CMOS inverter with its supply voltage applied. For
a typical CMOS circuit, usually VDD is selected between 5 V to 15 V. Let the input
 Basic Communication and Information Engineering

Problems 2.2 In a channel at pinch-off,

the drain current is ___.
P2.1 Compute the values of small-signal (maximum/minimum)
parameters of a junction eld-effect 2.3 The drain current at pinch-
transistor using the data given in off is called ___ drain current.
the following table. (saturation)
VGS VDS ID
2.4 The drain current-becoming-zero
0 0 condition is called the ___. (cut-off)
2 0.5
–2 4 1 2.5 The slope of the transfer char-
6 2 acteristic is called ___.
8 3
(transconductance)
10 4
0 0 2.6 The slope of the drain characteristic
2 0 is called ___. (drain resistance)
–3 4 0.5
6 1 2.7 The product gm × rd is called ___.
8 2 (μ, or amplication factor)
10 3
2.8 ___ and ___ are the two types
P2.2 Compute the value of amplication of MOSFETS. (enhancement,
factor of a junction eld-effect depletion)
transistor if at ID = 2 mA, when
2.9 The electron layer induced in
VDS = 15 V, VDS = –1 V and when
a channel is called a ___ layer.
VDS = 5 V, VGS = 0 V.
(inversion)
P2.3 Compute the value of trans-
2.10 In an enhancement-type MOSET,
conductance of a junction eld-
drain current starts owing only
effect transistor, if at VDS = 10 V,
after the gate voltage has reached
when VGS = –2 V, ID = 4 mA and
a voltage called ___ voltage.
when VGS = –3 V, ID = 2 mA.
(threshold)
P2.4 Compute the value of drain
resistance of a junction eld-effect 2.11 In a depletion MOSFET, there
transistor, if at VGS = –3 V, when already exists a diffused ___.
VDS = 15 V, ID = 4 mA and when (channel)
VDS = 10 V, ID = 2 mA. 2.12 The gate must be (positive/nega-
tive) with respect to the source in a
MOSFET for its normal operation.
One-Word Questions
(positive)
2.1 The word eld-effect transistor is 2.13 The gate must be (positive/negative)
derived from the action of ___ eld with respect to the source in a JFET
on the drain-current ow. (electric). for its normal operation. (negative)
 Basic Communication and Information Engineering

2.47 Explain how an inversion layer is 2.56 Explain with relevant circuit dia-
formed in an EMOSFET. grams the working principles of an
EMOSFET.
2.48 How does channel pinch-off occur?
2.57 Explain with relevant circuit dia-
2.49 How does channel cut-off occur?
grams the working principles of a
2.50 What is the difference between DMOSFET.
channel cut-off and pinch-off ?
2.58 Explain how amplication takes
2.51 What is threshold voltage in the place in JFE ampliers.
case of MOSFETS?
2.59 Explain how amplication takes
2.52 Discuss the structure operation of a place in MOSFET ampliers.
MESFET.
2.60 In CMOS circuits, the PMOS acts
2.53 Discuss the basic principles of oper- as the load of the NMOS and vice
ation of a MESFET. versa: Prove.
2.54 Explain the drain characteristics of 2.61 Explain the twin-tub well process of
a MESFET. CMOS IC manufacturing technique.
2.62 Discuss the construction, working
Review Questions principles, and drain characteristics
of a MESFET.
2.55 Explain with relevant circuit dia-
grams the working principles of a
JFET.