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Microprocessor Architecture
The microprocessor is the CPU (Central Processing Unit) of a computer. It is the heart of the computer.
Here, we will describe Intel 8085 as it is one of the most popular 8-bit microprocessor.

Intel 8085
Intel 8085 is an 8-bit, NMOS microprocessor designed by Intel in 1977.

It has following configuration:

o It is a 40 pin I.C. package fabricated on a single LSI chip.

o The Intel 8085 uses a single +5Vd.c. supply for its operation.
o Intel 8085?s clock speed is about 3 MHz; the clock cycle is of 320ns.
o 8 ?bit data bus.
o Address bus is of 16-bit, which can address up to 64KB
o 16-bit stack pointer
o 16 bit PC (Program Counter)
o Six 8-bit registers are arranged in pairs :BC, DE, HL

Intel 8085 is used in mobile phones, microwave ovens, washing machines etc.

The below diagram shows the block diagram of Intel 8085:

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ALU
The Arithmetic and Logic Unit, ALU performs the arithmetic and logical operations:

o Addition
o Subtraction
o Logical AND
o Logical OR
o Logical EXCLUSIVE OR
o Complement (Logical NOT)
o Increment (add 1)
o Decrement (subtract 1)
o Left shift, Rotate left, Rotate right
o Clear, etc.
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Timing and Control Unit
The timing and control unit is the section of the CPU.

o It is used to generate timing and control signals which are necessary for the execution of
instructions.
o It is used to control data flow between CPU and peripherals (including memory).
o It is used to provide status, control and timing signals which are required for the operation of
memory and I/O devices.
o It is used to control the entire operations of the microprocessor and peripherals connected to it.

Thus we can see that the control unit of the CPU acts as the brain of the computer system.

Registers
Registers are used for temporary storage and manipulation of data and instructions by the
microprocessor. Data remain in the registers till they are sent to the I/O devices or memory. Intel 8085
microprocessor has the following registers:

o One 8-bit accumulator (ACC) i.e. register A

o Six general purpose registers of 8-bit, these are B,C, D, E, H and L
o One 16-bit stack pointer, SP
o One 16-bit Program Counter, PC
o Instruction register
o Temporary register

In addition to the above mentioned registers the 8085 microprocessor contains a set of five flip-flops
which serve as flags (or status flags).

A flag is a flip-flop which indicates some conditions which arises after the execution of an arithmetic or
logical instruction.

a. Accumulator (ACC): The accumulator is an 8-bit register associated with the ALU. The register 'A'
is an accumulator in the 8085. It is used to hold one of the operands of an arithmetic and logical
operation.
The final result of an arithmetic or logical operation is also placed in the accumulator.
b. General-Purpose Registers: The 8085 microprocessor contains six 8-bit general purpose
registers. They are: B, D, C, E, H and L register.
To hold data of 16-bit a combination of two 8-bit registers can be employed.
The combination of two 8-bit registers is called register pair. The valid register pairs in the 8085
are: D-E, B-C and H-L. The H-L pair is used to act as a memory pointer.
c. Program Counter (PC): It is a 16-bit special purpose register. It is used to hold the address of
memory of the next instruction to be executed. It keeps the track of the instruction in a program
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while they are being executed.
The microprocessor increments the content of the next program counter during the execution of an
instruction so that at the end of the execution of an instruction it points to the next instruction?s
address in the program.
d. Stack Pointer (SP): It is a 16-bit special function register used as memory pointer. A stack is
nothing but a portion of RAM. In the stack, the contents of only those registers are saved, which
are needed in the later part of the program.
The stack pointer (SP) controls the addressing of the stack. The Stack Pointer contains the address
of the top element of data stored in the stack.
e. Instruction Register: The instruction register holds the opcode (operation code or instruction
code) of the instruction which is being decoded and executed.
f. Temporary Register: It is an 8-bit register associated with the ALU. It holds data during an
arithmetic/logical operation. It is used by the microprocessor. It is not accessible to programmer.
g. Flags: The Intel 8085 microprocessor contains five flip-flops to serve as a status flags. The flip-
flops are reset or set according to the conditions which arise during an arithmetic or logical
operation.

The five status flags of Intel 8085 are:

o Carry Flag (CS)

o Parity Flag (P)
o Auxiliary Carry Flag (AC)
o Zero Flag(Z)
o Sign Flag(S)

If a flip-flop for a particular flag is set, then it indicates 1. When it is reset, it indicates 0.

Data and Address Bus

o The Intel 8085 is an 8-bit microprocessor. Its data bus is 8-bit wide and therefore, 8 bits of data
can be transmitted in parallel from or to the microprocessor.
o The Intel 8085 requires an address bus of 16-bit wide as the memory addresses are of 16-bits.
o The 8 most significant bits of the address are transmitted by the address bus, A-bus (pins A8 ?
A15).
o The 8 least significant bits of the address are transmitted by data/address bus, AD-bus (pins AD0 ?
AD7).

Pin Configuration
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Fig: Pin diagram of Intel 8085 microprocessor

The descriptions of various pins are as follows:

Address Bus and Data Bus

o A8 ? A15 (Output): These are address bus and are used for the most significant bits of the
memory address or 8-bits of I/O address.
o AD0 ? AD7 (Input/output): These are time multiplexed address/data bus i.e. they serve dual
purpose. They are used for the least significant 8 bits of the memory address or I/O address during
the first cycle. Again they are used for data during 2nd and 3rd clock cycles.

Control and Status Signals

o ALE (Output): ALE stands for Address Latch Enable signal. ALE goes high during first clock
cycle of a machine cycle and enables the lower 8-bits of the address to be latched either into the
memory or external latch.
o IO/M (Output): It is a status signal which distinguishes whether the address is for memory or
I/O device.
o S0, S1 (Output): These are status signals sent by the microprocessors to distinguish the various
types of operation given in table below:
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Status codes for Intel 8085

S1 S0 Operations

0 0 HALT

0 1 WRITE

1 0 READ

1 1 FETCH

o RD (Output): RD is a signal to control READ operation. When it goes low, the selected I/O
device or memory is read.
o WR (Output): WR is a signal to control WRITE operation. When it goes low, the data bus' data
is written into the selected memory or I/O location.
o READY (Input): It is used by the microprocessor to sense whether a peripheral is ready to
transfer a data or not. If READY is high, the peripheral is ready. If it is low the micro processor
waits till it goes high.

Interrupts and Externally Initiated Signals

o HOLD (INPUT): HOLD indicates that another device is requesting for the use of the address and
data bus.
o HLDA (OUTPUT): HLDA is a signal for HOLD acknowledgement which indicates that the HOLD
request has been received. After the removal of this request the HLDA goes low.
o INTR (Input): INTR is an Interrupt Request Signal. Among interrupts it has the lowest priority.
The INTR is enabled or disabled by software.
o INTA (Output): INTA is an interrupt acknowledgement sent by the microprocessor after INTR
is received.
o RST 5.5, 6.5, 7.5 and TRAP (Inputs): These all are interrupts. When any interrupt is
recognized the next instruction is executed from a fixed location in the memory as given below:

Line Location from which next instruction is picked up

TRAP 0024

RST 5.5 002C

RST 6.5 0034

RST 7.5 003C

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RST 7.5, RST 6.5 and RST 5.5 are the restart interrupts which cause an internal restart to be
automatically inserted.

The TRAP has the highest priority among interrupts. The order of priority of interrupts is as follows:

o TRAP (Highest priority)

o RST 7.5
o RST 6.5
o RST 5.5
o INTR (Lowest priority).

Reset Signals

o RESET IN (Input): It resets the program counter (PC) to 0. It also resets interrupt enable and
HLDA flip-flops. The CPU is held in reset condition till RESET is not applied.
o RESET OUT (Output): RESET OUT indicates that the CPU is being reset.

Clock Signals

o X1, X2 (Input): X1 and X2 are terminals to be connected to an external crystal oscillator which
drives an internal circuitry of the microprocessor. It is used to produce a suitable clock for the
operation of microprocessor.
o CLK (Output): CLK is a clock output for user, which can be used for other digital ICs. Its
frequency is same at which processor operates.

Serial I/O Signals

o SID (Input): SID is data line for serial input. The data on this line is loaded into the seventh bit
of the accumulator when RIM instruction is executed.
o SOD (Output): SOD is a data line for serial output. The seventh bit of the accumulator is output
on SOD line when SIM instruction is executed.

Power Supply

Vcc : +5 Vlots supply

Vss : ground reference

8085 Instructions
An instruction of computer is a command given to the computer to perform a specified operation on
given data. Some instructions of Intel 8085 microprocessor are: MOV, MVI, LDA, STA, ADD, SUB, RAL,
INR, MVI, etc.
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Opcode and Operands
Each instruction contains two parts: Opcode (Operation code) and Operand.

The 1st part of an instruction which specifies the task to be performed by the computer is called Opcode.

The 2nd part of the instruction is the data to be operated on, and it is called Operand. The Operand (or
data) given in the instruction may be in various forms such as 8-bit or 16-bit data, 8-bit or 16-bit address,
internal registers or a register or memory location.

Instruction Word Size

A digital computer understands instruction written in binary codes (machine codes). The binary codes of
all instructions are not of the same length.

According to the word size, the Intel 8085 instructions are classified into the following three
types:

1. One byte instruction

2. Two byte instruction
3. Three byte instruction

1. One-byte instruction: Examples of one byte instructions are:

o MOV A, B - Move the content of the register B to register A.

o ADD B ? Add the content of register B to the content of the accumulator.

All the above two examples are only one byte long. All one-byte instructions contain information regarding
operands in the opcode itself.

2. Two-byte instruction: In a two byte instruction the first byte of the instruction is its opcode and the
second byte is either data or address.

Example:

MVI B, 05; 05 moved to register B.

06, 05; MVI B, 05 is in the code form.

The first byte 06 is the opcode for MVI B and second byte 05 is the data which is to be moved to register
B.

3. Three-byte instruction: The first byte of the instruction is its opcode and the second and third bytes
are either 16-bit data or 16-bit address.

Example:

LXI H, 2400H; Load H-L Pair with 2400H

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21, 00, 24; LXI H, 2400H in the code form

The first byte 21 is the opcode for the instruction LXI H. The second 00 is 8 LSBs of the data (2400H),
which is loaded into register L. The third byte 24 is 8 MSBs of the data (2400H), which is loaded into
register H.

Instruction Cycle

The time required to fetch an instruction and necessary data from memory and to execute it, is called
an instruction cycle. Or the total time required to execute an instruction is given by:

IC = FC + EC

Where,

IC = Instruction Cycle
FC = Fetch Cycle
EC = Execute Cycle

Timing Diagram for Instruction Cycle

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o Fetch the instruction (Fetch Cycle)

In the beginning of the fetch cycle, the content of the program counter (PC), which is the address of the
memory location where opcode is available, is sent to the memory. The memory puts the opcode on the
data bus so as to transfer it to the CPU.

The whole operation of fetching an opcode takes three clock cycles. A slow memory may take more time.

o Decode the instruction (Decode Cycle)

The opcode fetched from the memory goes to the data register, DR and then to instruction register, IR.
From the IR it goes to the decoder circuitry which decodes the instruction. Decoder circuitry is within the
microprocessor.

o Execute the Instruction (Execute Cycle)

After the instruction is decoded, execution begins.

If the operand is reside the general purpose registers, execution is immediately performed. The time
taken in decoding and execution of an instruction is one clock cycle.

In some situations, an execute cycle may involve one or more read or write cycles or both.

Read Cycle: If an instruction contains data or operand address which are in the memory, the CPU has to
perform some read operations to get the desired data. In case of a read cycle the instruction received
from the memory are data or operand address instead of an opcode.

Write Cycle: In write cycle data are sent from the CPU to the memory or an output device.

o Machine Cycle and State

The necessary steps carried out to perform the operation of accessing either memory or input output
device, constitute a machine cycle. In other words, necessary steps carried out to perform a fetch, a
read or a write operation constitutes a machine cycle.

One sub-division of an operation performed in one clock cycle is called a state or T-state. In short, one
clock cycle of the system clock is referred to as a state.

Timing Diagram
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The necessary steps carried out in a machine cycle can be represented graphically. Such a graphical
representation is called timing diagram. The timing diagram for opcode fetch, memory read, memory
write, I/O read and I/O write will be discussed below:

o Timing Diagram for Opcode Fetch Cycle:

o Timing Diagram for Memory Read

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o Timing Diagram for Memory Write

o Timing Diagram for I/O Read

o Timing Diagram for I/O Write

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In the above diagrams, the basic used parameters are:

ALE: ALE indicates the availability of a valid address on the multiplexed address/data lines. When it is
high or 1, then it acts as an address bus and when low or 0, then it acts as a data bus.

RD (low active): If it is high or 1, then no data is read by the microprocessor. If signal is low or 0, then
data is read by the microprocessor.

WR (low active): If it is high or 1, then no data is written by the microprocessor. If signal is low or 0,
then data is written by the microprocessor.

IO/M (low active): A high or 1 on this signal indicates I/O operation while a low or 0 indicates memory
operation.

S0, S1: S0 and S1 Indicate the type of machine cycle in progress.

The below table, shows the status of different control signal for different operation:
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Addressing modes in 8085 microprocessor

Prerequiste – Addressing modes
The way of specifying data to be operated by an instruction is called addressing mode.
Types of addressing modes –
In 8085 microprocessor there are 5 types of addressing modes:
1. Immediate Addressing Mode –
In immediate addressing mode the source operand is always data. If the data is 8-bit, then the instruction
will be of 2 bytes, if the data is of 16-bit then the instruction will be of 3 bytes.
Examples:
MVI B 45 (move the data 45H immediately to register B)
LXI H 3050 (load the H-L pair with the operand 3050H immediately)
JMP address (jump to the operand address immediately)
2. Register Addressing Mode –
In register addressing mode, the data to be operated is available inside the register(s) and register(s)
is(are) operands. Therefore the operation is performed within various registers of the microprocessor.
Examples:
MOV A, B (move the contents of register B to register A)
ADD B (add contents of registers A and B and store the result in register A)
INR A (increment the contents of register A by one)
3. Direct Addressing Mode –
In direct addressing mode, the data to be operated is available inside a memory location and that
memory location is directly specified as an operand. The operand is directly available in the instruction
itself.
Examples:
LDA 2050 (load the contents of memory location into accumulator A)
LHLD address (load contents of 16-bit memory location into H-L register pair)
IN 35 (read the data from port whose address is 01)
4. Register Indirect Addressing Mode –
IN register indirect addressing mode, the data to be operated is available inside a memory location and
that memory location is indirectly specified b a register pair.
Examples:
MOV A, M (move the contents of the memory location pointed by the H-L pair to the
accumulator)
LDAX B (move contains of B-C register to the accumulator)
LXIH 9570 (load immediate the H-L pair with the address of the location 9570)
5. Implied/Implicit Addressing Mode –
In implied/implicit addressing mode the operand is hidden and the data to be operated is available in the
instruction itself.
Examples:
CMA (finds and stores the 1’s complement of the contains of accumultor A in A)
RRC (rotate accumulator A right by one bit)
RLC (rotate accumulator A left by one bit)

Adressing Modes and Instruction Cycle

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The operation field of an instruction specifies the operation to be performed. This operation will be
executed on some data which is stored in computer registers or the main memory. The way any
operand is selected during the program execution is dependent on the addressing mode of the
instruction. The purpose of using addressing modes is as follows:

1. To give the programming versatility to the user.

2. To reduce the number of bits in addressing field of instruction.

Types of Addressing Modes

Below we have discussed different types of addressing modes one by one:

Immediate Mode
In this mode, the operand is specified in the instruction itself. An immediate mode instruction has an
operand field rather than the address field.
For example: ADD 7, which says Add 7 to contents of accumulator. 7 is the operand here.

Register Mode
In this mode the operand is stored in the register and this register is present in CPU. The instruction
has the address of the Register where the operand is stored.
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Advantages

 Shorter instructions and faster instruction fetch.

 Faster memory access to the operand(s)

Disadvantages

 Very limited address space

 Using multiple registers helps performance but it complicates the instructions.

Register Indirect Mode

In this mode, the instruction specifies the register whose contents give us the address of operand which
is in memory. Thus, the register contains the address of operand rather than the operand itself.

Auto Increment/Decrement Mode

In this the register is incremented or decremented after or before its value is used.

Direct Addressing Mode

In this mode, effective address of operand is present in instruction itself.

 Single memory reference to access data.

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 No additional calculations to find the effective address of the operand.

For Example: ADD R1, 4000 - In this the 4000 is effective address of operand.
NOTE: Effective Address is the location where operand is present.

Indirect Addressing Mode

In this, the address field of instruction gives the address where the effective address is stored in
memory. This slows down the execution, as this includes multiple memory lookups to find the
operand.
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Displacement Addressing Mode
In this the contents of the indexed register is added to the Address part of the instruction, to obtain
the effective address of operand.
EA = A + (R), In this the address field holds two values, A(which is the base value) and R(that holds
the displacement), or vice versa.

Relative Addressing Mode

It is a version of Displacement addressing mode.
In this the contents of PC(Program Counter) is added to address part of instruction to obtain the
effective address.
EA = A + (PC), where EA is effective address and PC is program counter.
The operand is A cells away from the current cell(the one pointed to by PC)

Base Register Addressing Mode

It is again a version of Displacement addressing mode. This can be defined as EA = A + (R), where
A is displacement and R holds pointer to base address.

Stack Addressing Mode

In this mode, operand is at the top of the stack. For example: ADD, this instruction will POP top two
items from the stack, add them, and will then PUSH the result to the top of the stack.
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Instruction Cycle
An instruction cycle, also known as fetch-decode-execute cycle is the basic operational process of
a computer. This process is repeated continuously by CPU from boot up to shut down of computer.
Following are the steps that occur during an instruction cycle:

1. Fetch the Instruction

The instruction is fetched from memory address that is stored in PC(Program Counter) and stored in
the instruction register IR. At the end of the fetch operation, PC is incremented by 1 and it then points
to the next instruction to be executed.

2. Decode the Instruction

The instruction in the IR is executed by the decoder.

3. Read the Effective Address

If the instruction has an indirect address, the effective address is read from the memory. Otherwise
operands are directly read in case of immediate operand instruction.

4. Execute the Instruction

The Control Unit passes the information in the form of control signals to the functional unit of CPU.
The result generated is stored in main memory or sent to an output device.

The cycle is then repeated by fetching the next instruction. Thus in this way the instruction cycle is
repeated continuously.
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Addressing Modes-

The different ways of specifying the location of an operand in an instruction are called
as addressing modes.

Types of Addressing Modes-

In computer architecture, there are following types of addressing modes-

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1. Implied / Implicit Addressing Mode

2. Stack Addressing Mode
3. Immediate Addressing Mode
4. Direct Addressing Mode
5. Indirect Addressing Mode
6. Register Direct Addressing Mode
7. Register Indirect Addressing Mode
8. Relative Addressing Mode
9. Indexed Addressing Mode
10. Base Register Addressing Mode
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11. Auto-Increment Addressing Mode
12. Auto-Decrement Addressing Mode

In this article, we will discuss about these addressing modes in detail.

1. Implied Addressing Mode-

In this addressing mode,

 The definition of the instruction itself specify the operands implicitly.
 It is also called as implicit addressing mode.

Examples-

 The instruction “Complement Accumulator” is an implied mode instruction.

 In a stack organized computer, Zero Address Instructions are implied mode instructions.
(since operands are always implied to be present on the top of the stack)

2. Stack Addressing Mode-

In this addressing mode,

 The operand is contained at the top of the stack.

Example-

ADD
 This instruction simply pops out two symbols contained at the top of the stack.
 The addition of those two operands is performed.
 The result so obtained after addition is pushed again at the top of the stack.

3. Immediate Addressing Mode-

In this addressing mode,

 The operand is specified in the instruction explicitly.
 Instead of address field, an operand field is present that contains the operand.
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Examples-

 ADD 10 will increment the value stored in the accumulator by 10.

 MOV R #20 initializes register R to a constant value 20.

4. Direct Addressing Mode-

In this addressing mode,

 The address field of the instruction contains the effective address of the operand.
 Only one reference to memory is required to fetch the operand.
 It is also called as absolute addressing mode.

Example-

 ADD X will increment the value stored in the accumulator by the value stored at memory location X.
AC ← AC + [X]
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5. Indirect Addressing Mode-

In this addressing mode,

 The address field of the instruction specifies the address of memory location that contains the effective
address of the operand.
 Two references to memory are required to fetch the operand.

Example-

 ADD X will increment the value stored in the accumulator by the value stored at memory location
specified by X.
AC ← AC + [[X]]

6. Register Direct Addressing Mode-

In this addressing mode,

 The operand is contained in a register set.
 The address field of the instruction refers to a CPU register that contains the operand.
 No reference to memory is required to fetch the operand.
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Example-

 ADD R will increment the value stored in the accumulator by the content of register R.
AC ← AC + [R]

NOTE-

It is interesting to note-
 This addressing mode is similar to direct addressing mode.
 The only difference is address field of the instruction refers to a CPU register instead of main memory.

7. Register Indirect Addressing Mode-

In this addressing mode,

 The address field of the instruction refers to a CPU register that contains the effective address of the
operand.
 Only one reference to memory is required to fetch the operand.
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Example-

 ADD R will increment the value stored in the accumulator by the content of memory location specified in
register R.
AC ← AC + [[R]]

NOTE-

It is interesting to note-
 This addressing mode is similar to indirect addressing mode.
 The only difference is address field of the instruction refers to a CPU register.

8. Relative Addressing Mode-

In this addressing mode,

 Effective address of the operand is obtained by adding the content of program counter with the address
part of the instruction.

Effective Address
= Content of Program Counter + Address part of the instruction
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NOTE-

 Program counter (PC) always contains the address of the next instruction to be executed.
 After fetching the address of the instruction, the value of program counter immediately increases.
 The value increases irrespective of whether the fetched instruction has completely executed or not.

9. Indexed Addressing Mode-

In this addressing mode,

 Effective address of the operand is obtained by adding the content of index register with the address
part of the instruction.

Effective Address
= Content of Index Register + Address part of the instruction
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10. Base Register Addressing Mode-

In this addressing mode,

 Effective address of the operand is obtained by adding the content of base register with the address
part of the instruction.

Effective Address
= Content of Base Register + Address part of the instruction
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11. Auto-Increment Addressing Mode-

 This addressing mode is a special case of Register Indirect Addressing Mode where-

Effective Address of the Operand

= Content of Register

In this addressing mode,

 After accessing the operand, the content of the register is automatically incremented by step size ‘d’.
 Step size ‘d’ depends on the size of operand accessed.
 Only one reference to memory is required to fetch the operand.

Example-
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Assume operand size = 2 bytes.

Here,
 After fetching the operand 6B, the instruction register RAUTO will be automatically incremented by 2.
 Then, updated value of RAUTO will be 3300 + 2 = 3302.
 At memory address 3302, the next operand will be found.

NOTE-

In auto-increment addressing mode,

 First, the operand value is fetched.
 Then, the instruction register RAUTO value is incremented by step size ‘d’.

12. Auto-Decrement Addressing Mode-

 This addressing mode is again a special case of Register Indirect Addressing Mode where-

Effective Address of the Operand

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= Content of Register – Step Size

In this addressing mode,

 First, the content of the register is decremented by step size ‘d’.
 Step size ‘d’ depends on the size of operand accessed.
 After decrementing, the operand is read.
 Only one reference to memory is required to fetch the operand.

Example-

Assume operand size = 2 bytes.

Here,
 First, the instruction register RAUTO will be decremented by 2.
 Then, updated value of RAUTO will be 3302 – 2 = 3300.
 At memory address 3300, the operand will be found.

RLC, RRC, RAL, RAR, CMA, CMC, STC

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1. RLC: - Each binary bit of the accumulator is rotated left by one position. Bit D7 is placed in the position
of D0 as well as in the Carry flag. CY is modified according to bit D7. Any other bit is not affected.

Eg: - RLC

2. RRC: - Each binary bit of the accumulator is rotated right by one position. Bit D0 is placed in the
position of D7 as well as in the Carry flag. CY is modified according to bit D0. Any other bit is not
affected.

Eg: - RRC

3. RAL: - Each binary bit of the accumulator is rotated left by one position through the Carry flag. Bit D7 is
placed in the Carry flag, and the Carry flag is placed in the least significant position D0. CY is modified
according to bit D7.

Eg: - RAL
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4. RAR: - Each binary bit of the accumulator is rotated right by one position through the Carry flag. Bit D0
is placed in the Carry flag, and the Carry flag is placed in the most significant position D7. CY is modified
according to bit D0.

Eg: - RAR

5. CMA: - The content of accumulator is complemented.

Eg: - CMA

6. CMC: - The carry flag is complemented.

Eg: - CMC

7. STC: - This instruction sets the carry flag .

Eg: - STC

CMP, CPI, ANA, ANI, XRA,XRI, ORA, ORI

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1. CMP: - (compare register or memory with accumulator) The contents of the operand register or
memory are M compared with the contents of the accumulator. Both contents are preserved . The result
of the comparison is shown by setting the flags of the PSW as follows:

if (A) < reg/mem: carry flag is set.

if (A) = reg/mem:

zero flag is set.

if (A) > reg/mem: carry and zero flags are reset.

Eg: - CMP B

CMP M

2. CPI: - (compare immediate with accumulator) The second byte (8-bit data) is compared with the
contents of the accumulator. The values being compared remain unchanged. The result of the
comparison is shown by setting the flags of the PSW as follows:

if (A) < data: carry flag is set

if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset

Eg: - CPI 89H

3. ANA: - logical AND operation is performed with the specified register or memory with accumulator.

Eg: - ANA B

ANA M
35

4. ANI: - (AND operation with immediate data) AND operation is performed between accumulator and
specified immediate data.

Eg: - ANI 30H

5.XRA: - The content of accumulator are exclusive OR with specified register or memory location.

Eg: - XRA B

XRA M

6. XRI: - The content of accumulator are exclusive OR with the immediate data.

Eg: - XRI 30H

36

7. ORA: - Logical OR operation is performed between accumulator and specified register and memory
location.

Eg: - ORA B

ORA M

8. ORI: - Logical OR operation is performed between accumulator and immediate data.

Eg: - ORI 30H

MOV, MVI, LDA, LDAX, LXI, LHLD, STA, STAX,SHLD

1.MOV: - This instruction is used to copy the data from one place to another.

Eg: - MOV Rd, Rs (This instruction copies the content of Rs to Rd)

MOV M,Rs (This instruction copies the content of register Rs to memory location pointed by HL
Register)
MOV Rd, M (This instruction copies the content of memory location pointed by the HL
register to the register Rd.)

2.MVI: - move immediate date to a register or memory location.

37

Eg: - MVI Rd, #30H (30h is stored in register Rd)

MVI M, #30H(30h is stored in memory location pointed by HL Reg)

3.LDA: - Load accumulator. (this instruction copies the data from a given 16 bit address to the
accumulator)

Eg: - LDA 3000H (content of memory location 3000h is coppied in accumulator)

4.LDAX(Load accumulator indirect): - The contents of the designated register pair point to a memory
location. This instruction copies the contents of that memory location into the accumulator. The contents
of either the register pair or the memory location are not altered.

Eg: - LDAX B
38
5.LXI(Load register pair immediate): - The instruction loads 16-bit data in the register pair designated in
the
operand.
Eg: - LXI H, 2034H (2034H is stored in HL pair so that it act as memory pointer)

LXI H, XYZ (address of level XYZ is copied in HL pair)

6.LHLD(Load H and L register direct): - this instruction loads the contents of the 16- bit memory location
into the HL register pair.

Eg: - LHLD 3000H (the content of location 3000h is copied into the HL reg pair)

7.STA: - the content of accumulator are copied into the memory location.

Eg: - STA 3000H (the content of accumulator is stored into the memory location 3000h)

8.STAX(Store accumulator indirect): - The contents of the accumulator are copied into the memory
location specified by the contents of the operand (register pair). The contents of the accumulator are not
altered.
39
Eg: - STAX B (the content of accumulator is stored into the memory location specified by the BC register
pair.)

9.SHLD(store H and L register direct): - The contents of register L are stored into the memory location
specified by the 16-bit address in the operand and the contents of H register are stored into the next
memory location by incrementing the operand. The contents of registers HL are not altered. This is a 3 -
byte instruction, the second byte specifies the low-order address and the third byte specifies the high-
order address.

Eg: - SHLD 3000H

Instruction Set 8085

1. Control
2. Logical
3. Branching
4. Arithmetic
5. Data Transfer

Control Instructions

Opcode Operand Explanation of Description

Instruction

NOP none No operation No operation is performed. The instruction is fetched and decoded. However
no operation is executed.
40

Example: NOP

HLT none Halt and enter The CPU finishes executing the current instruction and halts any further
wait state execution. An interrupt or reset is necessary to exit from the halt state.

Example: HLT

DI none Disable The interrupt enable flip-flop is reset and all the interrupts except the TRAP
interrupts are disabled. No flags are affected.

Example: DI

EI none Enable The interrupt enable flip-flop is set and all interrupts are enabled. No flags
interrupts are affected. After a system reset or the acknowledgement of an interrupt, the
interrupt enable flipflop is reset, thus disabling the interrupts. This instruction
is
necessary to reenable the interrupts (except TRAP).

Example: EI

RIM none Read interrupt This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5,
mas 5.5 and read serial data input bit. The instruction loads eight bits in the
accumulator with the following interpretations.

Example: RIM

SIM none Set interrupt This is a multipurpose instruction and used to implement the 8085 interrupts
mask 7.5, 6.5, 5.5, and serial data output. The instruction interprets the accumulator
contents as follows.

Example: SIM

LOGICAL INSTRUCTIONS

Opcode Operand Explanation of Description

Instruction

CMP R Compare register The contents of the operand (register or memory) are M compared with
or memory with the contents of the accumulator. Both contents are preserved . The result
M accumulator of the comparison is shown by setting the flags of the PSW as follows:
41
if (A) < (reg/mem): carry flag is set
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset

Example: CMP B or CMP M

CPI 8-bit Compare The second byte (8-bit data) is compared with the contents of the
data immediate with accumulator. The values being compared remain unchanged. The result of
accumulator the comparison is shown by setting the flags of the PSW as follows:

if (A) < data: carry flag is set

if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset

Example: CPI 89H

ANA R Logical AND
register or memory
M with accumulator
The contents of the accumulator are logically ANDed with M the contents
of the operand (register or memory), and the result is placed in the
accumulator. If the operand is a memory location, its address is specified
by the contents of HL registers. S, Z, P are modified to reflect the result of
the operation. CY is reset. AC is set.

Example: ANA B or ANA M

ANI 8-bit Logical AND The contents of the accumulator are logically ANDed with the
data immediate with 8-bit data (operand) and the result is placed in the
accumulator accumulator. S, Z, P are modified to reflect the result of the
operation. CY is reset. AC is set.

Example: ANI 86H

XRA R Exclusive OR
register or memory
M with accumulator
The contents of the accumulator are Exclusive ORed with M the contents
of the operand (register or memory), and the result is placed in the
accumulator. If the operand is a memory location, its address is specified
by the contents of HL registers. S, Z, P are modified to reflect the result of
the operation. CY and AC are reset.

Example: XRA B or XRA M

XRI 8-bit Exclusive OR The contents of the accumulator are Exclusive ORed with the 8-bit data
data immediate with (operand) and the result is placed in the accumulator. S, Z, P are modified
accumulator to reflect the result of the operation. CY and AC are reset.

Example: XRI 86H

ORA R Logical OR register
or memory with
M accumulator
The contents of the accumulator are logically ORed with M the contents
of the operand (register or memory), and the result is placed in the
accumulator. If the operand is a memory location, its address is specified
by the contents of HL registers. S, Z, P are modified to reflect the result of
the operation. CY and AC are reset.
42
Example: ORA B or ORA M

ORI 8-bit Logical OR The contents of the accumulator are logically ORed with the 8-bit data
data immediate with (operand) and the result is placed in the accumulator. S, Z, P are modified
accumulator to reflect the result of the operation. CY and AC are reset.

Example: ORI 86H

RLC none Rotate accumulator Each binary bit of the accumulator is rotated left by one position. Bit D7 is
left placed in the position of D0 as well as in the Carry flag. CY is modified
according to bit D7. S, Z, P, AC are not affected.

Example: RLC

RRC none Rotate accumulator Each binary bit of the accumulator is rotated right by one position. Bit D0
right is placed in the position of D7 as well as in the Carry flag. CY is modified
according to bit D0. S, Z, P, AC are not affected.

Example: RRC

RAL none Rotate accumulator Each binary bit of the accumulator is rotated left by one position through
left through carry the Carry flag. Bit D7 is placed in the Carry flag, and the Carry flag is placed
in the least significant position D0. CY is modified according to bit D7. S,
Z, P, AC are not affected.

Example: RAL

RAR none Rotate accumulator Each binary bit of the accumulator is rotated right by one position through
right through carry the Carry flag. Bit D0 is placed in the Carry flag, and the Carry flag is placed
in the most significant position D7. CY is modified according to bit D0. S,
Z, P, AC are not affected.

Example: RAR

CMA none Complement The contents of the accumulator are complemented. No flags are affected.
accumulator
Example: CMA

CMC none Complement carry The Carry flag is complemented. No other flags are affected.

Example: CMC

STC none Set Carry Set Carry

Example: STC

BRANCHING INSTRUCTIONS
43

Opcode Operand Explanation of Description

Instruction

JMP 16-bit Jump The program sequence is transferred to the

address unconditionally memory location specified by the 16-bit
address given in the operand.

Example: JMP 2034H or JMP XYZ

Flag 16-bit Jump The program sequence is transferred to the

Opcode Description address conditionally memory location specified by the 16-bit
Status
address given in the operand based on the
JC Jump on Carry CY = 1
specified flag of the PSW as described below.
Jump on no
JNC CY = 0 Example: JZ 2034H or JZ XYZ
Carry
Jump on
JP S=0
positive
JM Jump on minus S=1
JZ Jump on zero Z=1
JNZ Jump on no zero Z = 0
Jump on parity
JPE P=1
even
Jump on parity
JPO P=0
odd

Flag 16-bit Unconditional The program sequence is transferred to the

Opcode Description address subroutine call memory location specified by the 16-bit
Status
address given in the operand. Before the
CC Call on Carry CY = 1
transfer, the address of the next instruction
Call on no after CALL (the contents of the program
CNC CY = 0
Carry counter) is pushed onto the stack.
CP Call on positive S = 0
Example: CALL 2034H or CALL XYZ
CM Call on minus S=1
CZ Call on zero Z=1 Step 1: When a CALL instruction is
executed first ,save the returning
CNZ Call on no zero Z = 0 address on the top of the stack .
Call on parity
CPE P=1 Step2: Then microprocessor jumps
even
into the specified CALL location where
Call on parity
CPO P=0 the subroutine is present.
odd
Step3: Execute the subroutine.The
subroutine is terminated by the RET
instruction. When the microprocessor
executes this RET instruction,it will
44
fetch the returning address from the
top of the stack.

Step4: After getting the address from

the top of the stack, microprocessor
resumes its execution in the main
program.

RET none Return from The program sequence is transferred from

subroutine the subroutine to the calling program. The
unconditionally two bytes from the top of the stack are
copied into the program counter,and
program execution begins at the new
address.

Example: RET

Flag none Return from The program sequence is transferred from

Opcode Description subroutine the subroutine to the calling program based
Status
conditionally on the specified flag of the PSW as described
RC Return on Carry CY = 1
below. The two bytes from the top of the
Return on no stack are copied into the program counter,
RNC CY = 0
Carry and program execution begins at the new
Return on address.
RP S=0
positive
Example: RZ
RM Return on minus S = 1
RZ Return on zero Z=1
Return on no
RNZ Z=0
zero
Return on parity
RPE P=1
even
Return on parity
RPO P=0
odd

PCHL none Load program The contents of registers H and L are copied
counter with HL into the program counter. The contents of H
contents are placed as the high-order byte and the
contents of L as the low-order byte.

Example: PCHL

RST 0-7 Restart The RST instruction is equivalent to a 1-byte

call instruction to one of eight memory
locations depending upon the number. The
instructions are generally used in conjunction
with interrupts and inserted using external
45
hardware. However these can be used as
software instructions in a program to transfer
program execution to one of the eight
locations. The addresses are:

Restart
Instruction
Address
RST 0 0000H
RST1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H

The 8085 has four additional interrupts and

these interrupts generate RST instructions
internally and thus do not require any
external hardware. These instructions and
their Restart addresses are:

Restart
Interrupt
Address
TRAP 0024H
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH

Arithmetic Instructions

Opcode Operand Explanation of Description

Instruction
46
ADD R Add register or The contents of the operand (register or memory) are added to the
memory, to contents of the accumulator and the result is stored in the accumulator.
M accumulator If the operand is a memory location, its location is specified by the
contents of the HL registers. All flags are modified to reflect the result
of the addition.

Example: ADD B or ADD M

ADC R Add register to The contents of the operand (register or memory) and M the Carry flag
accumulator with are added to the contents of the accumulator and the result is stored in
M carry the accumulator. If the operand is a memory location, its location is
specified by the contents of the HL registers. All flags are modified to
reflect the result of the addition.

Example: ADC B or ADC M

ADI 8-bit data Add immediate to The 8-bit data (operand) is added to the contents of the accumulator
accumulator and the result is stored in the accumulator. All flags are modified to
reflect the result of the addition.

Example: ADI 45H

ACI 8-bit data Add immediate to The 8-bit data (operand) and the Carry flag are added to the contents
accumulator with of the accumulator and the result is stored in the accumulator. All flags
carry are modified to reflect the result of the addition.

Example: ACI 45H

LXI Reg. pair, Load register pair The instruction loads 16-bit data in the register pair designated in the
16-bit data immediate operand.

Example: LXI H, 2034H or LXI H, XYZ

DAD Reg. pair Add register pair to The 16-bit contents of the specified register pair are added to the
H and L registers contents of the HL register and the sum is stored in the HL register. The
contents of the source register pair are not altered. If the result is larger
than 16 bits, the CY flag is set. No other flags are affected.

Example: DAD H

SUB R Subtract register or The contents of the operand (register or memory ) are subtracted from
memory from the contents of the accumulator, and the result is stored in the
M accumulator accumulator. If the operand is a memory location, its location is specified
by the contents of the HL registers. All flags are modified to reflect the
result of the subtraction.

Example: SUB B or SUB M

SBB R Subtract source The contents of the operand (register or memory ) and M the Borrow
and borrow from flag are subtracted from the contents of the accumulator and the result
M accumulator is placed in the accumulator. If the operand is a memory location, its
47
location is specified by the contents of the HL registers. All flags are
modified to reflect the result of the subtraction.

Example: SBB B or SBB M

SUI 8-bit data Subtract immediate The 8-bit data (operand) is subtracted from the contents of the
from accumulator accumulator and the result is stored in the accumulator. All flags are
modified to reflect the result of the subtraction.

Example: SUI 45H

SBI 8-bit data Subtract immediate The contents of register H are exchanged with the contents of register
from accumulator D, and the contents of register L are exchanged with the contents of
with borrow register E.

Example: XCHG

INR R Increment register The contents of the designated register or memory) are incremented by
or memory by 1 1 and the result is stored in the same place. If the operand is a memory
M location, its location is specified by the contents of the HL registers.

Example: INR B or INR M

INX R Increment register The contents of the designated register pair are incremented by 1 and
pair by 1 the result is stored in the same place.

Example: INX H

DCR R Decrement register The contents of the designated register or memory are M decremented
or memory by 1 by 1 and the result is stored in the same place. If the operand is a
M memory location, its location is specified by the contents of the HL
registers.

Example: DCR B or DCR M

DCX R Decrement register The contents of the designated register pair are decremented by 1 and
pair by 1 the result is stored in the same place.

Example: DCX H

DAA none Decimal adjust The contents of the accumulator are changed from a binary value to two
accumulator 4-bit binary coded decimal (BCD) digits. This is the only instruction that
uses the auxiliary flag to perform the binary to BCD conversion, and the
conversion procedure is described below. S, Z, AC, P, CY flags are altered
to reflect the results of the operation.

If the value of the low-order 4-bits in the accumulator is greater than 9

or if AC flag is set, the instruction adds 6 to the low-order four bits.
48
If the value of the high-order 4-bits in the accumulator is greater than 9
or if the Carry flag is set, the instruction adds 6 to the high-order four
bits.

Example: DAA

Data Transfer Instructions

Opcode Operand Explanation of Description

Instruction

MOV Rd, Rs Copy from This instruction copies the contents of the source register into the
source(Rs) to destination register; the contents of the source register are not
M, Rs destination(Rd) altered. If one of the operands is a memory location, its location is
specified by the contents of the HL registers.
Rd, M
Example: MOV B, C or MOV B, M

MVI Rd, data Move immediate The 8-bit data is stored in the destination register or memory. If the
8-bit operand is a memory location, its location is specified by the
M, data contents of the HL registers.

Example: MVI B, 57H or MVI M, 57H

LDA 16-bit Load The contents of a memory location, specified by a 16-bit address in
address accumulator the operand, are copied to the accumulator. The contents of the
source are not altered.

Example: LDA 2034H

LDAX B/D Reg. Load The contents of the designated register pair point to a memory
pair accumulator location. This instruction copies the contents of that memory
indirect location into the accumulator. The contents of either the register
pair or the memory location are not altered.

Example: LDAX B

LXI Reg. pair, Load register pair The instruction loads 16-bit data in the register pair designated in
16-bit immediate the operand.
data
Example: LXI H, 2034H or LXI H, XYZ
49
LHLD 16-bit Load H and L The instruction copies the contents of the memory location pointed
address registers direct out by the 16-bit address into register L and copies the contents of
the next memory location into register H. The contents of source
memory locations are not altered.

Example: LHLD 2040H

STA 16-bit 16-bit address The contents of the accumulator are copied into the memory
address location specified by the operand. This is a 3-byte instruction, the
second byte specifies the low-order address and the third byte
specifies the high-order address.

Example: STA 4350H

STAX Reg. pair Store The contents of the accumulator are copied into the memory
accumulator location specified by the contents of the operand (register pair). The
indirect contents of the accumulator are not altered.

Example: STAX B

SHLD 16-bit Store H and L The contents of register L are stored into the memory location
address registers direct specified by the 16-bit address in the operand and the contents of
H register are stored into the next memory location by incrementing
the operand. The contents of registers HL are not altered. This is a
3-byte instruction, the second byte specifies the low-order address
and the third byte specifies the high-order address.

Example: SHLD 2470H

XCHG none Exchange H and The contents of register H are exchanged with the contents of
L with D and E register D, and the contents of register L are exchanged with the
contents of register E.

Example: XCHG

SPHL none Copy H and L The instruction loads the contents of the H and L registers into
registers to the the stack pointer register, the contents of the H register provide the
stack pointer high-order address and the contents of the L register provide the
low-order address. The contents of the H
and L registers are not altered.

Example: SPHL

XTHL none Exchange H and The contents of the L register are exchanged with the stack location
L with top of pointed out by the contents of the stack pointer register. The
stack contents of the H register are exchanged with the next stack
location (SP+1); however, the contents of the stack pointer register
are not altered.

Example: XTHL
 50
PUSH Reg. pair Push register pair The contents of the register pair designated in the operand are
onto stack copied onto the stack in the following sequence. The stack pointer
register is decremented and the contents of the highorder register
(B, D, H, A) are copied into that location. The stack pointer register
is decremented again and the contents of the low-order register (C,
E, L, flags) are copied to that location.

Example: PUSH B or PUSH A

POP Reg. pair Pop off stack to The contents of the memory location pointed out by the stack
register pair pointer register are copied to the low-order register (C, E, L, status
flags) of the operand. The stack pointer is incremented by 1 and the
contents of that memory location are copied to the high-order
register (B, D, H, A) of the operand. The stack pointer register is
again incremented by 1.

Example: POP H or POP A

OUT 8-bit Output data from The contents of the accumulator are copied into the I/O port
port accumulator to a specified by the operand.
address port with 8-bit
address Example: OUT F8H

IN 8-bit Input data to The contents of the input port designated in the operand are read
port accumulator from and loaded into the accumulator.
address a port with 8-bit
address Example: IN 8CH

Add two 16-bit numbers

Statement: Add the 16-bit number in memory locations 4000H and 4001H to the 16-bit number in memory
locations 4002H and 4003H. The most significant eight bits of the two numbers to be added are in memory
locations 4001H and 4003H. Store the result in memory locations 4004H and 4005H with the most significant byte in
memory location 4005H.

1. Sample problem:
2. (4000H) = 15H
3. (4001H) = 1CH
4. (4002H) = B7H
5. (4003H) = 5AH
6. Result = 1C15 + 5AB7H = 76CCH
7. (4004H) = CCH
8. (4005H) = 76H
9.
10. Source Program 1:
11. LHLD 4000H : "Get first I6-bit number in HL"
 51
12. XCHG : "Save first I6-bit number in DE"
13. LHLD 4002H : "Get second I6-bit number in HL"
14. MOV A, E : "Get lower byte of the first number"
15. ADD L : "Add lower byte of the second number"
16. MOV L, A : "Store result in L register"
17. MOV A, D : "Get higher byte of the first number"
18. ADC H : "Add higher byte of the second number with CARRY"
19. MOV H, A : "Store result in H register"
20. SHLD 4004H : "Store I6-bit result in memory locations 4004H and 4005H"
21. HLT : "Terminate program execution"

1. Source program 2:
2. LHLD 4000H : Get first I6-bit number
3. XCHG : Save first I6-bit number in DE
4. LHLD 4002H : Get second I6-bit number in HL
5. DAD D : Add DE and HL
6. SHLD 4004H : Store I6-bit result in memory locations 4004H and 4005H.
7. HLT : Terminate program execution

NOTE: In program 1, eight bit addition instructions are used (ADD and ADC) and addition is performed in two steps.
First lower byte addition using ADD instruction and then higher byte addition using ADC instruction.In program 2,
16-bit addition instruction (DAD) is used.

Add contents of two memory locations

Statement: Add the contents of memory locations 40001H and 4001H and place the result in the memory locations
4002Hand 4003H.

1. Sample problem:
2. (4000H) = 7FH
3. (400lH) = 89H
4. Result = 7FH + 89H = lO8H
5. (4002H) = 08H
6. (4003H) = 0lH
7. Source program:
8. LXI H, 4000H : "HL Points 4000H"
9. MOV A, M : "Get first operand"
10. INX H : "HL Points 4001H"
11. ADD M : "Add second operand"
12. INX H : "HL Points 4002H"
13. MOV M, A : "Store the lower byte of result at 4002H"
14. MVIA, 00 : "Initialize higher byte result with 00H"
15. ADC A : "Add carry in the high byte result"
16. INX H : "HL Points 4003H"
17. MOV M, A : "Store the higher byte of result at 4003H"
18. HLT : "Terminate program execution"
 52

Subtract two 16-bit numbers

Statement: Subtract the 16-bit number in memory locations 4002H and 4003H from the 16-bit number in memory
locations 4000H and 4001H. The most significant eight bits of the two numbers are in memory locations 4001H and
4003H. Store the result in memory locations 4004H and 4005H with the most significant byte in memory location
4005H.

1. Sample problem:
2. (4000H) = 19H
3. (400IH) = 6AH
4. (4004H) = I5H (4003H) = 5CH
5. Result = 6A19H – 5C15H = OE04H
6. (4004H) = 04H
7. (4005H) = OEH
8. Source program:
9. LHLD 4000H : "Get first 16-bit number in HL"
10. XCHG : "Save first 16-bit number in DE"
11. LHLD 4002H : "Get second 16-bit number in HL"
12. MOV A, E : "Get lower byte of the first number"
13. SUB L : "Subtract lower byte of the second number"
14. MOV L, A : "Store the result in L register"
15. MOV A, D : "Get higher byte of the first number"
16. SBB H : "Subtract higher byte of second number with borrow"
17. MOV H, A : "Store l6-bit result in memory locations 4004H and 4005H"
18. SHLD 4004H : "Store l6-bit result in memory locations 4004H and 4005H"
19. HLT : "Terminate program execution"

Finding one’s complement of a number

Statement: Find the l’s complement of the number stored at memory location 4400H and store the complemented
number at memory location 4300H.

1. Sample problem:
 53
2. (4400H) = 55H
3. Result = (4300B) = AAB
4. Source program:
5. LDA 4400B : "Get the number"
6. CMA : "Complement number"
7. STA 4300H : "Store the result"
8. HLT : "Terminate program execution"

Finding Two’s complement of a number

Statement: Find the 2′s complement of the number stored at memory location 4200H and store the complemented
number at memory location 4300H

1. Sample problem:
2. (4200H) = 55H
3. Result = (4300H) = AAH + 1 = ABH
4. Source program:
5. LDA 4200H : "Get the number"
6. CMA : "Complement the number"
7. ADI, 01 H : "Add one in the number"
8. STA 4300H : "Store the result"
9. HLT : "Terminate program execution"

Flag register in 8085 microprocessor

Prerequisite – Registers of 8085 microprocessor
The Flag register is a Special Purpose Register. Depending upon the value of result after any
arithmetic and logical operation the flag bits become set (1) or reset (0). In 8085 microprocessor, flag
register consists of 8 bits and only 5 of them are useful.
The 5 flags are:

1. Sign Flag (S) – After any operation if the MSB (B(7)) of the result is 1, it indicates the number is
negative and the sign flag becomes set, i.e. 1. If the MSB is 0, it indicates the number is positive
and the sign flag becomes reset i.e. 0.
from 00H to 7F, sign flag is 0
from 80H to FF, sign flag is 1
1- MSB is 1 (negative)
0- MSB is 0 (positive)
54
Example:
MVI A 30 (load 30H in register A)
MVI B 40 (load 40H in register B)
SUB B (A = A – B)
These set of instructions will set the sign flag to 1 as 30 – 40 is a negative number.
MVI A 40 (load 40H in register A)
MVI B 30 (load 30H in register B)
SUB B (A = A – B)
These set of instructions will reset the sign flag to 0 as 40 – 30 is a positive number.
2. Zero Flag (Z) – After any arithmetical or logical operation if the result is 0 (00)H, the zero flag
becomes set i.e. 1, otherwise it becomes reset i.e. 0.
00H zero flag is 1.
from 01H to FFH zero flag is 0
1- zero result
0- non-zero result
Example:
MVI A 10 (load 10H in register A)
SUB A (A = A – A)
These set of instructions will set the zero flag to 1 as 10H – 10H is 00H
3. Auxiliary Carry Flag (AC) – This flag is used in BCD number system(0-9). If after any arithmetic
or logical operation D(3) generates any carry and passes on to B(4) this flag becomes set i.e. 1,
otherwise it becomes reset i.e. 0. This is the only flag register which is not accessible by the
programmer
1-carry out from bit 3 on addition or borrow into bit 3 on subtraction
0-otherwise
Example:
MOV A 2B (load 2BH in register A)
MOV B 39 (load 39H in register B)
ADD B (A = A + B)
These set of instructions will set the auxiliary carry flag to 1, as on adding 2B and 39, addition of
lower order nibbles B and 9 will generate a carry.
4. Parity Flag (P) – If after any arithmetic or logical operation the result has even parity, an even
number of 1 bits, the parity register becomes set i.e. 1, otherwise it becomes reset i.e. 0.
1-accumulator has even number of 1 bits
0-accumulator has odd parity
Example:
MVI A 05 (load 05H in register A)
This instruction will set the parity flag to 1 as the BCD code of 05H is 00000101, which contains
even number of ones i.e. 2.
5. Carry Flag (CY) – Carry is generated when performing n bit operations and the result is more
than n bits, then this flag becomes set i.e. 1, otherwise it becomes reset i.e. 0.
During subtraction (A-B), if A>B it becomes reset and if (A<B) it becomes set.
Carry flag is also called borrow flag.
1-carry out from MSB bit on addition or borrow into MSB bit on subtraction
0-no carry out or borrow into MSB bit
Example:
55
MVI A 30 (load 30H in register A)
MVI B 40 (load 40H in register B)
SUB B (A = A – B)
These set of instructions will set the carry flag to 1 as 30 – 40 generates a carry/borrow.
MVI A 40 (load 40H in register A)
MVI B 30 (load 30H in register B)
SUB B (A = A – B)
These set of instructions will reset the sign flag to 0 as 40 – 30 does not generate any
carry/borrow.

Hexadecimal Addition

Example − Addition

Hexadecimal Subtraction
The subtraction of hexadecimal numbers follow the same rules as the subtraction of numbers in any
other number system. The only variation is in borrowed number. In the decimal system, you borrow a
group of 1010. In the binary system, you borrow a group of 2 10. In the hexadecimal system you borrow
a group of 1610.
56
Example - Subtraction

MY POINT OF VIEW FOR CALCULATING

ADDITION OF HEXADECIMAL NO.
ADDITION OF HEXADECIMAL NO.

EA+AE=

FIRST RHS A+E i.e A=10,E=14 SO ADDITON OF 10+14=24 AND DO 24-15=9 THE AGAIN DO ONE DECREAMENT i.e 9-1=8

SO A+E=8 WITH HAVING CARRY 1

CARRY=1

E A
A E
8
NOW DO THE CALCULATION OF REMAINING BITS

i.e E+A=24+1 CARRY=25 NOW 25-15=10-1=9

SO E+A+1=9 WITH 1 CARRY

SO

CARRY=1

E A
+A E
9 8
SO FINAL RESULT

E A
+A E
19 8

ADDITION OF TWO 8-BIT NO. USING 8085 MICROPROCESSOR

KIT
57
EA+AE=198

OPERATION HEX CODE

MVI A,EA 3E,EA
MVI B,AE 06,AE
ADD B 80
LXI H,8085 21,85,80
MOV M,A 77
MVI A,00 3E,00
ADC A 8F
INX H 23
MOV M,A 77
HLT 76
FIRST STEP :- LOADING IN RAM
RESET FIRST TO CLEAR RAM-> EXM MEM->8000->NEXT->3E -> NEXT-> EA-> NEXT->06-> NEXT-
>AE-> NEXT->80-> NEXT->21-> NEXT->85-> NEXT->80-> NEXT->77-> NEXT->3E-> NEXT->00->
NEXT->8F-> NEXT->23-> NEXT->77-> NEXT->76-> NEXT->RESET

SECOND STEP:- EXECUTION

GO->8000(I.E FIRST MEMORY ADDRESS)->EXECUTE->

THIRD STEP :- SEE THE RESULT

RESET-> EXM MEM-> NEXT->”YOU WILL SEE RESULT HERE” -> NEXT->”01/00(IF CARRY THEN
01 ELSE 00)”
58
ADDITION OF TWO 16-BIT NO. USING 8085
MICROPROCESSOR KIT
1423
+3218
463B

OPERATION HEX CODE

MVI A,23 3E,23
MVI B,18 06,18
ADD B 80
LXI H,2050 21,50,20
MOV M,A 77
MVI A,14 3E,14
MVI B,32 06,32
ADC B 88
INX H 23
MOV M,A 77
MVI A,00 3E,00
ADC A 8F
INX H 23
MOV M,A 77
HLT 76

IT WILL SHOW YOU RESULT

AT ADDRESS 2050 3B
AT ADDRESS 2051 46
AT ADDRESS 2052 00 (i.e NO CARRY=00,CARRY=01)

SUBTRACTION OF TWO 8-BIT NO.

THERE CAN BE TWO CONDITION FOR SUBTRACTION i.e
59
1. LARGER NO.- SMALLER NO.
2. SMALLER NO.- LARGER NO.
SO THIS PROGRAME IS VALID FOR BOTH TWO CASES

WE ARE CALCULATING FOR

03-08=08-03=05
ADDRESS OPERATION HEX CODE
8000,8001 MVI A,03 3E,03
8002,8003 MVI B,08 06,08
8004 SUB B 90
8005,8006,8007 LXI H,2050 21,50,20
8008,8009,800A JNC 800D (GO TO ADDRESS) D2,OD,80
800B CMA 2F
800C INR A 3C
800D MOV M,A 77
800E HLT 76

SUBTRACTION OF TWO 16-BIT NO.

2512

-1046

14CC

OPERATION HEX CODE

MVI A,12 3E,12
MVI B,46 06,46
SUB B 90
LXI H,5000 21,00,50
MOV M,A 77
INX H 23
60
MVI A,25 3E,25
MVI B,10 06,10
SBB B 98
MOV M,A 77
HLT 76