EXPERIMENT NO: 01

TITLE OF EXPERIMENT: Implementation of Multiplexer & Decoder using

VHDL

1
A. DIAGRAM:

1. 4:1 Multiplexer:

B
4:1 Y
MUX
C

S1 S0

Truth Table:

S1 S0 Y
0 0 A
0 1 B
1 0 C
1 1 D

2
2. 2:4 Decoder:

Y0

A Y1
2:4
Decoder
B Y2

Y3

Truth Table:

A B Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

3
 EXPERIMENT NO.1

1.1 AIM: 1. To write VHDL code for 4:1 Multiplexer and verify the result using
FPGA/CPLD kit.
2. To write VHDL code for 2:4 Decoder and verify the result using FPGA/CPLD
kit.

1.2 APPARATUS: 1. Computer with Xilinx software.

2. FPGA/CPLD kit with JTAG cable.

1.3 PROCEDURE:
1. Write a VHDL code for 4:1 Multiplexer and 2:4 Decoder in three different modeling
methods (Behavioral, Dataflow and Structural).
2. Verify the functional simulation after synthesizing the code.
3. Implement the code and verify the timing simulation.
4. Download the program on FPGA/CPLD and verify the operation.
5. Generate the RTL schematic for each modeling style.

1.4 RESULTS:
1. Operations of 4:1 multiplexer and 2:4 decoder are verified on FPGA/CPLD kit.
2. The worst case timing delay observed during timing simulation for 4:1 multiplexer is
___________.
3. The percentage of FPGA/CPLD utilized for 4:1 multiplexer is
_____________ (using behavioral)
_____________ (using structural)
_____________ (using dataflow)
4. The worst case timing delay observed during timing simulation for 2:4 decoder is
___________.
5. The percentage of FPGA/CPLD utilized for 2:4 decoder is
_____________ (using behavioral)
_____________ (using structural)
_____________ (using dataflow)

4
1.5 CONCLUSIONS:
1. Which modeling approach generates more hardware?
2. Which type of modeling gives better timings?
3. Which modeling approach is better for purely combinational circuits?
4. What is the program/ erase cycles endurance rating of XC9500 family?
5. How many logic cells are present in XC9572?

5
EXPERIMENT NO: 02

TITLE OF EXPERIMENT: Implementation of 2 bit comparator & full adder

using VHDL

6
A. DIAGRAM:
1. 2 bit Comparator:

A>B
A(1:0)

2 bit
Comparator A=B

B(1:0)
A<B

Truth Table:
2.
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
Full Adder:

Full Adder
Sum
A

7
 Carry
B

Truth Table:

A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

8
 EXPERIMENT NO.2

2.1 AIM:1. To write VHDL code for 2 bit comparator and verify the result using
FPGA/CPLD kit.
2. To write VHDL code for full adder and verify the result using FPGA/CPLD kit.

2.2 APPARATUS: 1. Computer with Xilinx software.

2. FPGA/CPLD kit with JTAG cable.

2.3 PROCEDURE:
1. Write a VHDL code for 2 bit comparator and full adder in any two different modeling
methods.
2. Verify the functional simulation after synthesizing the code.
3. Implement the code and verify the timing simulation.
4. Download the program on FPGA/CPLD and verify the operation.
5. Generate the RTL schematic for each modeling style.

2.4 RESULTS:
1. Operations of 2 bit comparator and full adder are verified on FPGA/CPLD kit.
2. The worst case timing delay observed during timing simulation for 2 bit comparator is
___________.
3. The percentage of FPGA/CPLD utilized for 2 bit comparator is
_____________ (using behavioral)
_____________ (using structural)
4. The worst case timing delay observed during timing simulation for full adder is
___________.
5. The percentage of FPGA/CPLD utilized for full adder is
_____________ (using behavioral)
_____________ (using structural)

9
2.5 CONCLUSIONS:
1. Is it possible to compare floating point numbers?
2. What is maximum frequency of the circuit?
3. How many CLBs are consumed by the design?
4. What is the necessity of slew rate control in CPLD?
5. How many programmable gates are present in XC9572?

10
EXPERIMENT NO: 03

TITLE OF EXPERIMENT: Implementation of 4 bit Arithmetic Logic Unit

(ALU) using VHDL

11
A. DIAGRAM:

4 Bit ALU:

A(3:0) Y(3:0)

4 bit Cout
B(3:0)
ALU
Sign
Cin
Borrow

S(2:0)

Truth Table:

S2 S1 S0 Y
0 0 0 A and B
0 0 1 A or B
0 1 0 A xor B
0 1 1 Not A
1 0 0 A
1 0 1 A+B
1 1 0 A+1
1 1 1 A-B

12
 EXPERIMENT NO.3

3.1 AIM: To write VHDL code for 4 bit ALU and verify the result using
FPGA/CPLD kit.

3.2 APPARATUS: 1. Computer with Xilinx software.

2. FPGA/CPLD kit with JTAG cable.

3.3 PROCEDURE:
1. Write a VHDL code for 4 bit ALU by any one method.
2. Verify the functional simulation after synthesizing the code.
3. Implement the code and verify the timing simulation.
4. Download the program on FPGA/CPLD and verify the operation.
5. Generate the RTL schematic for each modeling style.

3.4 RESULTS:
1. Operations of 4 bit ALU is verified on FPGA/CPLD kit.
2. The worst case timing delay observed during timing simulation for 4 bit ALU is
___________.
3. The percentage of FPGA/CPLD utilized for 4 bit ALU is _____________.

3.5 CONCLUSIONS:
1. What are applications of ALU?
2. What are the different ways to implement ALU? Which is more advantageous?
3. Is it possible to implement ALU without process statement?
4. Which protocol is used for downloading the program on the kit?

13
EXPERIMENT NO: 04

TITLE OF EXPERIMENT: Implementation of D, T, SR and JK flip-flops using

VHDL.

14
A. DIAGRAM:

1. D flip flop: Truth Table:

D Q
D 0 0
D Q 1 1
Clk flip flop

2. T flip flop: Truth Table:

T Q
T 0 Q
T Q 1 Not Q
Clk flip flop

3. SR flip flop: Truth Table:

S R Q
S 0 0 Q
SR Q
Clk 0 1 0
flip flop
1 0 1
R
1 1 Not defined

3. SR flip flop: Truth Table:

J K Q
J 0 0 Q
JK Q
Clk 0 1 0
flip flop
1 0 1
K
1 1 Not Q

15
 EXPERIMENT NO.4

4.1 AIM: To write VHDL code for D, T, SR and JK flip-flops and verify the result using
FPGA/CPLD kit.

4.2 APPARATUS: 1. Computer with Xilinx software.

2. FPGA/CPLD kit with JTAG cable.

4.3 PROCEDURE:
1. Write a VHDL code for D, T, SR and JK flip-flops by any one method.
2. Verify the functional simulation after synthesizing the code.
3. Implement the code and verify the timing simulation.
4. Download the program on FPGA/CPLD and verify the operation.
5. Generate the RTL schematic for each modeling style.

4.4 RESULTS:
1. Operations of D, T, SR and JK flip-flops are verified on FPGA/CPLD kit.
2. The worst case timing delay observed during timing simulation for D, T, SR and JK flip-
flops are ___________ respectively.
3. The percentage of FPGA/CPLD utilized for D, T, SR and JK flip-flops are _____________
respectively.

4.5 CONCLUSIONS:
1. How many logic cells and CLBs are available in XC2S50?
2. Why FPGA is faster than CPLD?
3. What is the function of fast connect switch matrix?
4. Which technology is used to fabricate XC9500 series?

16
EXPERIMENT NO: 05

TITLE OF EXPERIMENT: Implementation of shift register using VHDL.

17
 A. DIAGRAM:

Din
4 bit
Mode
Shift
Q(3:0)
Rst register

Clk

Truth Table:
Clk Rst Mode Direction
X 1 X 0000
Rising edge 0 1 Right shift
Rising edge 0 0 Left shift

18
5.1 AIM: To write VHDL code for shift register with a mode bit to indicate left and right shift
and verify the result using FPGA/CPLD kit.

5.2 APPARATUS: 1. Computer with Xilinx software.

2. FPGA/CPLD kit with JTAG cable.

5.3 PROCEDURE:
1. Write a VHDL code for shift register with a mode bit to indicate left and right shift by any
one method.
2. Verify the functional simulation after synthesizing the code.
3. Implement the code and verify the timing simulation.
4. Download the program on FPGA/CPLD and verify the operation.
5. Generate the RTL schematic for each modeling style.

5.4 RESULTS:
1. Operation of shift register is verified on FPGA/CPLD kit.
2. The worst case timing delay observed during timing simulation for shift register is
___________.
3. The percentage of FPGA/CPLD utilized for shift register is _____________.

5.5 CONCLUSIONS:
1. What is the difference between ASICs and FPGA?
2. Why generally active low reset is used?
3. Which file is used for downloading the program on FPGA device?
4. What are the different pins of JTAG cable?

19
EXPERIMENT NO: 06

TITLE OF EXPERIMENT: Implementation of UP/DOWN Counter using

VHDL.

20
 A. DIAGRAM:

Mode

Rst 4 bit
Counter Count (3:0)

Clk

Truth Table:
Clk Rst Mode Count
X 1 X 0000
Rising edge 0 1 UP
Rising edge 0 0 DOWN

21
 EXPERIMENT NO.6

6.1 AIM: To write VHDL code for Up/Down Counter and verify the result using FPGA/CPLD
kit.

6.2 APPARATUS: 1. Computer with Xilinx software.

2. FPGA/CPLD kit with JTAG cable.

6.3 PROCEDURE:
1. Write a VHDL code for Up/Down Counter by any one method.
2. Verify the functional simulation after synthesizing the code.
3. Implement the code and verify the timing simulation.
4. Download the program on FPGA/CPLD and verify the operation.
5. Generate the RTL schematic for each modeling style.

6.4 RESULTS:
1. Operation of Up/Down Counter is verified on FPGA/CPLD kit.
2. The worst case timing delay observed during timing simulation for Up/Down Counter is
___________.
3. The percentage of FPGA/CPLD utilized for Up/Down Counter is _____________.

6.5 CONCLUSIONS:
1. What is clock skew and how to minimize it?
2. How many Vcc and GND pins are available in XC9572PC84?
3. How many user configurable I/Os in XC9572?
4. Which file is used for downloading the program on FPGA device?

22
EXPERIMENT NO: 07

TITLE OF EXPERIMENT: Implementation of Lift Controller using VHDL.

23
A. DIAGRAM:

X1

X0 Motor
Lift
Rst Controller

Clk Direction

DS

Truth Table:

X1 X0 Function
0 0 Request from ground floor
0 1 Request from first floor
1 0 Request from second floor
1 1 Request from third floor

DS=Door Switch, 0=Open and 1=Close

Lift Controller must generate following outputs:

Motor: 1=ON and 0=OFF
Direction: 1=UP and 0=DOWN

1. Assume initially lift is on ground floor.

2. Don’t consider more than one requests at a time.
3. On each floor check X1 and X0 and decide the direction.

24
 EXPERIMENT NO.7

7.1 AIM: To write VHDL code for Lift Controller and verify the result using
FPGA/CPLD kit.

7.2 APPARATUS: 1. Computer with Xilinx software.

2. FPGA/CPLD kit with JTAG cable.

7.3 PROCEDURE:
1. Write a VHDL code for Lift Controller by any one method.
2. Verify the functional simulation after synthesizing the code.
3. Implement the code and verify the timing simulation.
4. Download the program on FPGA/CPLD and verify the operation.
5. Generate the RTL schematic for each modeling style.

7.4 RESULTS:
1. Operation of Lift Controller is verified on FPGA/CPLD kit.
2. The worst case timing delay observed during timing simulation for Lift Controller is
___________.
3. The percentage of FPGA/CPLD utilized for Lift Controller is _____________.

7.5 CONCLUSIONS:
1. What are the 3 different ways to implement any code using state machine?
2. Compare Moore and Mealy machines?
3. What are the different state encoding techniques? Compare them in brief.
4. Can we represent asynchronous circuits with state diagram?

25
EXPERIMENT NO: 08

TITLE OF EXPERIMENT: Implementation of RAM/FIFO using VHDL.

26
A. DIAGRAM:

Rd_req

Wr_req Full

Rd_ptr
FIFO Empty
Wr_ptr

Clk
Dout(7:0)
Rst

27
 EXPERIMENT NO.8

8.1 AIM: To write VHDL code for RAM/FIFO and verify the result using FPGA/CPLD kit.

8.2 APPARATUS: 1. Computer with Xilinx software.

2. FPGA/CPLD kit with JTAG cable.

8.3 PROCEDURE:
1. Write a VHDL code for RAM/FIFO by any one method.
2. Verify the functional simulation after synthesizing the code.
3. Implement the code and verify the timing simulation.
4. Download the program on FPGA/CPLD and verify the operation.
5. Generate the RTL schematic for each modeling style.

8.4 RESULTS:
1. Operation of RAM/FIFO is verified on FPGA/CPLD kit.
2. The worst case timing delay observed during timing simulation for RAM/FIFO is
___________.
3. The percentage of FPGA/CPLD utilized for RAM/FIFO is _____________.

8.5 CONCLUSIONS:
1. How many address lines are required for RAM/FIFO?
2. Write the applications of RAM/FIFO?
3. What is the difference between RAM and FIFO?
4. Is it synchronous or asynchronous?
5. What are the different ways to write the test bench?

28
EXPERIMENT NO: 09

TITLE OF EXPERIMENT: Implementation of Bidirectional buffer using

VHDL.

29
A. DIAGRAM:

Din

En Bidirectional Dout
Buffer

Do

30
 EXPERIMENT NO.9

9.1 AIM: To write VHDL code for bidirectional buffer and verify the result using
FPGA/CPLD kit.

9.2 APPARATUS: 1. Computer with Xilinx software.

2. FPGA/CPLD kit with JTAG cable.

9.3 PROCEDURE:
1. Write a VHDL code for bidirectional buffer by any one method.
2. Verify the functional simulation after synthesizing the code.
3. Implement the code and verify the timing simulation.
4. Download the program on FPGA/CPLD and verify the operation.
5. Generate the RTL schematic for each modeling style.

9.4 RESULTS:
1. Operation of bidirectional buffer is verified on FPGA/CPLD kit.
2. The worst case timing delay observed during timing simulation for bidirectional buffer is
___________.
3. The percentage of FPGA/CPLD utilized for bidirectional buffer is _____________.

9.5 CONCLUSIONS:
1. What is the application of tristate buffer?
2. What care one should take while writing the testbench of bidirectional buffer?
3. Is buffer mode in VHDL entity indicates tristate buffer?
4. Why tristate is required in digital circuits?

31
EXPERIMENT NO: 10

TITLE OF EXPERIMENT: Implementation of CMOS inverter using

Microwind.

32
A. DIAGRAM:

Inverter

Truth table:

A Y
0 1
1 0

33
 EXPERIMENT NO.10

10.1 AIM: To implement and verify the functionality of CMOS inverter using Microwind.

10.2 APPARATUS: Computer with Microwind Software.

10.3 PROCEDURE:
Part A:
1. Create your own NMOS & PMOS transistors.
2. Use the design rules for 180 nm process.
3. Plot the characteristics of NMOS transistor
Part B:
1. Open the Schematic Editor in Microwind. Click on the transistor symbol in the Symbol
Library on the right.
2. Instantiate nmos or pmos transistors from the symbol library and place them in the editor
window.
3. Connect the drains and sources of the transistors.
4. Connect Vdd and Gnd from the symbol library to the schematic.
5. Connect inputs and output. Input symbols are the first symbol in the first row of the symbol
library. LEDs are used to observe the output. LED symbol is the second symbol in the
second row of the symbol library.
6. Simulate the circuits to check the logic functionality.
Part C:
For Inverter following points to be consired,
1. Design rise & fall time,considering fan out in the form of a capacitive load.
2. Measure current drawn & hence power dissipation.
3. calculate propogation delay.

10.4 RESULTS:

10.5 CONCLUSIONS:
------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------

34
EXPERIMENT NO: 11

TITLE OF EXPERIMENT: Implementation of CMOS NAND gate using

Microwind.

35
A. DIAGRAM:

NAND

Truth Table:

A B Y
0 0 1
0 1 1
1 0 1
1 1 0

36
 EXPERIMENT NO.11

11.1 AIM: To implement and verify the functionality of CMOS NAND gate using Microwind.

11.2 APPARATUS: Computer with Microwind Software.

11.3 PROCEDURE:
Part A:
1. Create your own NMOS & PMOS transistors.
2. Use the design rules for 180 nm process.
3. Plot the characteristics of NMOS transistor
Part B:
1. Open the Schematic Editor in Microwind. Click on the transistor symbol in the Symbol
Library on the right.
2. Instantiate nmos or pmos transistors from the symbol library and place them in the editor
window.
3. Connect the drains and sources of the transistors.
4. Connect Vdd and Gnd from the symbol library to the schematic.
5. Connect inputs and output. Input symbols are the first symbol in the first row of the symbol
library. LEDs are used to observe the output. LED symbol is the second symbol in the
second row of the symbol library.
6. Simulate the circuits to check the logic functionality.

11.4 RESULTS:

11.5 CONCLUSIONS:
------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------

37
EXPERIMENT NO: 12

TITLE OF EXPERIMENT: Implementation of CMOS NOR gate using

Microwind.

38
A. DIAGRAM:

NOR

A B

Truth Table:

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

39
 EXPERIMENT NO.12

12.1 AIM: To implement and verify the functionality of CMOS NOR gate using Microwind.

12.2 APPARATUS: Computer with Microwind Software.

12.3 PROCEDURE:
Part A:
1. Create your own NMOS & PMOS transistors.
2. Use the design rules for 180 nm process.
3. Plot the characteristics of NMOS transistor
Part B:
1. Open the Schematic Editor in Microwind. Click on the transistor symbol in the Symbol
Library on the right.
2. Instantiate nmos or pmos transistors from the symbol library and place them in the editor
window.
3. Connect the drains and sources of the transistors.
4. Connect Vdd and Gnd from the symbol library to the schematic.
5. Connect inputs and output. Input symbols are the first symbol in the first row of the symbol
library. LEDs are used to observe the output. LED symbol is the second symbol in the
second row of the symbol library.
6. Simulate the circuits to check the logic functionality.

12.4 RESULTS:

12.5 CONCLUSIONS:
------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------

40
EXPERIMENT NO: 13

TITLE OF EXPERIMENT: Implementation of priority encoder & parity

detector using VHDL.

41
A. DIAGRAM:

1. 4:2 Priority encoder:

S3

S2 4:2 Y1
4:2
Priority
Priority
Encoder Y0
S1 Encode
r
S0

Truth Table:

S3 S2 S1 S0 Y1 Y0
1 X X X 1 1
0 1 X X 1 0
0 0 1 X 0 1
0 0 0 1 0 0

42
2. Parity generator:

Even

Parity
Generator
Odd

Truth Table:

Dataword Even Odd

00000000 0 1
10000000 1 0
00010000 1 0
11101001 1 0

43
44
 EXPERIMENT NO.13

13.1 AIM:1. To write VHDL code for 4:2 priority encoder and verify the result using
FPGA/CPLD kit.
2. To write VHDL code for parity generator and verify the result using
FPGA/CPLD kit.

13.2 APPARATUS: 1. Computer with Xilinx software.

2. FPGA/CPLD kit with JTAG cable.

13.3 PROCEDURE:
1. Write a VHDL code for 4:2 priority encoder and parity generator.
2. Verify the functional simulation after synthesizing the code.
3. Implement the code and verify the timing simulation.
4. Download the program on FPGA/CPLD and verify the operation.
5. Generate the RTL schematic for each modeling style.

13.4 RESULTS:
1. Operations of 4:2 priority encoder and parity generator are verified on FPGA/CPLD kit.
2. The worst case timing delay observed during timing simulation for 4:2 priority encoder is
___________.
3. The percentage of FPGA/CPLD utilized for 4:2 priority encoder is _____________.
4. The worst case timing delay observed during timing simulation for parity generator is
___________.
5. The percentage of FPGA/CPLD utilized for parity generator is _____________.

45
13.5 CONCLUSIONS:
1. What are the applications of priority encoder and parity generator?
2. How to force the value to the input other than waveform?
3. What is the difference between bit and std_logic?

46