B C C 5 2 x BASIC Computer/Controller

U s e r s Manual

Release 1.0

Copyright ( C ) 1988

Micromint, Inc.
115 Timberlachen Circle
Suite 200 1
Lake Mary, FL 32746
www.micromint.com

All rights reserved

t COPYRIGHT

BCC52, BCC52I and BCC52C are

trademarks and copyright ( c ) 1988 of
MICROMINT I N C .
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Micromint, Inc.
1 1 5 Timberlachen Circle
Suite 200 1
Lake Mary, F'L 32746
www.micromint.com

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THE MICROMINT I N C . makes no representations or warranties

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--- page i ---

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-- REV. 3/88
------ page ii ------
 TABLE OF CONTENTS

SECTION Description Paqe

1.0 An Overview of the BCC52x Boards 1

2.0 The BCC52x Computer/Controller Board

2.1 Processor
2.2 Address Decoding
2.3 Parallel I / O
2.4 Serial 1/0
2.5 EPROM Programmer

3.0 Powering U p the Board 10

4.0 A Word About BASIC

4.1 Variables and Expressions
4.2 Real T i m e Operation A f t e r RUN
5.0 Using t h e Parallel P o r t s 15

6.0 Pinouts of Connectors and Jumpers 18

Address Requirements f o r Interfacing

with Other BCC Series Boards 26
MB08 Eight Slot Card Cage Mountable Mother Board
and UPS Power Supplies 26
BCC52x Computer/Controller Board 27
BCC08 Serial Expansion Board 28
BCC13 Analog to Digital Converter Board 29
BCC18 Dual Serial/Modem Board 30
BCC22 TERM-MITE Smart T e r m i n a l Board 31
ADPSOO Pre-recorded Speech Board 32
BCC25 LCD/Keyboard I / D Board 33
BCC30 Analog to D i g i t a l Converter Board 34
BCC33 1/0 Memory Expansion Board 35
BCC40D & BCC40R Isolated B i t 1/0 Boards 36
BCC53 1/0 Memory Expansion Board 37
BCC55 PROTO (typing) Board 38

8.0 Optional Utilities EPROM (ROM A&B V1.l & V1.1C) 39

9.0 BCC52 (standard) Parts List

9.1 BCC52I Parts List
9.2 BCC52C Parts List

10.0 BCC52 (standard) Silkscreen 45

11.0 BCC52C Schematic 46

 LIST OF FIGURES

B l o c k Diagram of the BCC52x

Language Features of BASIC-52

Block Diagram of the 8 0 5 2 / 8 0 C 5 2 BASIC C h i p 5

Parallel Port Memory Address Possibilities 15

Parallel Port Addressing Example 16
8 2 5 5 / 8 2 C 5 5 (IC2) Port Configuration 17

Micromint Power Supply Specifications 26

Jumper S e t t i n g s f o r 24K RAM & Utilities ROM A&B 39

1.0 An Overview of the BCC52 Series of Boards

Currently, Micromint has available four versions of the BCC52

computer / controller board. These are:
3CC52
BCC52C
---
---
Our standard board (NMOS)
A CMOS version of t h e BCC52
BCC52f-1 --- Extended Ind. temp, version of the BCC52
(-40. to +85'C)

Throughout the rest of this manual all of these boards w i l l

be referred to as t h e BCC52x. Notations will be made whenever a
special case applies.
The BCC52x (standard,I,and 1-1) uses t h e Intel 8052AH-BASIC
chip. T h e BCC52C uses t h e Micromint 80C52-BASIC, but the other
versions of the board may a l s o have t h i s processor installed.
These processors are 8-bit microcontroller chips which contain a
ROM resident 8K byte BASIC interpreter. The BCC52x computer/
controller contains the processor, space f o r 48K bytes of
RAM/EPROM, a 2764/128 (or 27C64/27C128) EPROM programmer, 3
parallel ports, a serial terminal port with auto baud rate
selection, a serial printer port, and is bus compatible with all
the BCC series expansion boards.
It is particularly well suited for process control providing
IF THEN, FOR NEXT, DO WHILE/UNTIL, ONTIME, and CALL statements
among its broad repertoire of i n s t r u c t i o n s (Figure 1.0-1 block
diaqrams t h e hardware and Figure 1.0-2 lists the software
features). Calculations are handled in integer or floating point
math and fully supported with trigonometric and logical operators.
Because of its low system overhead it is extremely fast and
efficient.
Unlike most one-shot EPROM programmers that fill t h e entire
contents of an EPROM regardless of the application program size,
BCC52x treats the EPROM as "write oncen mass storage.

When a BASIC application program is saved to EPROM, it is

tagged with an identifying ROM number and stored only in the
amount of EPROM required to fit the program (plus header and EOF).
Additional application programs can be stared to t h e same EPROM
and recalled for execution by requesting a particular ROM number.
A 27128 (or 27C128) EPROM affords 16 Kbytes of mass storage space.
When it is full (a non-destructive EPROM FULL error will indicate
this), simply erase the present EPROM or insert another. Finally,
since this pseudo mass storage exists in directly addressable
memory space (as opposed to cassettes or disks), it runs at full
CPU speed and stored application programs are instantly
accessible.
The BCC52x bridges the gap between expensive intelligent
control capabilities and hard-to-justify price sensitive c o n t r o l
applications. The full floating point BASIC is fast and e f f i c i e n t
enough f o r the most complicated tasks while the cost effective
design allows it to be considered for many new areas of
implementation.

Page 1
 RS -232
Console
RS - 232 Auxiliary
Printer Serial
Port Port Port

Processor
I I

C D A
N A D Address
T T D Decoder
L A R
-
8K RAM
OOOOH

8K RAM/EPROM
I I I 2000H

8K RAM/EPROM
4000H

8K RAM/EPROM
6000H

8 K or 16K EPROM

EPROM PROGRAMMER 8000H

PORT A PORT B PORT C

Figure 1.0-1 Block Diagram of the BCCSPC

Page 2
COMMANDS OPERATORS

RUN BAUD ADD (+)

CONT CALL DIVIDE ( / )
LIST CLEAR EXPONENTIATION ( * * )
LIST# CLEAR (S&I) MULTIPLY ( * )
LIST@ CLOCK (1&0) SUBTRACT ( - )
NEW DATA LOGICAL AND ( .AND. )
NULL READ LOGICAL OR ( .OR. )
RAM RESTORE .
LOGICAL X-OR ( XOR. )
ElOM DIM NOT( 1
XFER Do-WHILE ABS(
PROG DO-UNTIL INT(
PROG 1 END SGN( 1
PROG2 FOR-TO-STEP saw 1
PROG3 NEXT RND
PROG4 GOSUB LOG( 1
PROG5 RETURN EXP(
PROG6 GOT0 SIN( 1
FPROG ON-GOT0 COS( 1
FPROGl ON-GOSUB TAN( 1
FPROG2 IF-THEN-ELSE ATN( 1
FPROG3 INPUT =,>,>=I<I<=,<>

FPROG4 LET ASCI 1

FPROG5 ONERR CHR(
FPROG6 ONEXl CBY( 1
ONTIME DBY(
PRINT XBY( 1
PRINT GET
PRINT@ IE
PHO. IP
PHO.@ PORT1
PHI. PCON
PHI. # RCAP2
PHI.@ T2CON
PGM TCON
PUSH TMOD
POP TIME
PWM TIMER0
REM TIMER1
RETI TIMER2
STOP XTAL
STRING MTOP
U1(11&0) LEN
UO (1&0) FREE
LD@ PI
ST@
IDLE
RROM

Figure 1.0-2 Language Features of BASIC-52

Page 3
 2.0 The BCC52x Computer/Controller Board
The BCC52x computer/controller is a single board controller/
development system. The 17 chip c i r c u i t is a compact 4 1 / 2 by 6
1/2 inches ( e x a c t l y the same s i z e as the Micromint TERM-MITE smart
terminal if you want a 2 board complete system). It contains RAM/
EPROM, an EPROM programmer, 3 parallel ports, and 2 serial ports.
There are five main sections to the BCC52x board: p r o c e s s o r ,
address decoding and memory, parallel I / O , serial I / O , and EPROM
programmer.

2.1 Processor
The BCC52x computer/controller board is based on the Intel
8052AH-BASIC chip (or in some cases t h e Micromint 80C52-BASIC
chip). This is a prepragrammed versions of the INTEL 8052AH
microcontroller (block diagrammed in Figure 2.1-1). The processor
contains 8K b y t e s of on-chip ROM, 2 5 6 bytes of RAM, three 16 b i t
counter/timers, 6 interrupts, and 32 1/0 lines. he ROM is a
masked BASIC interpreter and the I / O lines are redefined to
address, data, and control lines.
The processor has a 16 bit address and 8 bit data bus (the 8
least significant address bits (AO-A7) and the data bus (DO-D7)
are multiplexed together similar to the 8085 and 2 8 ) . When the
c h i p is powered up it s i z e s consecutive external memory from O O O O H
to end of memory (or memory failure) by alternately writing 55H
and O O H t o e a c h l o c a t i o n . A minimum of 1K bytes of RAM is
required for BCC52x to function and any RAM must be located
starting at 0000H.
Three control lines, RD ( p i n 171, WR (pin 161, and PSEN ( p i n
29) partition the address space as 64K bytes each of program a n d
data memory. However, user called assembly routines and EPROM
programming are unsupported in data memory. For that r e a s o n , t h e
BCC52x as designed are addressed completely as program memory
(RAM/EPROM mode) both for RAM and I / O . The addressing logic is as
follows:

1) The RD and the WR p i n s on t h e processor chip enable RAM

memory from O O O O H to 7FFFH. Addresses are used to
decode the chip select (CS) for the RAM devices and RD
and WR are used to enable the OE and W E or (WR) p i n s
respectively.
2) PSEN is used to enable EPROM memory from 2000H to
7FFFH. Addresses are used to decode the c h i p select (CS)
for the EPROM devices and PSEN is used to enable the
OE p i n .
3 ) Between 8000H and OFFFFH both RD and PSEN are used to
enable either EPROM or RAM memory. RD and PSEN are
logically *'ANDEDWfthrough IC13, a 74HCT08. The WR p i n
on t h e c h i p is used to w r i t e to RAM memory in this same
a d d r e s s space.

Page 4
 T h e SCCS2x reserves the first 512 bytes of External Data
Memory to implement two "softwarefvstacks. These are the control
stack and the arithmetic s t a c k or Argument Stack. Understanding
how the stacks work is only necessary if t h e user wishes to link
BASIC-52 and 8 0 5 2 Assembly Language routines. The details of how
to link to assembly language are covered in t h e Assembly Language
Linkage section of the MCS BASIC-52 User's Manual.

Figure 2.1-1 Block Diagram of the Intel 80CS2AH-BASIC Chip

Page 5
 The c o n t r o l stack occupies locations 96 ( 6 0 H ) through 254
(OFEH) in external RAM memory. This memory is used to s t o r e a l l
information associated with loop control (i. e. DO-WHILE,
DO-UNTIL, and FOR-NEXT) and BASIC subroutines (GOSUB). T h e stack
is initialized to 254 ( O F E H ) and "grows down.g1

The Argument Stack occupies locations 301 ( 1 2 D A ) through 510

(1FEH) in external RAM memory. his s t a c k stares all constants
that B A S I C is currently using. Operations such as Add, S u b t r a c t ,
~ u l t i p l y ,and Divide always operate on the first two numbers on
the Argument Stack and return the result to the Argument Stack.
The argument s t a c k is initialized to S l O ( 1 F E H ) and l'grows downt1 a s
more values are placed on the Argument Stack. Each floating point
number placed on the Argument S t a c k requires 6 b y t e s of storage.
T h e stack pointer (Special Function Register, SP) on the chip
is initialized to 77 ( 4 D H ) . The stack p o i n t e r 'tgrows upw as
values are placed on t h e s t a c k .
2.2 Address Decoding
The processor uses most of t h e first 32K (OH-7FFFH) as s p l i t
memory. DATA (RAM) memory is enabled by the RD line and PROGRAM
(EPROM) memory is enabled by the PSEN line. The BCC52x enables the
same memory by either RD or PSEN. As long a s t h e user's BASIC
and MACHINE routines do not occupy the same address space this is
not a problem. Let's suppose the OPTIONAL UTILITIES EPROM is to be
used (see OPTIONAL UTILITIES EPROM section). It occupies PROGRAM
address space 2000H. P l a c i n g the EPROM in socket IC3 (2000H) and
Ram at OOOOH, 4000H and 6000H. When powered up, the processor
will recognize RAM from OOOOH to lFFFH, the extension EPROM at
2000H and enter the COMMAND mode f o r user input. The RAM from
4000H to 6FFFH will not be recognized because it is not contiguous
with the RAM at 0000B. JP4 allows IC12 to be reassigned to
address 2000H. I C 1 is OOOOH, Ic3 is ZOOOH, I C 8 is 4000H and IC12
can now be 2000H a l s o . J P 5 allows fC1, I C 3 , and IC8 to be
accessed by either DATA or PROGRAM enable (normal mode) or DATA
enable only. In the DATA only mode the processor will only access
these three contiguous sockets as RAM A r e a . JP6 allows IC12 to be
accessed by t h e selection of J P 5 or PROGRAM enable o n l y . I n the
PROGIlAM only mode the processor w i l l only access IC12 a s EPROM
Area. Notice both I C 3 (RAM) and IC12 (EPROM) have t h e same Base
address (2000H). Each is enabled separately by using the RD f o r
the DATA area and PSEN for the PROGRAM area.
Both RD and PSEN are brought out to the edge connector
allowing t h e user to reconfigure memory on expansion boards f o r
either DATA or PROGRAM areas. The 3 most significant address
lines ( A 1 3 - A 1 5 ) are connected to a decoder chip, IC4, which
separates the addressable range into 8 8K memory segments, each
with its own chip select (YO-Y7). The 4 least significant c h i p
selects are connected to 28 pin 64K bit (8K by 8 ) memory devices,
either 2 7 6 4 (or 2 7 C 6 4 ) EPROMs or 6264 ( 5 5 6 4 ' s with the BCC52C)
s t a t i c RAMS, IC1, addressed at OOOOH, must be RAM in order for
board to function. IC locations 3 (2000H-3FFFH), 8 (4000H-5FFFH),
and 12 (6000-7FFFH) can use either RAM or EPROM. IC17 (8000H t h r u
9FFFH or BFFFH) is an EPROM programming socket intended for 2764 /
27128 (or 2 7 C 6 4 / 27C128) EPROMS or RAM.

Page 6
 Altogether there is 48K of memory on the board if you use 4
8K RAMS (in I C s 1,3,8,12) and a 16K EPROM in I C l 2 . T h e memory and
1/0 can be further expanded through the bus using BCC series
expansion cards.
A second decoder, IC14, partitions either C800H-CFFFH or
E800H-EFFFH as eight 256 byte 1/0 blocks. Rather than simply using
the available COOOH or EOOOH strobes from IC13 alone which would
occupy a 2000H address space for a single PIA c h i p , I C 1 6 allows
many peripherals to share the remaining address space by using
o n l y a 256 byte address range. This addressing convention is
consistent w i t h other BCC expansion boards and it i s easy to
configure a 6 4 channel A/D or 128 channel power 1/0 system using
this board w i t h a number of peripheral cards.

2 3 Parallel 1/0
The BCCS2x contains an 8 2 5 5 ( 8 2 C 5 5 i n the BCC52C) P I A which
provides three 8 bit software configurable parallel ports. The
three 1/0 p o r t s , labeled A , B, and C and a write only c o n t r o l port
occupy 4 consecutive addresses in one of the 8 jumper selectable
1/0 blocks. With COOOH selected and YO on IC16, the range would be
C800H thru C803H. Using the X B Y ( ) operator in BASIC, data can be
written to and read from this P I A (you are probably more familiar
w i t h PEEK and POKE. PEEK is accomplished with PRINT XBY(OC802H)
and a POKE is XBY(OC802H)=A). The three parallel port's TTL
compatible outputs are connected a l o n g with ground to a 2 6 p i n
Berg-type header.

2.4 Serial 1/0

There are two serial ports on the BCC52x. One is for the
console 1/0 terminal (IC5 p i n s 1 0 and 11) and the other is an
auxiliary serial output (IC5 p i n 8 ) frequently referred to as the
line printer port. When u s i n g an 1 1 . 0 5 9 2 MHz crystal, t h e console
port does auto baud rate determination on power up (a preset baud
rate can alternatively be stored in EPROM as well). It will
function at 19200 bps with no degradation in operation. The
console serial port format is 8 data bits, no p a r i t y , 1 stop b i t .
T h e B A U F e x p r ] statement is used to set t h e baud rate f o r t h e
line printer port. In order for this statement to properly
calculate the baud rate, the crystal (special function o p e r a t o r
-XTAL) must be correctly assigned ( e . g . XTAL = 900 0 0 0 0 ) . BASIC
assumes a crystal v a l u e of 11.0592 MHz if no XTAL value is
assigned.
The main purpose of the line p r i n t e r port is to let t h e user
make a "hard copywrof program listings and/or data. The command
LIST# and t h e statement PRINT# direct outputs t o t h e l i n e printer
p o r t . I f t h e BAUD [expr) s t a t e m e n t i s not executed before a LIST#
or PRINT# command/statement i s e n t e r e d , the output t o the software
line printer port will be at about 1 bps. It is necessary to
assign a BAUD rate to t h e printer port before u s i n g LIST# or
PRINT#. The maximum baud rate that can be assigned by the BAUD
statement depends on t h e crystal but, 4 8 0 0 b p s is a reasonable
maximum rate. The line printer port format is 8 data b i t s , no
p a r i t y , 2 stop b i t s .
Page 7
 MC1488 and MC1489 (MC14C88 and MC14C89 on t h e BCC52C) level
shifters ( I C s 7 and 6 ) convert t h e TTL logic levels from t h e
console and line p r i n t e r ports to RS-232C (the TTL serial l i n e s
are also connected to the bus to allow use of the TERM-MITE smart
terminal board without RS-232C voltages).

2 5 EPROM Programmer

One of the more unique and powerful features of the BCC52x is

that it has the ability to execute and save programs in an EPROM.
The processor chip actually generates all of the timing signals
needed to program EPROMs. Saving programs in EPROMS is a much
more attractive and reliable alternative to cassette tape,
especially in control and/or noisy environments.
Port 1, bit 4 (IC5 p i n 5) i s used to provide a 1 or 50
millisecond programming pulse. The length of the programming
pulse is determined by whether we are programming INTEL brand
fast program EPROMs or generic brand EPROMS. The length of the
programming pulse is calculated from the assigned crystal value.
The accuracy of this pulse is within 10 CPU clock cycles. This
p i n is normally in a logical high (1) state. It is asserted l o w
(0) to program the EPROMs.

Port 1, bit 5 ( I C 5 pin 6 ) is used to enable the EPROM

programing voltage. This pin is normally in a logical high (1)
state. Prior to t h e EPROM programming o p e r a t i o n , this pin is
b r o u g h t to a logical low ( 0 ) state. T h i s pin is used to turn the
h i g h voltage, 21 volts (12.5 volts f o r CMOS EPROMS) required to
program the EPROMS on or o f f .
BCC52x does not save a single program on an EPROM (unless the
size of the program and the EPROM are the same). In f a c t , it can
save as many programs as the s i z e of the EPROM memory p e r m i t s .
The programs are stored sequentially in the EPROM and any program
can be retrieved and executed. T h i s sequential storing of pro-
grams is referred to as the EPROM FILE. T h e following commands
permit t h e user to generate and manipulate the EPROM FILE.
RAM (cr) and ROH [integer] (cr)

T h e s e two commands tell the BCC52x interpreter whether to

select the current program (the current program is the one that
will be displayed during a L i s t command and executed when Run is
typed) out of RAM or EPROM. The RAM address is assumed to be 512
(200H) and the EPROM address begins at 3 2 , 7 8 4 (8010H)

RAM

When RAM (cr) is entered, B C C 5 2 x selects t h e c u r r e n t program

from RAM Memory. T h i s is usually considered the BqnormalM mode of
operation and is the mode that most users interact with the
command interpreter.

Page 8
 When ROM [integer] (cr) is entered BCC52x selects the c u r r e n t
program o u t of EPROM memory. If no integer is typed a f t e r t h e ROM
command ( e ROM (cr)), BCC52C defaults to ROM 1 . Since the
programs are stored sequentially in EPROM the integer following
t h e ROM command selects which program the user wants to run or
l i s t . If you attempt to select a program that does not exist
( i . e . you type in ROM 8 and only 6 programs are stored in the
EPROM) the message Error: Prom Mode will be displayed. The error
is non-destructive and you can retype the correct command.
The BCC52x does not transfer the program from EPROM to RAM
when the ROM Mode is selected and you cannot EDIT a program in
ROM. Attempting to do so will result i n an error message.

Since the ROM command does not t r a n s f e r a program to RAM, it

is possible to have different programs in ROM and RAM
simultaneously. The user can vfflipmw back and forth between the two
modes at any time. Another added benefit of not transferring a
program to RAM is that a l l of the RAM m e m o r y can be used f o r
variable storage if t h e program is stored in EPROM. The System
Control Values - MTOP and FREE always refer to RAM not EPROM.
XFER (cr)
The XFER (transfer) command transfers the c u r r e n t selected
program in EPROM to RAM and then selects the RAM mode. After the
XFER command is executed, the user may edit the program in the
same manner any RAM program may be e d i t e d .
PROG (cr)

T h e PROG Command programs the r e s i d e n t EPROM w i t h t h e current

selected program. The current selected program may reside in
either RAM or EPROM. A f t e r PROG (cr) is typed, BCC52C displays
the number i n the EPROM F i l e t h e program w i l l occupy.
PROGl

Normally, after power is applied to the BCC52x device, the

user must type a mqspacet@ character to initialize the processor's
console port. As a convenience, BCC52x contains a PROGl command.
What t h i s command does is program the resident EPROM with the baud
r a t e information. So, t h e next time the BCC52x is "powered u p , "
i . e , reset, the c h i p will read this information and initialize
the serial port with t h e stored baud rate. The 4fsign-on'fmessage
will be sent to the console immediately after BASIC device
completes its reset sequence. The character no longer
needs to be typed.

The PROG2 command does everything the PROGl command does, but
instead of msigning-onu and entering the command mode, the BCC52x
immediately begins executing the first program stored in the
r e s i d e n t EPROM.

Page 9
 By using the PROG2 command it is possible to r u n a program
from a reset condition and never connect the BCC52x to a console.
Saving PROG2 information is equivalent to typing ROM 1 and RUN in
sequence. This is ideal f o r c o n t r o l applications, where it is not
always possible to have a terminal present. Also, this feature
permits the user to w r i t e a special initialization sequence in
BASIC or Assembly Language and generate a custom "sign-on1' message
for specific applications.

3.0 Powering up the Board

Power requirements f o r the BCC52 (standard) are as follows:

+ 5 Volts +/- 5% @ 350 ma

+ 12 Volts +/- 2 0 % @ 3 0 ma
- 12 Volts +/- 20% @ 10 ma
** + 2 1 V o l t s +/- 2 % @ 3 0 ma
*** + 12.5 Volts +/- 2 % @ 30 ma

Power requirements for the BCCS2f h 1-1 are as follows:

+ 5 Volts +/- 5% @ 230 ma
+ 12 V o l t s +/- 2 0 % @ 30 ma
- 12 Volts +/- 2 0 % @ 10 ma
++ + 21 Volts +/- 2 % @ 3 0 ma
++* + 12.5 Volts +/- 2 % @ 3 0 ma

Power requirements f o r t h e BCC52C are as follows:

+ 5 Volts +/- 5 % @ 100 ma

* + 12 Volts +/- 2 0 % @ 3 0 ma
- 12 V o l t s +/- 20% @ 10 ma
** + 2 1 V o l t s +/- 2% @ 3 0 m a
*** + 12.5 V o l t s +/- 2 % @ 30 ma

-- Required only for 88-232 operation

** -- Required only for 2764/27128 EPROM programming
**a -- Required only for 27C64/27C128 EPROM programming

CAUTION - The 21/12.5 v o l t programming power source

should o n l y be applied after the BCC52C is powered up and
should be disconnected before the BCC52C is powered down.

Page 10
A f t e r applying power, the BCCS2x:

lj Clears the internal processor memory

2) Initializes the internal registers and pointers
3 ) Tests, clears, and sizes the external memory

BASIC then assigns the top of external RAM to the System

Control Value (MTOP) and uses t h i s number a s t h e random number
seed. BASIC assigns the default crystal value, 11.0592 Mhz, to
the System Control Value (XTAL) and uses this default value to
calculate all t i m e dependent functions, such as the EPROM
programming timer and the interrupt driven Real Time Clock.
Finally, BASIC checks external memory location 8000H to see if
the baud rate information is stored. If the baud rate is stored,
BASIC initializes the baud rate generator ( t h e processor's Special
Function Register - T2CON) w i t h t h i s information and signs on.
If not, BASIC interrogates the s e r i a l port input and waits f o r a
space character to be typed (auto baud rate detection).
If you have entered nothing on t h e console device, B A S I C w i l l
sit t h e r e waiting and appear inoperative to the uninitiated.
Simply type a space and the console device should d i s p l a y the
following:
*MCS-51(tm) BASIC VX-X*
.READY

To see if the processor is operating correctly, type:

>PRfNT XTAL, TNOD, TCON, T2CON

(BASIC should respond with the c o n t r o l and s p e c i a l function values)

4.0 A Word About the BASIC

The BCC52x i s oriented toward p r o c e s s control and i s
significantly more powerful than a t i n y BASIC. S i n c e most of you
are familiar with BASIC, individual instructions such as DO WHILE
and FOR NEXT e t c . w i l l not be d e s c r i b e d here. A few of t h e
pertinent features which demonstrate the exceptional small package
performance of the BCC52x will be discussed.
MCS BASIC-52 contains a minimum level line editor. Once a
line is entered the user may n o t change t h e l i n e without re-typing
the line. However, it is possible to delete characters while a
line is in the process of being entered. This is done by e n t e r i n g
a Rubout or Delete character ( 7 F H ) . The Rubout character w i l l
c a u s e the l a s t character entered to be erased from t h e text input
buffer. Additionally, a control-D will cause the entire l i n e to be
erased.

Page 11
 4.1 Variables and Expressions
The range of numbers that can be represented in the BCC52x is:

There are eight digits of significance. Numbers are

internally rounded to fit this precision. Numbers may be entered
and displayed in four formats: integer, decimal, hexadecimal, and
exponential.
EXAMPLE: 129, 3 4 - 9 6 , OA6EHn 1 . 2 3 4 5 6 $+3
Integers are numbers t h a t range from 0 to 6 5 5 3 5 (or OFFFFH).
All integers can be entered in either decimal or hexadecimal
format. A Hexadeaimal number is indiaated by placing the character
lmHmBa f t e r the number (e.g. 170H). If the Hexadecimal number
begins with an alpha character ( 9 . g . A O O O H ) , a leading zero needs
t o be attached to distinguish the number from a variable name
(e.g. O A O O O H ) . When an operator, such as AND requires an integer,
BASIC will truncate t h e fraction portion of the number so it will
fit the integer format. All line numbers are integers.
A v a r i a b l e can be either a letter, ( i . e . A, X, I), a letter
followed by a number, ( i . e . Q1, T7, L3), a letter followed by a
One Dimensioned expression, ( i . e . J ( 4 ) , G ( A + 6 ) , I(lO*SIN(X))), or
a letter followed by a number followed by a One Dimensioned
expression (i .e. .
A 1 ( 8 ) , P7 (DBY ( 9 ) ) , W8 (A+B) variables t h a t
include a One Dimensioned e x p r e s s i o n are often referred to as
DIMENSIONED or ARRAYED v a r i a b l e s . Variables that only involve a
letter or a letter and a number are called SCALAR variables.

BASIC allocates variables in a " s t a t i c u tmanner. That means

each t i m e a variable is used, BASIC allocates 8 bytes specifically
f o r that variable. his memory cannot be de-allocated on a
variable by variable basis. That means if you execute a statement
l i k e Q=3, l a t e r on you cannot tell BASIC that the variable Q no
longer e x i s t s and "free upM the 8 bytes of memory that belong to
Q. The u s e r can clear t h e memory a l l o c a t e d to variables with a
CLEAR s t a t e m e n t .

Relative to a dimensioned variable, it takes BASIC a lot less

t i m e to f i n d a s c a l a r variable. That's because there i s no
expression to evaluate i n a scalar variable, If you want to make
a program run as fast as possible, use dimensioned variables only
when you must. U s e scalars for intermediate variables, then assign
t h e final r e s u l t to a dimensioned variable.

Page 12
 An expression is a logical mathematical expression that
involves Operators (both unary and dyadic), C o n s t a n t s , and
Variables. Expressions can be simple or quite complex, i . e .
12*EXP ( A ) / l o o , H (1)+55, or (SIN(A)* S I N ( A ) +COS ( A ) *COS (A) ) / 2 . A
"stand aloneM variable [var] or constant [const] is also consid-
ered an expression.

4.2 Real ~ i m eOperation after RUH

A f t e r RUN (cr) is typed a l l v a r i a b l e s are s e t e q u a l to zero,
all BASIC evoked interrupts are cleared and program execution
begins with the first line number of the selected program. The
RUN command and the GOT0 statement are the o n l y way t h e u s e r can
execute a program in t h e Command mode. Program execution may be
terminated at any time by typing a control-C on the console
device.

Unlike some BASIC interpreters that allow a l i n e number t o

f o l l o w t h e Run command ( i . e . , RUN loo), BASIC-52 does not permit
such a variation on the Run command. Execution always begins with
the first line number. To obtain the same functionality as
RUN[ln num], use GOT0 [In num] in the direct mode.
The CLOCKl statement enables the software real t i m e clock in
the BCC52x. The special function operator time is incremented
once every 5 milliseconds after the CLOCK1 statement has been
executed. The CLOCK1 statement uses timer/counter 0 in the 13-bit
mode to generate an interrupt once every 5 milliseconds. Because
of this, the special function operator TIME has a resolution of 5
milliseconds.
BASIC a u t o m a t i c a l l y c a l c u l a t e s t h e proper reload value f o r
timer/counter 0 after t h e c r y s t a l value has been assigned ( i . e . ,
XTAL=value. I f no crystal v a l u e i s assigned, MCS BASIC-52 assumes
a value 11.0592 MHz). The special function operator time counts
from 0 to 65535.995 seconds. After reaching a count of 65535.995
seconds time overflows back to a count of zero.
The interrupts associated with the CLOCKl s t a t e m e n t cause
BASIC programs to run at about 99.6% of normal speed. That means
t h a t the i n t e r r u p t handling for the real time c l o c k feature only
consumes about , 4 % of the t o t a l CPU t i m e . This is very small
interrupt overhead. The CLOCK0 (zero) statement disables or "turns
o f f n the real time clock feature.

The TIME statement is used to retrieve and/or assign a value

to the real time clock after t h e CLOCKl statement e n a b l e s i t . TIME
= 5 presets t h e real time clock to 5 seconds while ONTIME 30,100
causes the program to jump to line 100 when the real time clock
reaches 3 0 seconds.

Page 13
 Finally, PWM is an interesting statement that might be useful
to literally add bells and whistles to your next c o n t r o l
application. PWM stands for Pulse Width Modulation. What it does
is generate a user defined pulse sequence on IC1 p i n 3 .
T h e statement appears as PWM 50,50,100. The f i r s t expression
following PWM is the number of clock cycles the pulse will remain
high. A clock cycle is equal to 1.085 microseconds (11.0592 MHz
Xtal). T h e second expression is the number of clock cycles the
pulse will remain low and the third expression is the total number
of cycles the user wishes to output, All expressions in t h e PWM
statement must be valid integers ( i . e . between 0 and 65535
(OFFFFH) inclusive) and the minimum value f o r the first t w o
expressions is 2 0 .
These are only a f e w of the 103 commands, statements, and
operators in BASIC-52. The INTEL MCS BASIC-52 User's Manual
describes them in detail.

Page 14
5.0 Using the 82C55 Parallel Ports
Three parallel input/output ports are provided on t h e BCC52x
Computer/Controller Board with an 8255 ( 8 3 2 5 5 ) peripheral
interface adapter c h i p ( P I A ) . T h e 2 4 I / O bits and ground are
available on a 2 6 p i n Berg connector between the 8 2 5 5 (or 8 2 C 5 5 )
and the RS-232C connector.

The 8255(or 8 2 C 5 5 ) is a programmable interface device. The

2 4 1/0 lines are divided into three ports, A , B, and C , configured
either as input, output, or handshaking lines under software
control. A c o n t r o l register defines the characteristics of the
2 4 I / O bits. To t h e BCC52x, t h e three I / O ports and c o n t r o l
register appear as f o u r memory addresses as follows. These
addresses can be user s e t to select one of sixteen possible
locations.

JP2 J P 3
BASE OFFSET PORT A PORT 3 PORT C CONTROL REG.

OCOOOH 800H OC800H OC801H

II 900H OC900H OC901H
II
OAOOH OCAOOH OCAOlH
II
0800H OCBOOH OCBOlH
It OCOOH OCCOOH OCCOlH
ODOOH OCDOOH OCDOlH
OEOOH OCEOOH OCEOlH
OFOOH OCFOOH OCFOlH
OEOOOH 800H OE800H OE801H
It
900H OE900H OE901H
It
OAOOH OEAOOH OEAOlH
II
OBOOH OEBOOH OEBOlH
It OCOOH OECOOH OECOlH
ODOOH OEDOOH OEDOlH
OEOOH OEEOOH OEEOlH
OFOOH OEFOOH OEFOlH

Figure 5 . 0 - 1 Parallel Port Memory Address Poaeibilities

Page 15
 T h e example shows a Base Address of OEOOOH and an Offset
Address of 0800H selected g i v i n g a PORT A address of OE800H.
(OEOOOH + 800H = OE800H)

EOOO

Figure 5 . 0 - 2 Parallel Port Addressing Example

T h e 24 lines are divided into two groups of 12 lines, group A

(port A and the upper h a l f of port C) and group B (port B and the
lower half of port C ) . The functional configuration of each port
is controlled by the system software. In essence, t h e BCC52x
outputs a control word to the PIA which contains information such
as 'tmodeBq," b i t s e t t m , "bit reset", etc., that initializes the PIA
(the control register is a write only location and the control
word cannot be read by examining the contents of the control
register address) .
When the power to the expansion board is turned on, the PIA
is in an unknown configuration. Before the ports can be used they
must be initialized by loading a control word into the c o n t r o l
register address, For example, the BASIC statement
XBY(OE803H)=80H will load the value 80H into the control register.
The value 80H sets all three ports to mode 0 operation and output
( b i t 7 of the c o n t r o l register must always be set to logic I). At
this point, 8 bit values can be directed to the specific ports
w i t h the XBY(addr) command. Outputing 56 hex from port B is done
simply by XBY (OE801H)=56H.
T h e three ports can j u s t as e a s i l y be configured a l l as mode
0 inputs by loading 9BH a s the control word. The command is
XBY(OE803H) = 9 B H . Reading the value of i n p u t port A then
becomes PRINT XBY(OE800H). The following is a list of c o n t r o l
word values f o r some typical P I A p o r t configurations. To use any
of them, simply load the c o n t r o l register address with t h e X B Y
command.

Page 16
Control Word Value Port A Port B Port C

output output output

output output input
output input output
output input input
input input input
input input output
input output input
input output output

F i g u r e 5.0-3 8255/82C55 (IC2) Port Configuration

A complete specification of t h e 8255 ( 8 2 C 5 5 ) is n o t included

in this manual. Should you need to configure the P I A f o r some
more complicated 1/0 configuration or require the use of
handshaking refer to an 8 2 5 5 ( 8 2 C 5 5 ) DATA sheet by one of t h e
following manufacturers:

Intel Corporation
3065 B o w e r s Avenue
Santa Clara
California 95051

NEC Electronics U . S . A . Inc.

One Natick Executive Park
Natick
Massachusetts 01760

National Semiconductor Corporation

2900 Semiconductor Drive
Santa Clara
California 95051

Page 17
 6.0 Pinout8 of Connectors and Jumpers

Console Serial Connector

(DB-258 RB-232 Connactor -
Top V i e w )

No Connection --------> 1
14 <-------- No Connection
-------- >
Console I n p u t 2
0 15 <-------- No Connection
Console Output ------- >
0
3
0 16 <-------- No Connection
No Connection --------> 4
0

0 17 <-------- No Connection
Pull Up to + 12 Volts-> 5
0

0 18 <-------- No Connect i o n
Pull Up to + 12 Volts-> 6
0

0 19 <-------- No Connect ion

Ground --------------- > 7 0

0 20 <-------- No Connection
P u l l U p to + 12 V d c --> 8
0 21 < -------- No Connection
No Connection --------> 9 0

22 <-------- No Connection
No Connection ------- > 10
23 <-------- No connection
No Connection -------> 11
2 4 <-------- No Connection
No Connection -------> 12
0

25 <-------- No Connection
No Connection ------- > 13 - ,/

Page 18
 Serial Printer Connector
(2 X 10 Pin Berg Header -
Top View)

No connection -----> 1 1 4 <----- No Connection

AUX Serial Out ----> 2 15 <----- No Connection

No Connection -----> 3 16 <----- No Connection

No Connection -----> 4 17 <----- No Connection

Pull Up to +12 V d c > 5 18 <----- No Connection

No Connection -----> 6 19 <----- No Connection

Ground ------------ > 7 20 < P u l l Up to +12 Vdc

No Connection -----> 8 21 <----- No Connection

No Connection -----> 9 22 <----- No Connection

No Connection -----> 10 23 <----- No Connection

(2 Pin Right Angle Wolex Connector -

2 1 / 1 2 . 5 Volt Programming Voltage Input
End View)

Locking Tab >

Ground >

2 pin Holex R i g h t Angle Connector

Page 19
 (End View -
MM28 Bus Pin Configuration
Edge Card Connector)

Component S i d e n Solder S i d e
1 <------- +5 V o l t s

+ 12 Volts ---------> B 9P 2

3
<------- Ground
<------- NO connection

NO Connection ------> D 9P
T i m e r Zero Input ---> E
-
RD -----------------
Timer One Input ----> H
PSEN ---------------> 3

T i m e r Two Input ----> K

Timer Two Trigger --> L 4
TTL Serial Out ----->
TTL serial In ------>
W
N
C19 12 <------ Pulse Width Mod.

Int 0 - DMA R e q ----> P 13 <------ Interrupt 1

----

1
DMA Acknowledge 14 <------ Program Enable

Address 15 ---------> S 15 <------ Program Pulse

Address 14 --------->"T 16 <------ No Connection

Address 13 ---------> U 17 <------ No Connection

Address 12 ---------> V 9P 18 <------ NO connect i o n

Address 11 ---------> W 19 <------ No connect i o n

Address 10 ---------> X 9P

Page 20
 8255 Parallel P o r t Connector ( T O P V i e w )
( 2 X 13 P i n Berg Header)

Ground ----- > 1 2 <-------- Ground

PB3 -------- > 3 4 <-------- PB4

Page 2 1
 56

4 Pin Molex Power connector (Top View)

Locking Tab
- 12 Volts > Ground

+ 12 V o l t s 1L + 5 Volts

NOTE : Jumpers JPl -

J P 9 are shown as shipped by the factory.
They are s e t for 32K of contiguous RAM in I C 1 , 3, 8 , 12, and
8K EPROM in IC17.

IC17 EPROM Beleution Jumper

(1 X 3 Pin Berg Header -Top view)

<= Jumper shown selecting

2764 8K EPROM

Page 22
(1
8 2 5 5 Base
x 3 Pin Berg Header -
Address Selection
TOP View)

EOOO

<= Jumper shown selecting

Base Address C O O O

8 2 5 5 O f f s e t Address Selection
(2 X 8 p i n Berg Header - Top View)

Selection shown as O f f s e t 800

Base Address = COOO ( J P 2 )

Offset Address = 800 (JP3)
+
Actual Address = C800

Page 2 3
 IC12 Base Address Selection
(1 X 3 Pin Berg Header -
Top View)

Address s e l e c t i o n for IC12

shown f o r 6000H
4
IC1, IC3 and IC8 RAM/EPROM Enable
(1 X 3 Pin Berg Header -
Top View)

DATA Storage Area

or
PROGRAM Storage A r e a

S e l e c t i o n of Data or
<= Program Areas e n a b l i n g
IC1, I C 3 and IC8.

DATA Storage A r e a Only

IC12 RAM/EPROM Enable

(1 X 3 Pin Berg Header -
Top View)

PROGRAM Storage Only L10[7 Selection from J P 5

Selection of DATA or PROGRAM

Areas Enabling IC12
4

Page 2 4
 U17 RAM/EPROM ENABLE
(1 X 3 P i n Berg Header Top View)-

Selection of U17 for EPROM - n

EPROM JP7 RAM

DEVICE IN 017 AS =/A8 EPROM SELECTION

(1 X 3 Pin Berg Header Top View) -

AS EPROM JP8 AS RAM

Device in U17 used as EPROM

I -.- -* I
EPROMS can only be used as EPROMS.
RAMS can be used as either RAMS or EPROMS. When used as RAM,
the total contiguous RAM will be 40K i n s t e a d of
32K. When used as EPROM they will store programs
as if they were an EPROM with the MPROGl commands.
Remember to fill the RAM with OFFH or it will look
like a non-blank EPROM. Unless this RAM is a
battery backed-up RAM (smartwatch) the program will
be lost upon power down.

EMULATE 8031
(1 X 2 P i n Berg Header - Top V i e w )

Unj urnpered f o r
80C52 Operation

*a* NOTE *** BCC52C board is shipped WITHOUT JP9

installed. User may install this header f o r 8031
emulation. Jumpering will ground p i n 3 1 of US.
Refer to Intel's MICROCONTROLLER HANDBOOK for
8031 i n f o r m a t i o n .

Page 25
 7.0 Interfacing with other Micromint Boards

The BCC52x is completely bus compatible w i t h Micromint's BCC

series expansion boards, This section discusses some aspects of
interfacing these boards to the BCC52x by supplying a graphical
representation of a 64K address space along with the specific
board's address space requirements plus any supplemental notes.

7.1 MBO8 Eight 810t nother Board

The MB08 is used to bus together the BCC52x w i t h any of t h e

Micromint 2 8 bus compatible boards. The bus may be expanded with
a short cable (BCC42), which ties together JP1 from one MB08 t o
J P 2 of the second MB08. Power is jumpered between boards to
supply the second board power from t h e first. Alternately a
second supply can power the second MB08 if necessary.

The Eight Slot Mother Board Enclosure

The MB08 is designed to mate with a cardguide-cardcage
enclosure. The CCOl (10 i n c h cardcage) can accommodate one MB08,
while the CC02 (19 inch cardcage) will hold two MB08's.

Powering the Eight Slot Mother Board

T h e MB08 may be powered with Micromint's Universal (UPS11)
power supply. The UPS05 is a card style which will mount in t h e
cardcage w i t h the rest of the system. The UPS10 is a heavy duty
metal enclosed switching power supply.

Figure 7.1-1 Micromint Power Supply Bpecifications

Page 26
7.2 BCC52x COMPUTER / CONTROLLER

64K BCC52C
Address Space Address Space
OOOOH

lOOOH

2000H
OOOOH

lOOOH

-1FFFH-
2000H
F
1
<
1st RAM
8052 Processor must have 200H
bytes of RAM at 0000H.
C o n t r o l Stack uses from
OFEH down to 60H.
Argument Stack uses from
1FEH down to 12DH.

3000H 3000H

-3FFFH-
4000H 4000H

5000H

6000H
5000H

-5FFFH
6000~-
F 3rd RAM

7000B

8000H
7000H

-7FFFH-
800OH
F
2
4th RAM

9000H

AOOOH
9000H

-9FFFH-
AOOOH
F 2764
EPROM

OR
- 27128
EPROM

BOOOH BOOOH

-BFFFH-
COOOH

DOOOH

EOOOH
8255
FOOOH Parallel Port
Base Address + Offset Address
FFFFH

Port A Address
Port B Address
Port C Address
Mode Register Address

Page 2 7
7.3 BCCO8 SERIAL EXPANSION

64K
Address Space

OOOOH

1000H

2000H

3000H

4000H

5000H

6000H

7000H

8000H

9000H

AOOOH

BOOOH

COOOH BCC08
Address Space
DOOOH DOOOH
DFFFH-
EOOOH EOOOH
EFFFH-
FOOOH FOOOH

FFFFH FFFFH
4

BCC08's can add up to three additional, fully configurable,

UART/ 20ma s e r i a l p o r t s t o the BCC52C system. The user must
configure the system to prevent any address conflicts between
boards. Each BCC08 will require a full 1K block, addressable at
either ODOOOH, OEOOOH or OFOOOH.

Page 2 8
7.4 BCC13 ANALOG TO DIGXTAL COMRTER

64K
Address Space

OOOOH

lOOOH

Actual Address Space = 100H

2000H
Actual Address = Base + Offset + Channel #
3000H

BCC13 BCC13
4000H 16 Possible 8 Possible
Base Addresses O f f s e t Addresses

5000H

6000H

7000H

A0 0 OH-
8000H

9000H BOOOH

AOOOH
COOOH

BOOOH
plus -
COOOH
ElDOOOH-
D800H

DOOOH

EOOOH
El
EOOOH
~ 8 0 0 ~ -

FOOOH-

FOOOH
FFFFH
Address space requirements for the BCC13 is held to a low
100H bytes. The BCC13 is addressable f o r any 1 of 128 locations
between 8000H and OFFFFH. Each BCC13 has 8 - 8 bit channels,
providing 1000 conversions/channel/second. Additional BCC13's c a n
be added to expand the available number of channels.

Page 2 9
 7.5 BCCl8 DUAL SERIhL/MODEX PORT BOXRD

64K
T/O Spacc

OOOOH f / O Space Used per Board = 200H

lOOOH The BCC18 can be configured with

e i t h e r two 300/1200-bps m o d e m s , t w o
synchronous/asynchronous serial
2000H p o r t s , or one of each. Each serial
port can be used f o r either RS-232,
RS-422, or RS-485 communication.
3000H

4000H

5000H

6000H

7000H BCC18
8 Possible
Offset Addresses
8000H

9000H

AOOOH
BCC18
BOOOH 2 Possible
Base Addresses
COOOH

DOOOR

EOOOH
or -plus + QE

FOOOH

i FFFm

Page 3 0
7.6 8CC22 TERMITE SMART TERMINAL

64K
Address Space
OOOOH

lOOOH

2000H

3000H

4000H

5000H

6000H

7000H

8000H BCC22 Requires No Address Space

9000H

AOOOH

3000H

COOOH

DOOOH

EOOOH

FOOOH

FFFFH

The BCC22 does not require any room w i t h i n t h e BCC52Crs 64K

address space. The BCC22ls communication l i n e s are t i e d to the
BCC52C thru the mother board, so no cabling is necessary (RTS and
CTS must be t i e d together on the BCC22 f o r handshaking). S e t the
BCC22 to 9600 baud.

Page 3 1
7.7 ADPSOO PRE-RECORDED SPEECH BOARD

64K
Address Space

l-l
OOOOH

lOOOH Actual Address Space = 100H

Actual Address = Base + Offset

BCC2 3
4000H 8 Possible
O f f s e t Addresses

5000H

6000H

7000H

8000H

9000B

AOOOH
BCC2 3
1 Possible
BOOOH Base Addresses

COOOH

DOOOH

EOOOH

FOOOH

FFFFH 1
The address space requirement f o r the ADPSOO is lOOH bytes
The ADP500 is addressable at 1 of 8 locations between OFOOOH and
OF7FFH. ASCII commands written to the ADPSOO through BASIC or
machine language w i l l playback pre-recorded messages.

Page 3 2
 64K
Address Space
OOOOH

lOOOH Actual Address Space = 200H

lOOH for LCD + lOOH for Keyboard
2000H
Actual Address = Base + Offset
3000H

BCC25
4OOOH 8 Possible
Offset Addresses

5000H

6000H

7000H

8000H

9000H

AOOOH
BCC25
2 Possible
BOOOH Base Addresses
plus -
COOOH

DOOOH

EOOOH
FOOOH

FOOOH

FFFFH
The address space requirement f o r the BCC25 is 200H bytes
(100H for the output port and 100H for the input port). The BCC25
is addressable to 2 of 16 locations between OFOOOH and OFFFFH.
The BCC25 controls either a 4 x 2 0 or 8 x 40 character LCD and h a s
an input port f o r a parallel encoded keyboard.

Page 3 3
7.9 BCC30 ANALOG TO DIGITAL CONVERTER
64K
Address Space
OOOOH

lOOOH

Actual Address Space = 100H

2000H
Actual Address = Base + Offset + Channel #
3000H

BCCl3 BCC13
4000H 16 P o s s i b l e 8 possible
Base Addresses O f f s e t Addresses

5000H

6000H

7000H

AOOOH
8000H

9000H

AOOOH
COOOH

BOOOH
plus -
DOOOH-
COOOH

DOOOH EOOOH-

EOOOH
FOOOH-
F800H
FOOOH

FFFFH
Address space requirements for the BCC30 is held to a low
100H bytes. The BCC30 is addressable f o r any 1 of 128 locations
between 8000H and OFFFFH. Each BCC30 has 16 -
12 bit channels,
providing 1000 conversions/second with a resolution of 1.2mV.
Additional BCC30ts can be added to expand t h e available number of
channel s .
Page 3 4
7.10 BCC33 f/O HEHORY EXPANSION

64K BCC3 3
Address Space Address Space
OOOOH

1000H

BCC33 Addressed for

2000H O O O O H - Quadrant 1
12K/14K/16K RAM or EPROM

3000H

4000H
-J I <= 8255 P a r a l l e l Port

5000H

BCC33 Addressed for

6000H 4000H - Quadrant 2
12K/14K/16K RAM or EPROM
7000H
1 <= 8255 Parallel Port
8000H

9000H

BCC33 Addressed f o r
AOOOH AOOOH 8000H - Quadrant 3
12K/14K/16K RAM or EPROM

BOOOH 1 -BOOOH-
B800H -1
<= Opt. Cassette/Clock EPROM

-BFFFH- -I <= 8255 Parallel Port

COOOH COOOH

DOOOH

BCC33 Addressed f o r
EOOOH EOOOH OCOOOH - Quadrant 4
12K/14K/16K RAM or EPROM

FOOOH
F8OOH <= 8255 Parallel Port
FFFFH
The BCC33 can add 3 parallel ports and 14K of RAM/EPROM space
or 16K of RAM EPROM space to the BCC52C system. The user must
examine the address space available to find a non conflicting area
f o r the BCC33. Only the functions enabled on the BCC33 can
potentially cause address conflicts. This feature allows t h e
BCC53 to require only the amount of system address necessary to
access the enabled functions.
Page 3 5
7.11 BCC4OD C BCC4OR ISOLATED BIT 1/0

64K
Address Space

Actual Address Space = lOOH

BCC4 0D/R
8 Possible
O f f s e t Addresses

AOOOH
BCC40D/R
2 Possible
BOOOH B a s e Addresses
plus -
COOOH

I DOOOH I or

EOOOH =

1 FFFFH 1
The address space requirements f o r the BCC40D/R is h e l d to a
low 100H bytes. The BCC40D/R is addressable f o r any 1 of 16
locations between OC800H and OFFFFH. Each BCCQOR controls 8
relays and each BCCIOD controls 8 opto-isolated i n d u s t r y s t a n d a r d
1/0 modules.

Page 36
7.12 BCC53 I/O HEHORY EXPANSION

64K BCC53 BCC53

Address Space Data Address Space Code Address Space
- -
OOOOH OOOOH 8K RAM 8K EPROM OOOOH
-lFFH - Replaces Replaces -
lOOOH ZOOH- RAM of or BASIC in
BCC52C BCC52C
-1FFFH -1FFFH-
2000H ZOOOH- 8K RAM 8K EPROM 2000H
Replaces for -
RAM of or Utilities
3000H BCC52C user code

-3FFFH- 2
-3 F F F H -
4000H 4000H 8K RAM 8K EPROM 4000H
Replaces for Jump
RAM of or Vectors -
5000H BCC52C user Code

-SFFFH- -SFFFH-
6000H 6000H 8K RAM 8K EPROM 6000H

7000H

8000H
-7FFFH-
8000H
F
A
Replaces
RAM of
BCC52C

8K RAM
for
or U t i l i t i e s
user Code

8K EPROM
-

L
-7FFFH
8000~-

9000H

AOOOH
-9FFFH-
AOOOH
F Replaces
EPROM
in Z I F
socket

8K RAM
or user Code

or 8K EPROM
-9FFFH
AOOOH-

BOOOH
user Code
-BFFFH- -BFFFH
COOOH COOOH COOOH-
C8 00H
CFOOH
DOOOH

DFFFH DFFFH
EOOOH EOOOH- EOOOH-

FOOOH
E800H
EFOOh :;zzIL~
f or EPROM
8K

FFFFH FFFFH FFFFH

The BCC53 can add 6 parallel ports and 48-64K of RAM/EPROM

space to the BCCS2C system. The user must examine the address
space and s e t up non-conflicting areas f o r the RAM/EPROM on t h e
BCC53. Only the functions enabled on the BCC53 can potentially
cause address conflicts. This feature allows the BCC53 to require
o n l y the amount of system address space necessary to access t h e
enabled fu n t i o n s .
Page 3 7
7.13 BCC55 PROTO (TYPING)

64K
Address Space

OOOOH

1000H

2000H

3000H

BCC55 BCC5 5
4000H 8 Possible 8Possible
Base Addresses Offset Addresses
5000H

6000H

7000H

8000H

9000H

AOOOH

BOOOH

COOOH

DOOOH

EOOOH

FOOOH

The BCC55 provides the user with a way of building custom

boards without the worry of buffering and address decoding. 8
BASE address locations along w i t h 8 OFFSET a d d r e s s locations are
decoded on the board. Note the BCC55 as shipped t a k e s 800H bytes,
t h e user may d i s a b l e 7 of the 8 c h i p selects to limit the board's
requirements to l O O H bytes.
Page 3 8
8.0 Optional Utilities EPROM (ROM A&B V1.l, ROM A&B V1.1C)

Micromint a l s o has available t h e optional MCS BASIC-52

expansion package (ROM ALB) for the BCC52x. T h i s 8K expansion ROM
plugs right into the BCC52x to provide many u s e f u l o p t i o n s and
follows much the same syntax as t h e standard MCS BASIC-52 commands
and statements. Two versions of ROM A t B are available; ROM AhB
V1.1 for boards MOT using the CMOS processor and ROM ALB V1.1C f o r
boards that ARE using the CMOS version of the processor.
As shipped from t h e factory, the BCCS2x enables DATA and
PROGRAM memory within the same address space. The optional
Utilities EPROM is addressed at 2000R. T h i s address c o r r e s p o n d s
to I C 3 . When the EPROM is placed in IC3 the contiguous RAM is
only that in ICl. If about 8K of RAM is sufficient, then this is
the easiest configuration to use; simply install one 8K b y t e RAM
into IC1. Refer to section 6 . 0 for t h e proper configuration of
JP4 -JP6 as shipped from t h e factory.

Alternately, if more contiguous RAM is needed, I C 1 , I C 3 , and

IC8 can be configured to respond only to requests to the DATA
memory area w i t h JP5 (RAM-only selection). IC12 can be configured
to respond only to requests to the PROGRAM memory with JP6 (FROG-
only s e l e c t i o n ) . This scheme w i l l g i v e 24K of contiguous RAM.
Insert 8K RAMS into I C 1 , I C 3 , and I C 8 and s e t the jumpers as shown
in Figure 8.0-1. (NOTE: To eliminate p o s s i b l e address conflicts,
be sure to understand t h e use of separated DATA and PROGRAM areas
before changing any jumpers. Use the Intel Microcontroller
Handbook as a reference.)

Features of the utilities ROM-ALB include:

ARMS - a single line assembler which supports backward referenced

labels, the EQU operator, the $ operator, addition and
subtraction operators, and standard Intel mnemonics.
CHANGE - used to display and/or modify the contents of individual
external memory l o c a t i o n s .
DIS - displays a region of external memory in hexadecimal and
ASCII.

EDIT - used to edit a specific line in a BASIC text file.

HEXL - the HEX Load command is used to load an INTEL
standard HEX format f i l e from the console device into
memory.
HEX8 - the HEX Save command outputs a standard INTEL HEX
f i l e to the console device from memory.

REHUn - renumbers the lines in a BASIC t e x t f i l e .

Page 3 9
 COMMANDS cont.
BLAST - is used to program an EPROM with the contents of a
specified block of memory. May select between t h e normal
programing algorithm or the 1NTELigent programming
algorithm.
MOV - used to move blocks of memory from one location to
another.
FILL - fills a block of memory w i t h a specified byte of d a t a .
VERIFY - does a byte for byte comparison of a l l data stored in two
blocks of memory.
ASH - invokes a resident two-pass assembler that p e r m i t s both
forward and backward referenced labels.
TEDIT - invokes a text editor which allows the creation of new t e x t
f i l e s or the e d i t i n g of t e x t files saved to EPROM.

Page 4 0
 IC12 Base Address election
(1 X 3 Pin Berg Header Top View) -

Address selection f o r ICl2

shown for 2000H
n
JPS

I C 1 , I C 3 and I C 8 RAld/EPROM Enable

(1 X 3 Pin Berg Header -
Top V i e w )
DATA Storage Area
or
PROGRAM Storage A r e a

<= Selection of Data Area

enabling I C 1 , I C 3 , Ic8

DATA Storage Area Only

IC12 RAM/EPROI Enable

(1 X 3 Pin Berg Header - Top View)

PROGRAM Storage Only 1 1 1 Selection from J P 5

Selection of DATA
Areas Enabling IC12

Figure 8.0-1 Jumper settings for 24K RAM h Utilities ROM

Page 4 1
 BCCS2 (standard) PARTS LIST
Designation Description
IC' 8
IC1 6264 RAM 8K x 8
IC2 74LS373 Octal Latch
I C 3 , I C 8 , IC1 6264 RAM 8K x 8 (optional)
IC4, I C 9 74LS245 Octal Transceiver
ICS 8052AH-BASIC ( o p t . 80C52) Microcontroller
IC6 MC1489 RS2 3 2 Rcvr
IC7 MCl488 RS232 Xmtr
IClO 74LS04 (use 74HCT14 w/80C52)Hex Inverter
ICll DM7407 Hex Buffer
IC13,IC14 74LS138 3-to-8 Decoder
IC15 74LS08 Quad 2 Input AND
ICl6 8255 PIA
IC17 2764/27128 EPROM (Optional)

47K (yel-vio-org)
10K (brn-blk-org)
1K (bm-blk-red)
4.7K ( yel-vio-red)
4.7K S I P (9 Element)
CAPACITORS

.1 MFD Ceramic, 25V

10 MFD Electrolytic, 25V
2 7 PFD Ceramic, 25V

PCB BCC52 Printed C i r c u i t Board

PB1 PANASONIC Pushbutton EVQPlR04K
XTALl 11.0592 MHZ Xtal MTRON MP-1
Q1 PN2907 Transistor
CR2 1N270 Diode
CR1 IN4148 Diode
JP1,2, JP4-JP8 1x3 Berg-type Header
JP3 2x8 Berg-type Header
J1 DB-25-S RS-232 Connector H2R25RA28A2
J2 2x10 Berg-type Header
J3 2 P i n Right Angle Male Molex Connector
J5 2x13 Berg-type Header
J6 4 Pin Molex Male Connector
SJ1-SJ8 Shorting Jumpers
SOCKETS

28 pin socket
20 pin socket
40 pin socket
14 p i n socket
16 pin socket
2 8 pin ZIF socket

Page 4 2
Designation

IC1 6264 PI-15 RAM 8K x 8

IC2 74HCTLS373 Octal Latch
I C 3 , IC8, IC12 6264 P I - 1 5 8K x 8 (Optional)
IC4,IC9 74HCTLS24 5 Octal Transceiver
fC5 8 052AH-BASIC Microcontroller
IC6 MC1489 RS232 Rcvr
IC7 MC1488 RS232 X m t r
IClO 74HCTLS04 Hex I n v e r t e r
ICll DM7407 Hex Buffer
IC13, IC14 7 4HCTLS 138 3-to-8 Decoder
IC15 74HCTLS08 Quad 2 Input AND
IC16 8255 PIA
IC17 2764/27128 EPROM (Optional)
RESISTORS
47K (yel-vio-org)
1OK (bm-blk-org )
1K (bm-blk-red)
4.7K (yel-vio-red)
4.7K S I P ( 9 Element)

CAPACITORS
- 1 MFD Ceramic, 25V
10 MFD Electrolytic, 25V
27 PFD Ceramic, 25V

PCB BCC52 Printed Circuit Board

PB1 PANASONIC Pushbutton EVQPlROIK
XTALl 11.0592 MHZ Xtal MTRON MP-1
Ql PN2907 Transistor
CR2 1N270 Diode
CR1 1H4148 Diode
JP1,2,J P 4 - J P 8 1x3 Berg-type Header
JP3 2x8 Berg-type Header
J1 DB-25-S RS-232 Connector H2R25RA28A2
52 2x10 Berg-type Header
J3 2 Pin Right Angle Male Molex Connector
J5 2x13 Berg-type Header
J6 4 P i n Molex Male Connector
SJ1-SJ8 Shorting Jumpers
SOCKETS

28 pin socket
20 pin socket
40 pin socket
14 pin socket
16 pin socket
28 p i n Z I F socket

Page 4 3
 BCC52C PARTS LIST

Designation Description

5564 CMOS RAM 8K x 8

74HCT373 Octal Latch
5564 CMOS RAM 8K x 8 (Optional)
74HCT245 Octal Transceiver
80C52 CMOS pcontroller
MC14C89 RS232 Rcvr
MC14C88 RS232 X m t r
74HCT14 Hex Inverter
7407 H e x Buffer
74HCT138 3-to-8 Decoder
74HCT08 Quad 2 Input AND
82C55 PIA
27C64/27C128 EPROM {Optional)
RESISTORS
47K ( yel-vio-org)
10K (bm-blk-org)
1K (brn-blk-red)
4.7K (yel-vio-red)
lox S I P (9 Element)
CAPACITORS

- 1 MFD C e r a m i c , 25V
10 MFD Electrolytic, 25V
27 PFD Ceramic, 25V

PCB BCC52 P r i n t e d C i r c u i t Board

PB1 PANASONIC Pushbutton EVQPlROQK
XTALl 11.0592 MHZ Xtal MTRON MP-1
Q1 PN2907 Transistor
CR2 IN270 Diode
CR1 IN4148 Diode
JP1,2, JP4-JP8 1x3 Berg-type Header
JP3 2x8 Berg-type Header
J1 DB-25-S RS-232 Connector H2R25RA28A2
J2 2x10 Berg-type Header
J3 2 Pin Right Angle Male Molex Connector
J5 2x13 Berg-type Header
J6 4 Pin Molex Male Connector
SJ1-SJ8 Shorting Jumpers
SOCKETS

28 pin socket
20 pin socket
40 pin socket
14 pin socket
16 p i n socket
28 pin ZIF socket

Page 4 4
10.0 BCC52x SILKSCREEN

The silkscreen is the same for each version of t h e BCC52x.

-f
uRESET
I
0

-W
E

@ YICROMIHT INC. 1985

UIS Ut4 Z71t0

*a
I0 N

B
8

uz
0
MMZBBUS J4
z

Page 45
 Theschematic shown here (BCCSZC) is identical f o r all three
versions of t h e BCC52x. The b a s i c difference is t h e type of I C s
used on each version ( i . e . NMOS/CMOS)

P I W
I n I a

Page 4 6
 T h e schematic shown here (BCC52C) is identical f o r a l l three
versions of the BCC52x. The b a s i c difference is the type of I C s
used on each version ( i . e . NMOS/CMOS)

m u
I W
I r)
I
Page 4 6