Solder Mask

What is a solder mask and what is its role?

A solder mask is a polymer coating used to mask or protect the untinned copper tracks from oxidation and abrasive
damage. It also prevents solder bridges between tacks during soldering. esp wave soldering or reflow soldering. It
provides an environmental protection to the track, provides insulationand protects against dirt, fingerprints, etc.
Figure shows the solder mask and solder mask well.

The solder mask performsthese functions

• Reduce solder bridging and solder shorts
• Reduce the consumption of solder during wave soldering thereby reducing the weight and cost
• Provides environmental protection to the tracks, esp from moisture ingress
• Provides insulation between adjacent tracks which are closely placed
• Prevent the PCB from getting damaged by dirt, fingerprints etc
• Keeps the solder pot free from contamination during wave soldering

Solder mask and solder mask swell

The PCB solder mask (resist) material used is in the nature of somea liquid photo-polymer. Iit uses epoxy or epoxy-
acrylate resin technology and the whole board is coated with the material.

Once a sloder mask applied, openings are made in the solder mask, in selective areas where components need to
be exposed to solder (solder unmask), This is accomplished using photolithography technique. Solder mask is
traditionally green but is now available in many colors.

Solder resist classification

The solder resist are basically classified into two categories:

 • Temporary solder resists
• Permanent solder resists

Figure shows the various types of temporary and permanent solder masks. The permanent masks are applied either
by the screen printing method or photo-printing method. The screen printingis further classified as thermal curable or
ultraviolet curable. The photo printing masks use either the liquid film solder mask or dry film solder mask. The
temporary solder masks are classified on the basis of the chemistry used for developing the resist.
Solder resist

Permanent Temporary

Screen Printing Photo Printing Solvent Aqueous Peelable

Thermal Ultra Liquid Dry

Violet

Solder resist application methods

Temporary Resists
These resists are used temporarily. Scenarios are
The solder should not get into some holes and fill up thereby preventing insertion of some components later
on
Gold plated fingers in the PCB should not be wetted by solder. These goldplated fingers may be inserted
into edge connectors later on

Permanent Resist
These resists are applied permanently on the PCB. They become an integral part of the PCB. Demand for solder
mask is increasing every dya due to wide spreas usage of SMD components with very small footprints and also due
to compactness of PCBs with very closely spaced PCB tracks. Solder masking brings down inspection and rework
costs and improves reliability.

Solder Mask Application

The solder mask or solder resist are applied either by screen printing or photo printing method. Figure shows the
types of solder resist applications.

Application methods
 Screen Printing Photo Printing

Thermal curing Ultraviolet curing Liquid film Dry film

methodmethod

Solder resist application methods

The solder mask should have a clearance of at least 0.25 mm around the solder pad for components. This is shown
in Figure.

Solder mask minimum dimension overlap for a leaded component land

Reliability of Solder Mask

The reliability of the solder mask is dependent upon how well the coating has been applied and how much
encapsulation is achieved. A minimum of 50microns thickness is essential to protectagainst mechanical/handling
damages.The material used for solder mask must have sufficient insulation properties, at least with a dielectric
strength of 1000 volts.In case of liquid solder mask coated boards, the thickness will be less than 50microns. Hence,
these boards will have more pin holes and skips and poor insulation, when compared to the dry film solder masked
board.

Soldering and Cleaning

Different solder mask systems have their own cleaning systems. The degree of cleanliness on and around the pad
will affect the flow of flux which, in turn, controls the degree of wetting of the pad area and eventually the solder joint
itself.

Tenting of Vias (PTH)

With SMD technology, the vias tend to become smaller and smaller in size. When liquid mask is used, there is no
possibility of reliably shielding the hole against liquid mask entering vias. The liquid maks will enter the vias. Once
entered, it is also difficult to dissolve these coatings. Therefore, the reliable solder filling of the holes is not possible.
Liquid solder mask is therefore to be avoided when vias in SMD boards are used. A dry film solder mask on the other
hand, can tent the vias through photo-imaging, even with a 50 micron film with thick durable protective coating, as
illustrated in Figure

Figure 4.3 Cross-section of tenting vias

https://www.quora.com/What-is-a-netlist-in-PCB

Netlist
What is a network?
A network is a collection of two or more interconnected components. A net is a conductor that interconnects two or
more component terminals
What is a netlist?
In PCB design, a netlist is a comprehensive description of the connections in an electronic circuit. Therefore, a netlist
will be a complete list of the electronic components in a circuit and a list of the nodes these components are
connected to.
The netlist contains the electrical connections between the components on the circuit board, and is usually held in
textual format (Electronic Design Interchange Format). Netlist file is a document file which contains information about
the logical interconnections between signals and pins. A Netlist file consists of nets, pins, components, connectors,
junctions, no-connection symbols, and power and ground symbols

A netlist is set of connections that describe the circuit.

Example 1: For example if pin A of Resistor R5 is connected to Pin No B of inductor L2 and Pin 1 of capacitor C8,
and this connection is also connected to pin no 3 of IC 18 then net 1 is R5[A].L2[B]. C8[1].IC18[3].Like this all
connections are generated from the circuit and become part of the PCB artwork design.
Example 2
Description of the circuit :
X1 and Y1 are the inputs to a NAND gate U1.
X2 and Y2 are the inputs to AND gate U2.
Z1 and Z2 are the inputs to an NOR gate U3.

The Netlist file of the design will be :

NOR(T, Z1, Z2)
NAND G1 (Z1, X1, Y1)
AND G2 (Z2, X2, Y2)
G1 is an instance of NAND gate and G2 is the two instance of the AND gate. Each time a part is used in a netlist, this
is called an "instance".It is evident that all the gates in the circuit are in the netlist file. The bracket following each
instance contains the outputs and the inputs.(output written first). Every CAD tool (multisim for example)will have
library, consisting of gates, comonents, ICs etc. Example: In multisimwe can select an AND gate, OR gate, NOT
gate, etc anduse it in our circuits.Each time we select a particular gate for the PCB design will be an instance. Hence
instances are the copies of something which has been already defined.Thus netlist defines all the physical
connections in the design.

The netlist file is an ASCII text file. The filename should include the ".net" extension. The netlist is written in a single
file, but includes four sections:
1) A file header
2) A table listing each of the components
3) A table listing each of the net names
4) A table listing each of the net connections.
Every table entry is written using a single line of text that ends with a CRLF.

Gerber
What is Gerber?
Gerber data is a simple, generic means of transferring printed circuit board information to a wide variety of devices
that convert the electronic PCB data to artwork produced by a photoplotter.
Virtually every PCB CAD system generates Gerber data because all photoplotters read it.
It is a software structure consisting of X,Y coordinates supplemented by commands that define where the PCB image
starts, what shape it will take, and where it ends.
In addition to the coordinates, Gerber data contains aperture information, which defines the shapes and sizes of
lines, holes, and other features.
What is Gerber and what is its role?
It is a file format used by PCB industry software to describe the images of a PCB (copper layers, solder mask,
legend, etc.) as well as the drilling and milling data.
The gerber PCB data gets converted to artwork thro a photo plotter.
The gerbers need to be standardised universally and standards are available. RS-274X (extended Gerber format)
and the obsolete RS-274-D
In addition to the coordinates, Gerber data also contains aperture information, to define the shapes and sizes of
lines, holes, and other features.
Gerber is a data file.
Gerber is a, generic means of transferring PCB information to a wide variety of devices (PCs, Plotters, Printers
etc)
Gerber is a software structure.
Mainly contains X,Y coordinates
Gerber contains commands that define
– where the PCB image starts
– where it ends
– what shape it will take, and

Standard Gerber Files

GBL – Gerber Bottom Layer
GTL – Gerber Top Layer
GBS – Gerber Bottom Solder Resist
GTS – Gerber Top Solder Resist
GBO – Gerber Bottom Overlay
GTO – Gerber Top Overlay
GBP – Gerber Bottom Paste
GTP – Gerber Top Paste
GKO – Gerber Keep-Out Layer
GM1 – Gerber Mechanical 1
GM2 – Gerber Mechanical 2
GPT – Gerber Top Pad Master
GPB – Gerber Bottom Pad Master
Gerber is used in PCB fabrication data for manufacturing industry primarily.. It is in ASCII format. Gerber has several
flavours that describes the printed circuit board images: copper layers, solder mask, legend, drill data, etc. PCBs are
designed on CAD software. This data typically contains a Gerber file for each image layer (copper layers, solder
mask, legend or silk) as shown in the figures. For assembly, the gerber files contain the solder paste layers and the
central locations of components to create the stencil and place and bond the components.
The standard file extension is .GBR or .gbr though other extensions are also used.

Electromagnetic Interference /
Compatibility (EMI/EMC)
Today’s PCB engineers need to deal with new materials and new components, high speed circuitry, high packing
density, shrinking track widths and shrinking track spacings and so on……...All these aspects give rise to higher
levels of EMC (electromagnetic compatibility) and EMI (electromagnetic interference) problems.
Electromagnetic compatibility (EMC) and related electromagnetic interference (EMI) are two major culprits, design
engineers have to pay close attention.. This results in a huge set of rules to be followed in PCB layout and design.
What is EMC?
EMC is all about generation, propagation, and reception of undesirable electro-magnetic energy.
What is EMI?
EMI is all about unwanted, damaging effects EMC or the undesirable energy EMC generates.
High speed digital circuits are potential sources of electromagnetic radiation. The level of emissions from a PCB is
proportional to the clock rates used by the circuit, switching speeds with fast rise/fall times, length of the tracks that
carry clock and high speed switching signals and poor grounding/shielding techniques. At high frequencies, tracks on
a PCB act as mono-pole or loop antennas. When the track length approaches one-seventh of the wavelength, the
antenna effect becomes more pronounced and radiation starts taking place. (EMI).
In high speed designs the characteristic impedance shd be close to 50 ohms. (maybe 50 to 70 ohms). Lower
impedance values will induce excessive di/dtcross-talk and consequently power consumption will double and create
heat dissipation problems.
An important concept in PCB design for EMI compliance is, the loop area concept. Interference can both exit and
enter the PCB into areas inside the loops. The smaller the dimensions of each loop, the smaller will be the magnitude
of interference to be dealt with. The circuitry on the board may be contained inside several small loops, through a
gridded power supply distribution. This concept is called Ground-plane grids The best design will devote one or two
exclusive planes or sheets of copper, as power plane and ground plane. A four-layer circuit board, with the two
centre layers being power and ground, is often used to minimize EMI emissions and susceptibility. When using
double-sided PCBs, without the opportunity for ground planes, special attention must be paid to the loop area (Grids).
High frequency circuits, such as crystals, should be having an overall ground in that area. If there is an opportunity to
earth the metal case of such devices, it is usually worthwhile to do so.
Signal traces can be sandwiched between the ground and power planes. This provides a shield which reduces both
radiation and susceptibility to radiation. It also provides ESD protection. It is a good practice to route high speed, fast
rise time signals between those planes to eliminate radiation.
The high speed clock circuits must be located at the centre of the PCB. The clock traces should be short in length.
Longer traces will act like antennae, radiating RF energy.

High Frequency Circuits Design

Main problems in high freq applications are
a. Cross talk
b. Gnd and supply corruptions
c. EMI
d. EMC

The digital circuits that work on signal frequency above 300 MHz and analog circuits above 100MHz are generally
referred as a high frequency signal. At these frequencies, even short pieces of conductors on a PCB act as
transmission lines.
Nature of Trace Impedance
How \ is it that a trace has an AC impedance?
Every trace has series inductance. The inductance(L) value is proportional to the length of the trace and is inversely
related to the cross-sectional area of the trace. This L offers impedance and it is significant.
Every trace has a shunt capacitance (C) between this trace and its signal return trace (path) wherever that return
path trace is.. Therefore this C is distributedthrough out the pcb and is related to the width (or diameter) of the trace
and also to the dielectric of the PCB material used.. This C is obviously inversely related to the distance to the return
path. Therefore, impedance offered is large as the frequency of the signal increase or the switching speed increase.
Thus, we see that every trace looks like a distributed LC circuit to the source which is driving it. The (AC) impedance
of the trace is due to this distributed LC
This AC impedance is “uncontrolled.” We need to carefully design the pcb traces..
The traces should look like a transmission line which can be terminated it in its characteristic impedance to avoid
reflections. If we do this we have designed a “controlled impedance” trace or a “controlled impedance” transmission
line. Reflections go down as we approach characteristic impedance and consequently EMI/EMC issues go away
Controlled Impedance
“Controlled impedance” meas that the impedance should be constant all along the trace. The best way to do this will
be to control its geometry. and its environment. There are three primary (and one secondary) aspects to the overall
geometry that must be controlled:
1. The width of the trace
2. The spacing between the signal trace and the signal return path (This is one reason why we use planes, it
makes control over this spacing much easier.)
3. The relative dielectric coefficient of the material that surrounds the trace, and
4. The thickness of the trace.
Coaxial cables are excellent examples of controlled impedance transmission lines where these variables are tightly
controlled by consruction. The center wire is at constant distance from the return path for hundreds of kilometres..
The old Twin lead” cables are also good examples of controlled impedance transmission lines.

A printed circuit board is considered as a transmission line if its length ‘L’ (in meters) is:

3Mhz
L= ; Where f = highest frequency in the signal in MHz
f

Such a transmission line has certain impedance, called the ‘Wave Impedance’. A broad conductor has smaller wave
impedance than a narrow conductor. Similarly, a conductor which is near the ground plane will have smaller wave
impedance than the one which is far away.
In a transmission line, if the wave impedance is not matched with the source and/or load impedance (Characteristic
Impedance Z0), reflections do take place. Reflections are harmful as they cause attenuation, loss of bandwidth and
slowing down of switching speeds.
The rise-time increase due to a mismatched line will be a multiple of its transmission delay of approximately 5–10
nsec/m. As a rough estimate, it can be taken as “10 to100 nsec/m” or “0.1 to 1.0 nsec/cm”
If RS, RL<< ZO, the line behaves as an inductor, and if RS, RL>> ZO, the line behaves as a capacitor.
Where
RS = Source impedance
RL = Load impedance
ZO = Wave impedance of the transmission line.
𝟏 𝟏 𝟏 𝟏
Remember 𝐙 ∝ 𝐰 ∝ 𝐭 ∝ 𝐡 ∝
√𝐄𝐫
.
The ground and power supply lines also play an important role in high frequency applications. This is because the
current drawn from the power supply line is fed back into the ground, where it appears as high frequency
components, such as current spikes, ringing (damped oscillations) etc. Therefore, the dc potential of the power
supply does not remain constant, leading to a significant deterioration in the behaviour of the circuit. Therefore, as a
ground rule, power supply lines must be kept as short as possible.
The following guidelines are useful for high frequency circuit PCB design:
• Use a ground plane or very large ground surface for ground conductors
• Use broad power supply conductors (Traces or even wires)
• Ground and power supply lines should run close to each other and they should be parallel
• Provide a de-coupling capacitor between the ground and the power supply. The conductor length for a fast
pulse system should be short as skin effect and dielectric losses increase in proportion to the length
• For large-sized PCBs, dielectric losses play an important role. In such cases, use PCB with suitable high
frequency quality material
• Decide which parasitic elements (capacitive and inductive) are more harmful and design the conductor
layout accordingly
• Keep all lines which are not matched very short, otherwise the rise-time increase could be as high as 1
nsec/cm
• Provide ground lines (grounded or connected via a capacitor to the ground) when even a parasitic
capacitance is likely to have a deteriorating effect

Microstrip:
What is Micro Strip? Where it is used?
• It is a strip of transmission line, usually a trace in PCBs.
• It is a thin film strip in contact with a flat substrate (FR4) on one side with a similar thin film ground plane
conductor on the other side of the substrate.
• Hot conductor on top and return conductor (plane) at the bottom.
• Finds application in the microwave region, Antennas, filters etc.
• Inexpensive.
• Cannot handle high power.
• Losses are high.
• In microwave applications FR4 suffers heavy losses and therefore alumina (Al2O3) substrates are used.
• Micro strips should not have sharp 900 bends (Reflections) can have gradual bends.

• Example Velocity of microwave = 3x 108 m/sec

At 10GH2 wave length =3cm
Effective dielectric strength of a substrate = 7
Therefore, Actual Wave velocity in this substrate = 3cm/√7 = 1.13 cm
Micro stirp Stub matching = 1.13/2 = 5.6 mm
Therefore, Length of the µ strip truck in the pcb = 5.6 mm

EMI /EMC reduction:

Ground: Ground plane design is the most important part of reducing EMI/EMC. Increase the PCB’s ground area as
much as possible in the PCB. All vacant area should be filled with ground plane (Copper). This large ground plane
will reduce unwanted RF emissions, crosstalk, and noise. All relevant components should be connected to a ground
point or plane.

EMC Reduction: Large Ground plane reduces the impedance levels which plays a big role in minimizing EMC.

Ground planes – (a) Bottom view (b) top view (c) ground grid plane
To reduce EMC problems in a multi-layer PCB, use a solid ground plane or ground plane grids as shown above.

Criss Cross grids :

In Double Sided PCBs it may be a good idea to run gnd on either side. Length wise on the PCB top side and &
Width wise in the PCB bottom side.
The track length of signal forward from the source and signal returns to ground should be of equal length. Imbalances
will induce, “antenna-like” radiations and cause EMI. If source and return path aren’t about equal in length, ground
bounce, another form of EMI problem occurs. Also, the track lengths should become shorter and shortes as the
signal frequency or switching speed increases.

Quarantine EMI prone circuits:

A good EMI/EMC design should separate out analog and digital circuitry separately and make them separate islands
with their individual ground planes. They can be referred to as Analog ground and Digital grounds in the circuit
diagrams.
Analog circuits are inherently high current circuits and digital circuits are high switching speed circuits. High current
traces should be kept away from high-speed traces or switching signals. These grounds should eventually meet only
at the filter capacitor of the Power supply. It is a good idea to decouple power supply traces at many places (strategic
nodes) all over the PCB. LC decoupling or RC decoupling will be a good idea. RF chokes can be used in all PCB
supply tracks at every strategic node of the circuit. When the speeds are high each IC should have its own RF
ceramic capacitor. (0.01 to 0.1μF) right across its supply and ground pins, physically very close to the IC.

Tracks carrying high-speed signals and clocks should be short in length as already mentioned. These tracks should
also be adjacent to the ground plane to minimise crosstalk, noise, and radiation levels. On the other hand tracks of
these digital signals should also be kept away from the power plane. If they’re close to it they can create spike noise
or induction, which will spread through the entire PCB like a virus and increase EMI problems.
 w
General Thumb Rules on track width to board thickness ratios for avoiding reflections ( )
b
w
• Power supply tracks: ≥5
b
w
• Signal tracks : b
= 0.4

Beware of crosstalk.
What is cross talk?
• Un wanted signal interfering with desired signal is a cross talk.
How does it happen?
• If two tracks run parallel to each other for a certain length, one track induces spikes on the other [TTL – 20
cm, ECL – 10 cm, CMOS – 50 mm]
• Closer the track spacing, higher will be the cross talk.
• Conformal coating and solder mask Insulation between tracks, reduce cross talk.
• Higher the frequency, more will be the cross talk.
• Matching closer to Z0 will reduce cross talk.
• A ground track (shielding) between two tracks help (electro static shielding).
Adjacent tracks induce cross talk. One may be the aggressor track and the other may be a victim track.
Tracks carry currents. The high frequency signal tracks or high speed signal tracks should be separated from the
ground plane or other tracks running in parallel. Two high-speed signals running in parallel create EMC and EMI, in
particular crosstalk. The golden rule is to keep the tracks short and wide and to keep the return paths equal in length
to onward tracks.
When it comes to EMI, one trace is called the “aggressor,” while the other is the “victim.” An inductive and capacitive
coupling affects the victim trace (track). This is due to an induced electromagnetic field from the aggressor, creating
forward and backward currents in the victim trace.
Crosstalk’s effect on adjacent traces can be minimized by keeping them at least twice the trace width apart. For
example, if trace width is five mils, minimum distance between two parallel traces should be 10 mils or more. A guard
track can be run in between the aggressor track and victim track to minimise coupling.

Avoid 90° angles

To reduce EMI it’s important to avoid 90° angles for traces, vias, and other components because right angles cause
radiation. Here, capacitance increases in the sharp corner and characteristic impedance changes causing reflection,
which in turn causes EMI interference. To avoid 90° angles, traces should be routed at least on two 45° angles to the
corners.
Use vias with care (PTH)
Vias are used for conductive connections between top to bottom layers.. However, vias create inductance and
capacitance. They create reflections because the characteristic impedance changes when a via is made in a trace.

It’s also important to remember that a via increases trace length, which needs to be matched. If Vias are necessary
then use vias in both signal and return traces.
.
Cables and physical shields
Major portion of EMI/EMC is in the external aspects of a system like boxes and cables and wiring. Cables carrying
digital circuits and analog currents are one of the major causes of EMC, creating parasitic capacitance and
inductance. Twisted pair cables are very good at low frequencies. Any pick up will happen in both wires

since they are twisted together closely. Equal pick up in both wires effectively cancel all pick up signals.. For high-
frequency signals, twisted pair is ineffective. Shielded cables are far more effective at higher frequencies. The outer
core called shield is, connected to ground at the front and back, which cancels whatever EMI interference is present.
Physical enclosures (metallic boxes) is another technique to combat EMI/EMC. These metallic packages cover the
entire system or parts of a PCB. These enclosures are grounded which effectively keep EMI from entering into the
PCB’s circuitry.
To summarize
Supply and Gnd conductors
• They carry the entire current of the PCB.
• Width should be appropriate (Maximum wherever possible).
• Use short track lengths.
• Lesser width and higher current increases voltage drops.
• In Double Sided PCBs it may be a good idea to run supply and gnd on either side. Length wise & Width
wise.
• Use exclusive tracks for analoggnd and exclusive tracks for digital gnd. Join them only at the sourcing gnd
point (Usually the main decoupling capacitor) – A strong stable reference point.
• This avoids spikes entering analog parts causing oscillations, errors in decision thresholds and instability.

EMI Interference
o Use good enclosure shielding techniques
o Use of coaxial shielded wires with appropriate Z0.
o Electro static shielding – Gnd tracks between signal tracks.
o Use Chassis as a ground and connect to PCB ground.
o Mains supply is the most corrupted signal. It picks up all kinds of noises.
o Use EMI filters and RF chokes at mains input and along the supply tracks.
o .
o Use same strategy for power supply tracks also. Separation of analog and digital supply tracks are
to be implemented.
o This isolation of supply lines avoids cross coupling disturbances.
o Ground :
a. Use one full layer exclusively for gnd in multilayer boards (or)
b. Use a ground mesh (Grid).
c. Have max gnd track width in all unused areas of the PCB (gnd fill).

o Use decoupling capacitors (ceramic 0.1 µF or 0.01 µF) liberally. Preferably or every IC or every
few ICs.
o SMD capacitors (with Zero lead lengths) more preferable.
o Use tantalum (low leakage) capacitors as high value decoupling capacitors. Do not use normal
electrolytics.

Thumb rule : Wground>WSupply>Wsignal

Digital circuits: Wground>2WSupply

• Do not use SMPS for ADCs, DACs and other analog circuits Buffer them with straight regulators.
• To avoid external magnetic fields, use RF chokes in series with supply tracks.
• Use toroidal transformers in high frequency applications.
• Use ferrite is the magnetic medium.
• Do not keep transformers on PCBs (to avoid magnetic fields).
• LSIs, VLSIs and PLDs (Prog Logic Devices) need ceramic capacitor decoupling right at their supply pins.
• In analog designs. Keep ground loops small or nil. Use filters to filter out unwanted spectrum