Reference + Output

- G

H
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 EXAMPLES OF
CONTROL SYSTEMS

• Position

• Speed

• Liquid Level

• Temperature
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 Pneumatic
valve Controller

Inflow
---------------------
---
---------------------
---------------------
---------------------
---------------------

Outflow
Liquid - level control system
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 Modelling
• Understand the concept
Verbal description/Physical diagram
• Block diagram or Signal flow graph
• Mathematical equations
• Transfer Function (Laplace Transforms)
• Measurement of parameters

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Desired Actual
level Pneumatic Water level
Controller valve tank

Float

Block diagram

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Basic Components of a
Control System

Plant
Transducer
Controller
Amplifier
Actuator
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 Temperature
measuring device
Automatic Hot
controller water

Control
valve
Steam R

Cold
Automatic feedback control of a Drain
water Thermal System
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 Airplane Projected
position

Lead
angle
antenna
Power Radar,
computer
amplifier circuits
Antiaircraft
gun
Drive motor

Actuating signal BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 Systems involved
 Electrical
 Mechanical
 Electromechanical
 Hydraulic
 Pneumatic
 Thermal
 Chemical
 Non - Engineering
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Mathematical Modelling

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Classification of control
systems

• Open Loop / Closed Loop

• Linear/ Non Linear
• Time Invariant Parameter / Time Variant
Parameter
• Lumped Parameter / Distributed Parameter
• Analog / Digital

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

• Y(t)= a x(t) +x3 (t)
• Y(t)= at x(t) +x3 (t)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Mechanical System

+
K
M f
B
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 Mechanical System

+
K
M f
B
Free body diagram approach

Kx

M f
Bx

 
M x  f - Kx - B x
 
M x  B x  Kx  f BITS Pilani, Pilani Campus
Equivalent Mechanical Network

B M K f

g BITS Pilani, Pilani Campus

Electrical Systems
R, L, C, Voltage (e), Current (i)

iR = e / R

ic = C (de/dt)
iL = (1/L) e dt
BITS Pilani, Pilani Campus
Force - current analogy

C M
1/L K

1/R B
BITS Pilani, Pilani Campus
Example: Electromechanical System

i K B
R L
+
eS
+
- M

v
f
BITS Pilani, Pilani Campus
• voltage source es
• current i
• force f
• velocity v
• back emf eb

BITS Pilani, Pilani Campus

es i f v

eb

BITS Pilani, Pilani Campus

es + (es - eb) i f v
-
eb

BITS Pilani, Pilani Campus

 Equations
(es-eb) = Ri + L di/dt

f = K1 i

f = M dv/dt+Bv+K  vdt
eb = K 2 v

BITS Pilani, Pilani Campus

input output
x K y

y = K x

BITS Pilani, Pilani Campus

In our example

i f
K1

v eb
K2

BITS Pilani, Pilani Campus

Now
e i
?
Take Laplace Transform of
e = Ri + Ldi/dt
E (s) = R I (s) + Ls I (s)
= (R + Ls) I(s)
assuming ?

Initial Conditions to be Ignored/zero

BITS Pilani, Pilani Campus
1 /( s  a) → e
-at

s
2 2
→ cos at
( s) + a
s+b
2 2
→ e cos at
- bt

(s+b) +a
a
2 2
→ sin at
( s) + a
a
2 2
→ e sin at
- bt

(s+b) +a
BITS Pilani, Pilani Campus
 E I
?
I(s)/E(s) = 1/(R + Ls) = G1 (s) (say)

BITS Pilani, Pilani Campus

Similarly

F v
?

BITS Pilani, Pilani Campus

 F v
?
? = 1 / ( Ms + B + K /s )

= G2 (say)
BITS Pilani, Pilani Campus
es + e i f v
G1 K1 G2
-
eb

K2

BITS Pilani, Pilani Campus

Block Diagram Reduction Techniques
x x2 x
1 G1 G2 3

X2 / X1 = G1
X3 / X2 = G2
Therefore

X3 / X1 = G1.G2
BITS Pilani, Pilani Campus
Block Diagram Reduction Techniques:

G1 G2 G3

becomes

G1 G2 G3

BITS Pilani, Pilani Campus

es + e G1 G2 K1
v
-
eb

K2
BITS Pilani, Pilani Campus
Let us take

R + E C
G
-

H
where E = R-CH & C = GE
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
G1
+

+
G2

becomes
G1 + G2

BITS Pilani, Pilani Campus

 z
+
x +
becomes
-
y z
+
x + +
-
y
BITS Pilani, Pilani Campus
R + C
G
-
H

C G
R 1+ GH
BITS Pilani, Pilani Campus
R + C
G
+
H

C G
R 1- GH
BITS Pilani, Pilani Campus
 In the example under
discussion

es e v
+ G1 G2 K1
-

K2
V (s) G1 G2 K1
--------- = ----------------------------
Es (s) 1+ G1G2K1K2 BITS Pilani, Pilani Campus