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TABLE I
D EVELOPING C ONDITIONS FOR R EDUCED L EAKAGE
C URRENT D URING P OWER S TATE
Fig. 6. Operating modes of the proposed hybrid converter in shoot-through Fig. 8. Operating modes of the proposed hybrid converter in power state.
state: (a) for v ac > 0. (b) for v ac < 0. (a) for v ac > 0. (b) for v ac < 0.
Fig. 9. Switching waveforms: (a) PWM signals for positive half cycle of ac output voltage, v ac > 0. (b) PWM signals for negative half cycle of ac output
voltage, v ac < 0. (c) Inductor current (i L ), diode current (i D ), and switch node current (iSN ) for v ac > 0.
TABLE II
C OMPLETE S WITCHING S TATES OF THE P ROPOSED C ONVERTER
TABLE III
T OTAL C OMMON -M ODE V OLTAGE T HROUGH OUT THE S WITCHING C YCLE
ratio (D). The output dc voltage expression is same as boost The peak output ac voltage is a function of both modulation
converter and is given by index (Ma ) and D. The expression for the peak output ac
voltage is given by
VPV
Vdc = (6) (V ac )pk = Ma Vdc (7)
1− D
Ma V P V
(V ac )pk = . (8)
where Vdc = average output voltage at the dc side. 1− D
1334 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 7, NO. 2, JUNE 2019
As the same set of switches control the dc and ac output as I L ,pk−pk of the average current and LF output voltage
voltages, the following constraint exists on Ma and D for the ripple equal as V dc,pk−pk of average dc output voltage (Vdc ).
proposed hybrid converter: Limiting LF oscillation was the main design criteria. From the
chosen specifications of the proposed topology, the L and Cdc
Ma + D ≤ 1. (9)
can be designed to satisfy (20) by assuming V dc,pk−pk and
The dc output power of the proposed hybrid converter is given I L ,pk−pk .
by The ac side passive (L f and C f ) components are design
based on the corner frequency of L f and C f , and switching
(VPV )2
Pdc = . (10) frequency of the controlled switches. To design the ac side
Rdc (1 − D)2 passive components, corner frequency is chosen to be kept
Instantaneous ac output power ( pac ) is given by at ( f sw /9), where f sw is switching frequency. It gives enough
attenuation at 10 KHz switching frequency
pac = (v ac ) × (i ac ) (11)
1 f sw
(Vac )2 = . (21)
Pac = (12) 2π L f C f 9
Rac
(Vac )2pk (sin ωt)2 Therefore, the ac side passive components can be chosen to
pac = (13) satisfy (21).
Rac
(Vac )2pk (1 − cos 2ωt)
pac = (14) E. Power Loss Analysis of the Proposed Converter
2Rac
(Vac )2pk (Vac )2pk Power losses in the proposed converter occur due to con-
pac = − cos 2ωt. (15) duction and switching states of the semiconductor devices, and
2Rac 2Rac
due to losses in the passive components [24], [25].
Instantaneous ac power pac contains steady state component 1) Conduction Losses in the Semiconductor Devices: The
as well as time varying ac component. The steady state power dissipation during conduction is computed by multiply-
component is the real power consumed by the load and ing the ON-state voltage and the ON-state current. In PWM
is denoted by Pac . The time varying ac component of the converters, the conduction loss for the controlled switches
instantaneous power is denoted by p̃ac and is given by (insulated-gate-bipolar transistors (IGBTs) are considered in
(v ac )2pk this paper) must be multiplied by the duty factor to obtain the
p̃ac = cos 2ωt (16) average power dissipation as given in the following equation:
2Rac
= Pac − p̃ac .
pac (17) 1 T
Pavg,cond = VCE,Sat (t) ∗ i CE (t)d x (22)
Furthermore, if I L is the average inductor (L) current, then T 0
Pdc + Pac where VCE,Sat is the ON state saturation voltage of an IGBT
IL = . (18) and i CE is the instantaneous current flowing through the IGBT.
VPV
Conduction loss for the diode D can be calculated as
Component p̃ac is balanced by i L and capacitor (Cdc ) volt- follows:
age v dc ; therefore, inductor current (i L ) and capacitor voltage
(v dc ) contain LF ripple (twice the ac output voltage frequency). PD,avg,cond = V D I D (23)
The power balance equation is given by
where V D is diode forward voltage drop and I D is average
d 12 Cdc v dc
2 + 1 Li 2
L diode current. For the conduction losses of the semiconduc-
p̃ac = 2
(19)
dt tor devices, the conduction sates of the devices are shown
Pac in Fig. 10.
L I L I L ,pk−pk + C Vdc V dc,pk−pk = . (20)
ω 2) Switching Losses in the Semiconductor Devices: In
LF ripples in the output dc voltage as well as in inductor power electronics switching losses typically contribute a sig-
current increases with an increase in ac load current. By sim- nificant amount to the total system losses. Switching losses
plifying (19), (20) is obtained and it can be observed from (20) occurred because the transitions from ONstate to OFFstate and
that if Pac increases, LF ripples V dc,pk−pk and I L ,pk−pk vice versa, do not occur instantaneously. During the transition
increases. Values of L and Cdc can be designed using (20). intervals, both the current through and the voltage across the
device are substantially larger than zero, which leads to large
instantaneous power loss. The switching power losses in the
D. Design of Passive Elements
controlled switches are calculated based on the normalized
The dc side passive components (L and Cdc ) are designed values (provided in the manufactures datasheet) as follows:
based on (20). Due to the presence of single-phase inverter
system in the proposed topology, there is LF oscillation PSw
(2 ∗ 50 = 100 Hz) in the both the dc output voltage and (E ON + E OFF )Vdc × average current through IGBT × f sw
=
the input inductor current. For designing L and Cdc , consider Vnom Inom
the LF allowable ripple in the input inductor (L) current (24)
DEY et al.: TRANSFORMERLESS HYBRID CONVERTER WITH AC AND DC OUTPUTS AND REDUCED LEAKAGE CURRENT 1335
Fig. 11. Inductor current and voltage sensing of ac output of the proposed
hybrid converter.
Fig. 14. Bode plots: (a) AC outer voltage controller. (b) AC inner current controller. (c) DC Voltage controller.
Taking Laplace transformation of (31) and (32), inner current converter [26] and is given by
loop and outer voltage loop transfer function are given by
ṽ dc Vdc D − s L Vdc
D Rdc
I L f d (s) I L f q (s) 1 = . (35)
s 2 LCdc + 2
Rdc + D
sL
= = (33) d̃
Uid (s) Uiq (s) r + sL f
Vc f d (s) Vc f q (s) Rac The type-3 controller is used to get gain margin = 20 dB
= = (34) and phase margin = 61.8°. Fig. 14(c) shows bode plot
Uvd (s) Uvq (s) Rac C f + 1
of uncompensated and compensated system for dc output.
where It may be observed from Fig. 14(c) that the phase margin for
Uid (s) = Md (s)V Dc + ωL f I L f q (s) − v c f d (s) uncompensated and compensated system is −19.5° and 61.8°,
respectively. It is also clear from Fig. 14(c) that the gain
Uiq (s) = Mq (s)V Dc + ωL f I L f q (s) − v c f q (s) margin for uncompensated and compensated system is
Uvd (s) = I L f d (s) + ωC f Vc f q (s) −45.8 dB and 20 dB, respectively.
Uvq (s) = I L f q (s) − ωC f Vc f d (s).
VI. E XPERIMENTAL V ERIFICATION
Closed loop control structure for ac output of the proposed The proposed transformerless hybrid converter with
hybrid converter is given in Fig. 13. To design a controller reduced leakage current is validated through experimentation
for outer ac voltage loop, a Type-2 controller is used to have on 300 W laboratory prototype. Fig. 15 shows the overall
adequate gain and phase margin. Fig. 14(a) shows a bode implementation of the proposed algorithm. Fig. 16 shows the
plot for uncompensated and compensated ac voltage loop. photograph of the experimental set up. According to [23], the
It can be observed from Fig. 14(a) that for voltage loop, phase PV-to-ground capacitance for the glass-face modules should
margin = 84.2◦ and bandwidth = 578 Hz are achieved. be 50–150 nF/kW and 1 μF/kW for thin-film modules in
Fig. 14(b) shows bode plot for uncompensated and compen- damp environment. In this paper, for experimental analysis,
sated inner current loop, and it is clear that phase margin = 90° the value of CPVg (shown in Fig. 5) is taken equal to 110 nF.
and bandwidth = 3 kHz are achieved.
A. Steady-State Performance of the Proposed Hybrid
B. DC Side Voltage Controller Converter at Low Power Operating Condition
The control-to-output transfer function of the proposed The steady state performance of the proposed trans-
hybrid converter is same as that of the conventional boost formerless hybrid converter is validated for the following
DEY et al.: TRANSFORMERLESS HYBRID CONVERTER WITH AC AND DC OUTPUTS AND REDUCED LEAKAGE CURRENT 1337
Fig. 18. Closed loop steady state results. (a) VPV = 80 V, Vdc = 125 V,
(Vac )pk = 60 V, and iLeakage . (b) VPV , Vdc , Vac , and inductor current i L
containing 100 Hz component.
Fig. 17. Experimental verification of PWM signals. (a) PWM signals for S1 ,
S2 , S3 , and S4 for positive half cycle of ac output voltage. (b) PWM signals
for S1 , S4 , S5 , and S6 .
Fig. 19. Steady state results VPV , i L2 , iLf , and v ac . (a) For positive half
specifications: input voltage to the converter VPV = 80 V, cycle (v ac > 0) filter current flows through L 1 . (b) For negative half cycle
(v ac < 0) inductor current flows through L 2 .
duty ratio D = 0.36, modulation index Ma = 0.48, switching
frequency = 10 kHz, line frequency = 50Hz, L = 1120 μH,
Cdc = 1800 μF, L f (= L 1 = L 2 ) = 2 mH, and CPVg = It can also be observed from Fig. 18(a) that the leak-
110 nF. Fig. 17(a) shows PWM signals given to the switches age current i Leakage is significantly small. Fig 18(b) shows
S1 to S4 for the positive half cycle of ac output voltage and inductor (L) current (i L ), input voltage (VPV ), output dc
Fig. 17(b) shows PWM signals given to the switches of one voltage (Vdc ), and output ac voltage (Vac ). It may be observed
leg, S5 and S6 . It can be seen from Fig. 17(b) that during from Fig. 18(b) that i L contains twice the ac line frequency
positive half cycle, S1 and S4 are operated and S5 is kept ON. component (100 Hz) as described in Section III.
Fig. 18(a) shows the steady state results showing input volt- Fig. 19(a) shows that for positive half cycle of ac output
age (VPV ), output dc voltage (Vdc ), output ac voltage (Vac ) and voltage (Vac ), inductor (L 2 ) current i L2 is zero because the net
leakage current (i Leakage ). It can be observed from Fig. 18(a) filter inductor current i Lf (i Lf = i L1 in this case) is bypassed
that for VPV = 80 V and given reference voltages (60 V peak by the switch S5 . During negative half cycle of the Vac , net
for ac reference and 125 V for dc reference), the proposed filter inductor current flows through L 2 and i L1 is equal to
converter gives (Vac )pk = 60 V and Vdc = 125 V. zero, which is shown in Fig. 19(b).
1338 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 7, NO. 2, JUNE 2019
Fig. 20. (a) Switching waveforms of the proposed hybrid converter (PWM Fig. 22. (a) Switch node voltage along with leakage current profile.
signal S1 and S4 , input inductor current i L , and diode current i D ). (b) Results (b) Inductor current i L along with the switch node voltage.
confirming no HF component in voltage across CPVg and reduced leakage
current iLeakage .
Fig. 21. (a) Switching voltage stress of S1 and S4 along with i L and G S1 .
(b) Switching voltage stress of S5 and S6 along with iLf and Vac .
TABLE IV
C OMPARATIVE A NALYSIS A MONG THE P ROPOSED C ONVERTER AND S OME C ONVENTIONAL T OPOLOGIES
Fig. 25. Efficiency variation with change in the load power. (a) Efficiency
versus output load with variation in ac output load. (b) Efficiency versus output
load with variation in dc output load.
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nanogrid applications,” IEEE Trans. Power Electron., vol. 28, no. 3, from the Vignan’s Engineering College (Vignan
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