63a4a Compal LA-9161P

A B C D E
1 1
VCUAA
2
Metis 10F/10FG 2
LA-9161P REV 1.0 Schematic

Intel Processor (Ivy Bridge) / PCH(Panther Point)
2012-08-07 Rev 1.0
3 3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VCUAA
Date: Tuesday, October 16, 2012 Sheet 1 of 53
A B C D E
A B C D E
Intel CPU
PCI-Express 16X Gen2 Ivy Bridge Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2
17W Dual Channel BANK 0, 1, 2, 3 page 11,12
1.5V DDRIII 1066/1333/1600 MT/s

BGA-1023 GCLK
1 1
31mm*24mm
SLG3NB300VTR page 34
page 5,6,7,8,9,10
VGA (DDR3)
nVIDIA N13P-GL with 2GB
FDI X8 DMI X4
2.7GT/s 5GT/s
page 13,14,15,16,17,18,19,20,21
USB30 2x
5V 5GT/s USB Left USB Right
USB20 port 2 USB20 port 0,1
USB20 3x USB30 port 1,2
page 37 page 37
LVDS Conn. 5V 480MHz
page 22
Intel PCH USB20 2x CardReader RTS5137 Int. Camera

2 HDMI Conn. Panther Point 5V 480MHz USB20 port 8 USB port 11 2
page 36 page 22
page 23
FCBGA-989
PCIe Gen1 1x PCIeMini Card
RJ45 RTL8105E-VD 10/100M PCIe Gen1 1x 25mm*25mm 1.5V 5GT/s
page 35 1.5V 5GT/s
WLAN PCIe port 2
page 34
PCIe port 1 page 35
SATA Gen3 port 0 SATA HDD

SATA port 0
5V 6GHz(600MB/s) page 33
SATA Gen3 port 1 SATA mSATA

5V 3GHz(300MB/s) SATA port 1
page 24,25,26,27,28,29,30,31,32 page 34
TP/B
page 41
3 LED+LID/B LPC BUS HD Audio 3
page 41
3.3V 33 MHz 3.3V 24MHz
RTC CKT. SPI ROM

page 24
Debug Port KB9012 HDA Codec
(4MB +page
2MB)
24 page 41 page 40 ALC259
page 38
DC/DC Interface CKT.
page 42
Touch Pad Int.KBD SPK Conn JPIO

page 39
Power Circuit DC/DC page 41 page 41 (HP &page
MIC)39
page 43,44,45,46,47,48,
49,50,51
Power On/Off CKT.

4
page 41 4

Block Diagram
1.0
VCUAA
A B C D E
5 4 3 2 1
DESIGN CURRENT 0.1A +3VL

DESIGN CURRENT 0.1A +5VL
B+
Ipeak=8.13A, Imax=5.69A, Iocp min=8.7 DESIGN CURRENT 5A +5VALW
SUSP#
D D
DESIGN CURRENT 2A +1.8VS
SY8033BDBC
SUSP
N-CHANNEL DESIGN CURRENT 4A +5VS

SI4800
RT8205LZQW
VCCP_PWRGOOD
Ipeak=6A, Imax=4.A, Iocp min=8 DESIGN CURRENT 6A +VCCSA

SY8037
Ipeak=5A, Imax=3.5A, Iocp min=6.2A DESIGN CURRENT 5A +3VALW

C C
WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN

AO-3413
SUSP
N-CHANNEL DESIGN CURRENT 4A +3VS

SI4800 LCD_ENVDD
P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD

AO-3413
DGPU_PWR_EN
DESIGN CURRENT 60mA +3VS_DGPU
P-CHANNEL
AO-3413
DESIGN CURRENT 2A +3V_WLAN

VR_ON PJ6
DESIGN CURRENT 94A +CPU_CORE

NCP6132A DESIGN CURRENT 33A +GFX_CORE
SUSP#
B
Ipeak=20.53A, Imax=14.37A, Iocp min=23.91A +1.05VS_VCCP B
TPS51212
VGA_PWROK
DESIGN CURRENT 60mA +1.05VS_DGPU
P-CHANNEL
AO-3413
SYSON
Ipeak=15A, Imax=10.5A, Iocp min=18A DESIGN CURRENT 10A +1.5V
RT8207M SUSP
N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU

FDS6676AS
DESIGN CURRENT 2A +1.5VS

PJ1
SUSP or 0.75VR_EN#
DESIGN CURRENT 1.5A +0.75VS
VGA_PWROK
A DESIGN CURRENT 8.6A A

N-CHANNEL +VRAM_1.5VS
FDS6676AS
SUSP#
Ipeak=33.8A, Imax=23.4A, Iocp min=40A DESIGN CURRENT 20.5A +VGA_CORE

TPS51518RUKR

Power Tree
1.0
VCUAA
5 4 3 2 1
A B C D E
( O MEANS ON X MEANS OFF )

Voltage Rails Platform SKU CPU PCH VGA
+5VS Ivy Bridge i3
+RTCVCC B+ +5VL +5VALW +1.5V HM77C1(HM77@)
+3VS (CPUI3@) nVIDIA N13P-GL
+3VL +3VALW Chief River HM77C1_R1(HM77R1@)
+1.8VS Ivy Bridge i5 (N13PGL@)
+VSB HM77C1_R3(HM77R3@)
power +1.5VS (CPUI5@)
plane +1.05VS
+0.75VS
1 BTO Option Table 1
+CPU_CORE
+VGA_CORE
Function SKU MIC LAN
+GFX_CORE
+VTT description
State
+VRAM_1.5VS
+3VS_DGPU
explain
+1.05VS_DGPU BTO
S0
O O O O O O
S1
O O O O O O
S3
O O O O O X
2
S5 S4/AC
Function 2
O O O O X X
description
S5 S4/ Battery only
O O O X X X explain
S5 S4/AC & Battery BTO
don't exist
O X X X X X
Function
PCH SM Bus Address description
explain
Power Device HEX Address
BTO
+3VS DDR SO-DIMM 0 A0 H 1010 0000 b
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b
Function
description
3 3
explain
BTO
SIGNAL
EC SM Bus1 Address EC SM Bus2 Address STATE SLP_S3# SLP_S4# SLP_S5#
Full ON HIGH HIGH HIGH

Power Device HEX Address Power Device HEX Address
S1(Power On Suspend) HIGH HIGH HIGH
+3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b
+3VL Smart Charger 12 H 0001 0010 b +3VS NVIDIA GPU 9E H 1001 1010 b S3 (Suspend to RAM) LOW HIGH HIGH
S4 (Suspend to Disk) LOW LOW HIGH

Power Device HEX Address S5 (Soft OFF) LOW LOW LOW
G3 LOW LOW LOW
4 4

Notes List
Custom 1.0
VCUAA
A B C D E
A B C D E
UC1B 100 MHz

J3 CLK_CPU_DMI
BCLK CLK_CPU_DMI <25> +1.05VS_VCCP
H2 CLK_CPU_DMI#
BCLK# CLK_CPU_DMI# <25>
MISC
@
CLOCKS
1000P_0402_50V7K 2 1 CC62 PM_DRAM_PWRGD_R H_SNB_IVB# F49
<29> H_SNB_IVB# PROC_SELECT#
DPLL_REF_CLK AG3 DPLL_REF_CLK DPLL_REF_CLK# RC1571 2 1K_0402_5%
@
DPLL_REF_CLK# AG1 DPLL_REF_CLK#
1000P_0402_50V7K 2 1 CC63 H_PWRGOOD_R T1 PAD TP_SKTOCC# C57 DPLL_REF_CLK RC1581 2 1K_0402_5%
PROC_DETECT#
T2 PAD H_CATERR# C49 @

CATERR# H_DRAMRST# 1 2
THERMAL
1 CC34 180P_0402_50V8J 1
H_PECI A48 AT30 H_DRAMRST#

+1.05VS_VCCP <40> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
by ESD requestion and place near CPU
RC159 BF44 SM_RCOMP_0 RC56 2 1 140_0402_1% DDR3 Compensation Signals
DDR3
MISC
RC44 SM_RCOMP[0]
2 1 62_0402_5% H_PROCHOT# <40> H_PROCHOT# 1 2 H_PROCHOT#_R C45 PROCHOT# SM_RCOMP[1] BE43 SM_RCOMP_1 RC59 2 1 25.5_0402_1% Layout Note:Place these
56_0402_5% BG43 SM_RCOMP_2 RC61 2 1 200_0402_1% resistors near Processor
SM_RCOMP[2]
RC45 2 1 10K_0402_5% H_PWRGOOD H_THERMTRIP# D45

<29> H_THERMTRIP# THERMTRIP#
PRDY# N53
PREQ# N55
L56 XDP_TCK T3 PAD @

TCK XDP_TMS T4 PAD @
TMS L55
PWR MANAGEMENT
J58 XDP_TRST# 1 2 Routed as a single daisy chain
TRST# RC55 51_0402_5%
JTAG & BPM

@ <26> H_PM_SYNC H_PM_SYNC C48 M60 XDP_TDI
1000P_0402_50V7K 2 PM_SYNC TDI
1 CC70 H_PECI
TDO L59 XDP_TDO T6 PAD @
T7 PAD @
@
1000P_0402_50V7K 2 1 CC67 H_PM_SYNC <29> H_PWRGOOD 1 @ 2 H_PWRGOOD_R B46
RC183 0_0402_5% UNCOREPWRGOOD
DBR# K58
@
1000P_0402_50V7K 2 1 CC66 BUF_CPU_RST#
PM_SYS_PWRGD_BUF 1 2 PM_DRAM_PWRGD_R BE45 G58
RC170 130_0402_5% SM_DRAMPWROK BPM#[0]
BPM#[1] E55
BPM#[2] E59
2 Please place near JCPU BPM#[3] G55
G59 2
BUF_CPU_RST# BPM#[4]
D44 RESET# BPM#[5] H60
BPM#[6] J59
BPM#[7] J61
+3VALW_PCH
Close to CPU side
2 1 DRAMPWROK +3VALW_PCH
RC11 200_0402_5% +1.5V_CPU
2 1 IVY-BRIDGE_BGA1023 <BOM>
1
10K_0402_5% 0.1U_0402_10V7K
+3VS 2 RC13 1 CC33 RC14
UC3 200_0402_5%
5
74AHC1G09GW_TSSOP5
2
1 2 1
P
<26,40> PM_PWROK
RC12 @ 0_0402_5% B 4 PM_SYS_PWRGD_BUF
O
1
<26> DRAMPWROK 2 A
G
RC25
39_0402_5%
3
@
2
1 @ 2 0_0402_5%
RC184
1
QC2 D
<34,42,9> SUSP SUSP 2
G
2N7002KW_SOT323-3
S@
3
3 3
Buffered Rest to CPU XDP Connector FAN Control Circuit

+3VS
+5VS +3VS
1 0.1U_0402_10V7K
1
CC36 1A JFAN @
+1.05VS_VCCP 1 @ 2 +FAN1 R2 7
PLT_RST# <28,34,35,40,41> GND2
2 R1 0_0603_5% 10K_0402_5% 6
2 GND1
5 5
1
UC2 C3 4
2
PLT_RST# RC38 10U_0805_10V6K 4
1 OE# <40> FANPWM 3 3
5 75_0402_5% @ 1 2
VCC <40> FAN_SPEED1 2
1 +FAN1 1
RC35 C4 1
2
2
IN 43_0402_1% 0.01U_0402_25V7K ACES_88266-05001

4 BUFO_CPU_RST# 1 2 BUF_CPU_RST# @
OUT 2
3 GND
1
74AHC1G125GW_SOT353-5 RC40
0_0402_5%
@
2
1
1 1
D1 C5 C6
4 4
BAS16_SOT23-3 2 2
2
10U_0603_6.3V6M 1000P_0402_50V7K

Ivy Bridge_JTAG/XDP/FAN
Custom 1.0
VCUAA
A B C D E
A B C D E
PEG_ICOMPI and RCOMPO signals should be

+1.05VS_VCCP shorted and routed
with - max length = 500 mils - typical
1
impedance = 43 m ohm (4 mils)
RC1
24.9_0402_1%
PEG_ICOMPO signals should be routed with -
max length = 500 mils
UC1A
- typical impedance = 14.5 m ohm (12 mils)
2
G3 PEG_COMP
PEG_ICOMPI
PEG_ICOMPO G1
1 DMI_PTX_CRX_N0 1
<26> DMI_PTX_CRX_N0 M2 DMI_RX#[0] PEG_RCOMPO G4
DMI_PTX_CRX_N1 P6
<26> DMI_PTX_CRX_N1 DMI_RX#[1]
DMI_PTX_CRX_N2 P1
<26> DMI_PTX_CRX_N2 DMI_RX#[2] PCIE_GTX_C_CRX_N[0..15] <13>
DMI_PTX_CRX_N3 P10 H22 PCIE_GTX_C_CRX_N0
<26> DMI_PTX_CRX_N3 DMI_RX#[3] PEG_RX#[0]
J21 PCIE_GTX_C_CRX_N1
DMI_PTX_CRX_P0 PEG_RX#[1] PCIE_GTX_C_CRX_N2
<26> DMI_PTX_CRX_P0 N3 DMI_RX[0] PEG_RX#[2] B22
DMI_PTX_CRX_P1 P7 D21 PCIE_GTX_C_CRX_N3
<26> DMI_PTX_CRX_P1 DMI_RX[1] PEG_RX#[3]
DMI
DMI_PTX_CRX_P2 P3 A19 PCIE_GTX_C_CRX_N4
DMI_PTX_CRX_P3 P11 D17 PCIE_GTX_C_CRX_N5
B14 PCIE_GTX_C_CRX_N6
DMI_CTX_PRX_N0 PEG_RX#[6] PCIE_GTX_C_CRX_N7
<26> DMI_CTX_PRX_N0 K1 DMI_TX#[0] PEG_RX#[7] D13
DMI_CTX_PRX_N1 M8 A11 PCIE_GTX_C_CRX_N8
<26> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
DMI_CTX_PRX_N2 N4 B10 PCIE_GTX_C_CRX_N9
DMI_CTX_PRX_N3 R2 G8 PCIE_GTX_C_CRX_N10
A8 PCIE_GTX_C_CRX_N11
DMI_CTX_PRX_P0 PEG_RX#[11] PCIE_GTX_C_CRX_N12
<26> DMI_CTX_PRX_P0 K3 DMI_TX[0] PEG_RX#[12] B6
DMI_CTX_PRX_P1 M7 H8 PCIE_GTX_C_CRX_N13
<26> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]
DMI_CTX_PRX_P2 P4 E5 PCIE_GTX_C_CRX_N14
DMI_CTX_PRX_P3 T3 K7 PCIE_GTX_C_CRX_N15
PCIE_GTX_C_CRX_P[0..15] <13>
K22 PCIE_GTX_C_CRX_P0
PEG_RX[0] PCIE_GTX_C_CRX_P1
PEG_RX[1] K19
C21 PCIE_GTX_C_CRX_P2
FDI_CTX_PRX_N0 PEG_RX[2] PCIE_GTX_C_CRX_P3
<26> FDI_CTX_PRX_N0 U7 FDI0_TX#[0] PEG_RX[3] D19
FDI_CTX_PRX_N1 W11 C19 PCIE_GTX_C_CRX_P4
<26> FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
FDI_CTX_PRX_N2 W1 D16 PCIE_GTX_C_CRX_P5
FDI_CTX_PRX_N3 AA6 C13 PCIE_GTX_C_CRX_P6
FDI_CTX_PRX_N4 W6 D12 PCIE_GTX_C_CRX_P7
FDI_CTX_PRX_N5 PCIE_GTX_C_CRX_P8
PCI EXPRESS -- GRAPHICS

<26> FDI_CTX_PRX_N5 V4 FDI1_TX#[1] PEG_RX[8] C11
FDI_CTX_PRX_N6 Y2 C9 PCIE_GTX_C_CRX_P9
FDI_CTX_PRX_N7 AC9 F8 PCIE_GTX_C_CRX_P10
Intel(R) FDI
C8 PCIE_GTX_C_CRX_P11
2 PEG_RX[11] PCIE_GTX_C_CRX_P12 2
PEG_RX[12] C5
FDI_CTX_PRX_P0 U6 H6 PCIE_GTX_C_CRX_P13
<26> FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
FDI_CTX_PRX_P1 W10 F6 PCIE_GTX_C_CRX_P14
FDI_CTX_PRX_P2 W3 K6 PCIE_GTX_C_CRX_P15
FDI_CTX_PRX_P3 AA7
<26> FDI_CTX_PRX_P3 FDI0_TX[3] PCIE_CTX_C_GRX_N[0..15] <13>
FDI_CTX_PRX_P4 W7 G22 PCIE_CTX_GRX_N0 CC8 1 2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_N0
<26> FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
FDI_CTX_PRX_P5 T4 C23 PCIE_CTX_GRX_N1 CC11 1 2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_N1
FDI_CTX_PRX_P6 AA3 D23 PCIE_CTX_GRX_N2 CC16 1 2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_N2
FDI_CTX_PRX_P7 AC8 F21 PCIE_CTX_GRX_N3 CC20 1 2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_N3
H19 PCIE_CTX_GRX_N4 CC27 1 2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_N4
FDI_FSYNC0 PEG_TX#[4] PCIE_CTX_GRX_N5 CC30 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_N5
<26> FDI_FSYNC0 AA11 FDI0_FSYNC PEG_TX#[5] C17 1 2
<26> FDI_FSYNC1 FDI_FSYNC1 AC12 K15 PCIE_CTX_GRX_N6 CC1 1 2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_N6
FDI1_FSYNC PEG_TX#[6] PCIE_CTX_GRX_N7 CC4 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_N7
PEG_TX#[7] F17 1 2
<26> FDI_INT FDI_INT U11 F14 PCIE_CTX_GRX_N8 CC15 1 2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_N8
FDI_INT PEG_TX#[8] PCIE_CTX_GRX_N9 CC18 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_N9
PEG_TX#[9] A15 1 2
<26> FDI_LSYNC0 FDI_LSYNC0 AA10 J14 PCIE_CTX_GRX_N10 CC22 1 2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_N10
FDI_LSYNC1 FDI0_LSYNC PEG_TX#[10] PCIE_CTX_GRX_N11 CC24 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_N11
<26> FDI_LSYNC1 AG8 FDI1_LSYNC PEG_TX#[11] H13 1 2
M10 PCIE_CTX_GRX_N12 CC29 1 2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_N12
PEG_TX#[12] PCIE_CTX_GRX_N13 CC26 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_N13
PEG_TX#[13] F10 1 2
D9 PCIE_CTX_GRX_N14 CC3 1 2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_N14
PEG_TX#[14] PCIE_CTX_GRX_N15 CC32 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_N15
PEG_TX#[15] J4 1 2
+1.05VS_VCCP RC2 1 2 24.9_0402_1% EDP_COMP AF3 eDP_COMPIO PCIE_CTX_C_GRX_P[0..15] <13>
AD2 F22 PCIE_CTX_GRX_P0 CC10 1 2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_P0
RC3331 eDP_ICOMPO PEG_TX[0] PCIE_CTX_GRX_P1 PCIE_CTX_C_GRX_P1
+1.05VS_VCCP 2 1K_0402_5% AG11 eDP_HPD# PEG_TX[1] A23 CC5 1 2 OPT@ 0.22U_0402_16V7K
D24 PCIE_CTX_GRX_P2 CC6 1 2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_P2
PEG_TX[2] PCIE_CTX_GRX_P3 CC7 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_P3
PEG_TX[3] E21 1 2
AG4 G19 PCIE_CTX_GRX_P4 CC12 1 2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_P4
eDP_AUX# PEG_TX[4] PCIE_CTX_GRX_P5 CC9 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_P5
AF4 eDP_AUX PEG_TX[5] B18 1 2
K17 PCIE_CTX_GRX_P6 CC19 1 2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_P6
PEG_TX[6]
eDP
G17 PCIE_CTX_GRX_P7 CC14 1 2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_P7

PEG_TX[7] PCIE_CTX_GRX_P8 CC13 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_P8
AC3 eDP_TX#[0] PEG_TX[8] E14 1 2
AC4 C15 PCIE_CTX_GRX_P9 CC17 1 2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_P9
3 eDP_TX#[1] PEG_TX[9] PCIE_CTX_GRX_P10 CC21 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_P10 3
AE11 eDP_TX#[2] PEG_TX[10] K13 1 2
AE7 G13 PCIE_CTX_GRX_P11 CC23 1 2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_P11
eDP_TX#[3] PEG_TX[11] PCIE_CTX_GRX_P12 CC28 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_P12
PEG_TX[12] K10 1 2
AC1 G10 PCIE_CTX_GRX_P13 CC25 1 2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_P13
eDP_TX[0] PEG_TX[13] PCIE_CTX_GRX_P14 CC2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_P14
AA4 eDP_TX[1] PEG_TX[14] D8 1 2
AE10 K4 PCIE_CTX_GRX_P15 CC31 1 2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_P15
eDP_TX[2] PEG_TX[15]
AE6 eDP_TX[3]
IVY-BRIDGE_BGA1023 <BOM>
PEG DG suggest AC cap
Gen1/Gen2 75 nF~265 nF
IVY Bridge
Gen3 180 nF~265 nF
SANDY Bridge Gen1/Gen2 180 nF~265 nF
NV N13X Gen1/2/3 Suggest 220 nF
4 4

Ivy Bridge_DMI/PEG/FDI
Custom 1.0
VCUAA
A B C D E
A B C D E
<11> DDR_A_D[0..63]
<12> DDR_B_D[0..63]
UC1C UC1D
DDR_A_D0 AG6 DDR_B_D0 AL4

DDR_A_D1 SA_DQ[0] DDRA_CLK0 DDR_B_D1 SB_DQ[0] DDRB_CLK0
AJ6 SA_DQ[1] SA_CK[0] AU36 DDRA_CLK0 <11> AL1 SB_DQ[1] SB_CK[0] BA34 DDRB_CLK0 <12>
DDR_A_D2 AP11 AV36 DDRA_CLK0# DDR_B_D2 AN3 AY34 DDRB_CLK0#
SA_DQ[2] SA_CK#[0] DDRA_CLK0# <11> SB_DQ[2] SB_CK#[0] DDRB_CLK0# <12>
DDR_A_D3 AL6 AY26 DDRA_CKE0 DDR_B_D3 AR4 AR22 DDRB_CKE0
SA_DQ[3] SA_CKE[0] DDRA_CKE0 <11> SB_DQ[3] SB_CKE[0] DDRB_CKE0 <12>
DDR_A_D4 AJ10 DDR_B_D4 AK4
DDR_A_D5 SA_DQ[4] DDR_B_D5 SB_DQ[4]
AJ8 SA_DQ[5] AK3 SB_DQ[5]
DDR_A_D6 AL8 DDR_B_D6 AN4
AL7 SA_DQ[7] AR1 SB_DQ[7]
1 DDR_A_D8 DDR_B_D8 1
AR11 SA_DQ[8] AU4 SB_DQ[8]
DDR_A_D9 AP6 AT40 DDRA_CLK1 DDR_B_D9 AT2 BA36 DDRB_CLK1
SA_DQ[9] SA_CK[1] DDRA_CLK1 <11> SB_DQ[9] SB_CK[1] DDRB_CLK1 <12>
DDR_A_D10 AU6 AU40 DDRA_CLK1# DDR_B_D10 AV4 BB36 DDRB_CLK1#
SA_DQ[10] SA_CK#[1] DDRA_CLK1# <11> SB_DQ[10] SB_CK#[1] DDRB_CLK1# <12>
DDR_A_D11 AV9 BB26 DDRA_CKE1 DDR_B_D11 BA4 BF27 DDRB_CKE1
SA_DQ[11] SA_CKE[1] DDRA_CKE1 <11> SB_DQ[11] SB_CKE[1] DDRB_CKE1 <12>
DDR_A_D12 AR6 DDR_B_D12 AU3
AP8 SA_DQ[13] AR3 SB_DQ[13]
DDR_A_D14 AT13 DDR_B_D14 AY2
AU13 SA_DQ[15] BA3 SB_DQ[15]
DDR_A_D16 BC7 DDR_B_D16 BE9
DDR_A_D17 SA_DQ[16] DDRA_SCS0# DDR_B_D17 SB_DQ[16] DDRB_SCS0#
BB7 SA_DQ[17] SA_CS#[0] BB40 DDRA_SCS0# <11> BD9 SB_DQ[17] SB_CS#[0] BE41 DDRB_SCS0# <12>
DDR_A_D18 BA13 BC41 DDRA_SCS1# DDR_B_D18 BD13 BE47 DDRB_SCS1#
SA_DQ[18] SA_CS#[1] DDRA_SCS1# <11> SB_DQ[18] SB_CS#[1] DDRB_SCS1# <12>
DDR_A_D19 BB11 DDR_B_D19 BF12
BA7 SA_DQ[20] BF8 SB_DQ[20]
DDR_A_D21 BA9 DDR_B_D21 BD10
BB9 SA_DQ[22] BD14 SB_DQ[22]
DDR_A_D23 AY13 DDR_B_D23 BE13
DDR_A_D24 SA_DQ[23] DDRA_ODT0 DDR_B_D24 SB_DQ[23] DDRB_ODT0
AV14 SA_DQ[24] SA_ODT[0] AY40 DDRA_ODT0 <11> BF16 SB_DQ[24] SB_ODT[0] AT43 DDRB_ODT0 <12>
DDR_A_D25 AR14 BA41 DDRA_ODT1 DDR_B_D25 BE17 BG47 DDRB_ODT1
SA_DQ[25] SA_ODT[1] DDRA_ODT1 <11> SB_DQ[25] SB_ODT[1] DDRB_ODT1 <12>
AR19 SA_DQ[27] BE21 SB_DQ[27]
DDR_A_D28 BA14 DDR_B_D28 BE14
AU14 SA_DQ[29] BG14 SB_DQ[29]
DDR_A_D30 BB14 DDR_B_D30 BG18
SA_DQ[30] DDR_A_DQS#[0..7] <11> SB_DQ[30] DDR_B_DQS#[0..7] <12>
DDR_A_D31 BB17 AL11 DDR_A_DQS#0 DDR_B_D31 BF19 AL3 DDR_B_DQS#0
DDR_A_D32 SA_DQ[31] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D32 SB_DQ[31] SB_DQS#[0]
BA45 SA_DQ[32] SA_DQS#[1] AR8 BD50 SB_DQ[32] SB_DQS#[1] AV3 DDR_B_DQS#1
DDR_A_D33 AR43 AV11 DDR_A_DQS#2 DDR_B_D33 BF48 BG11 DDR_B_DQS#2
AW48 SA_DQ[34] SA_DQS#[3] AT17 BD53 SB_DQ[34] SB_DQS#[3] BD17 DDR_B_DQS#3
DDR_A_D35 BC48 AV45 DDR_A_DQS#4 DDR_B_D35 BF52 BG51 DDR_B_DQS#4
BC45 SA_DQ[36] SA_DQS#[5] AY51 BD49 SB_DQ[36] SB_DQS#[5] BA59 DDR_B_DQS#5
DDR_A_D37 AR45 AT55 DDR_A_DQS#6 DDR_B_D37 BE49 AT60 DDR_B_DQS#6
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY B

AT48 SA_DQ[38] SA_DQS#[7] AK55 BD54 SB_DQ[38] SB_DQS#[7] AK59 DDR_B_DQS#7
2 DDR_A_D40 SA_DQ[39] DDR_B_D40 SB_DQ[39] 2
BA49 SA_DQ[40] BF56 SB_DQ[40]
DDR_A_D41 AV49 DDR_B_D41 BE57
BB51 SA_DQ[42] BC59 SB_DQ[42]
DDR_A_D43 AY53 DDR_B_D43 AY60
BB49 SA_DQ[44] DDR_A_DQS[0..7] <11> BE54 SB_DQ[44]
DDR_A_D45 AU49 AJ11 DDR_A_DQS0 DDR_B_D45 BG54
SA_DQ[45] SA_DQS[0] SB_DQ[45] DDR_B_DQS[0..7] <12>
DDR_A_D46 BA53 AR10 DDR_A_DQS1 DDR_B_D46 BA58 AM2 DDR_B_DQS0
DDR_A_D47 SA_DQ[46] SA_DQS[1] DDR_A_DQS2 DDR_B_D47 SB_DQ[46] SB_DQS[0] DDR_B_DQS1
BB55 SA_DQ[47] SA_DQS[2] AY11 AW59 SB_DQ[47] SB_DQS[1] AV1
DDR_A_D48 BA55 AU17 DDR_A_DQS3 DDR_B_D48 AW58 BE11 DDR_B_DQS2
AV56 SA_DQ[49] SA_DQS[4] AW45 AU58 SB_DQ[49] SB_DQS[3] BD18
DDR_A_D50 AP50 AV51 DDR_A_DQS5 DDR_B_D50 AN61 BE51 DDR_B_DQS4
AP53 SA_DQ[51] SA_DQS[6] AT56 AN59 SB_DQ[51] SB_DQS[5] BA61
DDR_A_D52 AV54 AK54 DDR_A_DQS7 DDR_B_D52 AU59 AR59 DDR_B_DQS6
DDR_A_D53 SA_DQ[52] SA_DQS[7] DDR_B_D53 SB_DQ[52] SB_DQS[6] DDR_B_DQS7
AT54 SA_DQ[53] AU61 SB_DQ[53] SB_DQS[7] AK61
DDR_A_D54 AP56 DDR_B_D54 AN58
AP52 SA_DQ[55] AR58 SB_DQ[55]
DDR_A_D56 AN57 DDR_B_D56 AK58
AN53 SA_DQ[57] AL58 SB_DQ[57]
DDR_A_D58 AG56 DDR_B_D58 AG58
AG53 SA_DQ[59] DDR_A_MA[0..15] <11> AG59 SB_DQ[59]
DDR_A_D60 AN55 DDR_B_D60 AM60
SA_DQ[60] SB_DQ[60] DDR_B_MA[0..15] <12>
DDR_A_D61 AN52 BG35 DDR_A_MA0 DDR_B_D61 AL59 BF32 DDR_B_MA0
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AG55 SA_DQ[62] SA_MA[1] BB34 AF61 SB_DQ[62] SB_MA[1] BE33
DDR_A_D63 AK56 BE35 DDR_A_MA2 DDR_B_D63 AH60 BD33 DDR_B_MA2
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_DQ[63] SB_MA[2] DDR_B_MA3
SA_MA[3] BD35 SB_MA[3] AU30
AT34 DDR_A_MA4 BD30 DDR_B_MA4
SA_MA[4] DDR_A_MA5 SB_MA[4] DDR_B_MA5
SA_MA[5] AU34 SB_MA[5] AV30
BB32 DDR_A_MA6 BG30 DDR_B_MA6
DDR_A_BS0 SA_MA[6] DDR_A_MA7 DDR_B_BS0 SB_MA[6] DDR_B_MA7
<11> DDR_A_BS0 BD37 SA_BS[0] SA_MA[7] AT32 <12> DDR_B_BS0 BG39 SB_BS[0] SB_MA[7] BD29
DDR_A_BS1 BF36 AY32 DDR_A_MA8 DDR_B_BS1 BD42 BE30 DDR_B_MA8
<11> DDR_A_BS1 SA_BS[1] SA_MA[8] <12> DDR_B_BS1 SB_BS[1] SB_MA[8]
DDR_A_BS2 BA28 AV32 DDR_A_MA9 DDR_B_BS2 AT22 BE28 DDR_B_MA9
<11> DDR_A_BS2 SA_BS[2] SA_MA[9] <12> DDR_B_BS2 SB_BS[2] SB_MA[9]
BE37 DDR_A_MA10 BD43 DDR_B_MA10
3 SA_MA[10] DDR_A_MA11 SB_MA[10] DDR_B_MA11 3
SA_MA[11] BA30 SB_MA[11] AT28
BC30 DDR_A_MA12 AV28 DDR_B_MA12
DDR_A_CAS# SA_MA[12] DDR_A_MA13 DDR_B_CAS# SB_MA[12] DDR_B_MA13
<11> DDR_A_CAS# BE39 SA_CAS# SA_MA[13] AW41 <12> DDR_B_CAS# AV43 SB_CAS# SB_MA[13] BD46
DDR_A_RAS# BD39 AY28 DDR_A_MA14 DDR_B_RAS# BF40 AT26 DDR_B_MA14
<11> DDR_A_RAS# SA_RAS# SA_MA[14] <12> DDR_B_RAS# SB_RAS# SB_MA[14]
DDR_A_WE# AT41 AU26 DDR_A_MA15 DDR_B_WE# BD45 AU22 DDR_B_MA15
<11> DDR_A_WE# SA_WE# SA_MA[15] <12> DDR_B_WE# SB_WE# SB_MA[15]
IVY-BRIDGE_BGA1023 <BOM> IVY-BRIDGE_BGA1023 <BOM>
+1.5V
RC75
1
0_0402_5%
1 2 RC76
@ 1K_0402_5%
RC77
2
QC3 1K_0402_5%
S
<5> H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2 SM_DRAMRST# <11,12>

2
BSS138_NL_SOT23-3 1
RC78 CC35
G
2
4.99K_0402_1% 180P_0402_50V8J
2
1
4 4
<11,25> DRAMRST_CNTRL_PCH 1 @ 2 DRAMRST_CNTRL Request by ESD

RC73 0_0402_5%
<40> EC_DRAMRST_CNTRL_PCH 1 @ 2
RC3 0_0402_5%
1
CC37 Security Classification Compal Secret Data Compal Electronics, Inc.
0.047U_0402_25V6K 2012/04/19 2015/04/19 Title
Issued Date Deciphered Date
2
Ivy Bridge_DDR3
Custom 1.0
VCUAA
A B C D E
A B C D E
+CPU_CORE UC1F POWER +1.05VS_VCCP
33A 8.5A
VCCIO[1] AF46
VCCIO[3] AG48
VCCIO[4] AG50
A26 VCC[1] VCCIO[5] AG51
A29 VCC[2] VCCIO[6] AJ17
1 1
A39 VCC[7] VCCIO[11] AK50
A42 VCC[8] VCCIO[12] AK51
C26 VCC[9] VCCIO[13] AL14 For DDR
C27 VCC[10] VCCIO[14] AL15
D27 VCC[16] VCCIO[20] AL48
D32 VCC[17] VCCIO[21] AM16
D39 AM43
PEG IO AND DDR IO

VCC[20] VCCIO[24]
E26 VCC[22] VCCIO[26] AN20
E37 VCC[26]
E38 VCC[27]
CORE SUPPLY
F25 VCC[28]
F26 VCC[29]
F28 VCC[30]
F32 VCC[31]
F34 VCC[32]
F37 VCC[33] VCCIO[30] AA14
F38 VCC[34] VCCIO[31] AA15
F42 VCC[35] VCCIO[32] AB17
G42 VCC[36] VCCIO[33] AB20
2 2
H25 VCC[37] VCCIO[34] AC13
H26 VCC[38] VCCIO[35] AD16
H32 VCC[41] VCCIO[38] AE14 For PEG
H34 VCC[42] VCCIO[39] AE15
H35 VCC[43] VCCIO[40] AF16
H40 VCC[46] VCCIO[43] AG15
J25 VCC[47] VCCIO[44] AG16
J32 VCC[51] VCCIO[48] AJ14
J34 VCC[52] VCCIO[49] AJ15
J35 VCC[53]
J37 VCC[54]
J38 +1.05VS_VCCP
VCC[55]
J40 VCC[56]
J42 VCC[57]
K26 VCC[58] VCCIO50 W16
K27 VCC[59] VCCIO51 W17
K29 VCC[60]
K32 VCC[61]
K34 VCC[62]
K35 VCC[63]
K37 VCC[64] 1mA
K39 VCC[66]
K42 VCC[67] VCCIO_SEL BC22
L25 VCC[68]
L28 VCC[69]
3 3
L33 VCC[70]
L36 +1.05VS_VCCP Reserve 0.1u to avoid noise
VCC[71]
L40 VCC[72] +1.05VS_VCCP +1.05VS_VCCP
N26 VCC[73] 0.1U_0402_10V7K 0.1U_0402_10V7K
RAILS
QUIET
N30 VCC[74] VCCPQE[1] AM25

N34 VCC[75] VCCPQE[2] AN22 1 2 1 2
N38 1 CC50 CC49
VCC[76] CC71 @ @
1
1
1U_0402_6.3V6K
RC91 RC89
2 130_0402_5% 75_0402_5%
2
2
A44 H_CPU_SVIDALRT# 1 2
VIDALERT# VR_SVID_ALRT# <49>
B43 H_CPU_SVIDCLK RC90 1 @ 2 43_0402_1%
VIDSCLK VR_SVID_CLK <49>
SVID
C44 H_CPU_SVIDDAT RC88 1 @ 2 0_0402_5%

VIDSOUT VR_SVID_DAT <49>
RC92 0_0402_5%
+CPU_CORE
Pull high resistor on VR side
2
RC93
100_0402_1%
1
VCC_SENSE F43 VCCSENSE_R RC94 1 @ 2 0_0402_5% VCCSENSE <49>

SENSE LINES
VSS_SENSE G43 VSSSENSE_R 1 @ 2 VSSSENSE <49>

RC95 0_0402_5%
1
VCCIO_SENSE
VCCIO_SENSE <47>
RC97
1
RC98 100_0402_1%
AN16 10_0402_1%
4 VCCIO_SENSE 4
AN17
2
VSS_SENSE_VCCIO
+1.05VS_VCCP Close to CPU

2
VCCIO_SENSE_VSS
VCCIO_SENSE_VSS <47>
1
RC96
10_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
Close to CPU Ivy Bridge_POWER-1

2
Custom 1.0
VCUAA
A B C D E
A B C D E
+GFX_CORE UC1G POWER +V_SM_VREF should

+1.5V_CPU
29A have 20 mil trace width RC120 1K_0402_0.5%

1 2
AY43 +V_SM_VREF
SM_VREF CC65
AA46 1 2
VREF
VAXG[1]
0.1U_0402_10V7K
AB47 1 RC109 1K_0402_0.5%
VAXG[2]
AB50 VAXG[3] SA_DIMM_VREFDQ BE7 +VREF_DQA_M3
AB51 VAXG[4] SB_DIMM_VREFDQ BG7 +VREF_DQB_M3
1 1
AB52 VAXG[5] 2
AB53 VAXG[6]
AB55 VAXG[7]
AB56
AB58
VAXG[8] 5A +1.5V_CPU Decoupling:
VAXG[9]
AB59 VAXG[10] 1X 330U (6m ohm), 6X 10U, 8X 1U
AC61 VAXG[11]
AD47 +1.5V_CPU
VAXG[12]
AD48 VAXG[13]
AD50 VAXG[14] Place TOP IN BGA
AD51 AJ28
- 1.5V RAILS
VAXG[15] VDDQ[1] CC57 CC51 CC52 CC55 CC54 CC56
AD52 VAXG[16] VDDQ[2] AJ33 1
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
AD53 VAXG[17] VDDQ[3] AJ36 1 1 1 1 1 1
AD55 AJ40 + CC53
VAXG[18] VDDQ[4] @
AD56 VAXG[19] VDDQ[5] AL30
AD58 AL34 330U_D2_2VM_R6M
VAXG[20] VDDQ[6] 2 2 2 2 2 2 2
AD59 AL38 ESR 6mohm
VAXG[21] VDDQ[7]
AE46 VAXG[22] VDDQ[8] AL42
N45 VAXG[23] VDDQ[9] AM33
P47 VAXG[24] VDDQ[10] AM36
P48 VAXG[25] VDDQ[11] AM40
P50 VAXG[26] VDDQ[12] AN30
P53 AR26 Place BOT OUT BGA
DDR3
VAXG[29] VDDQ[15]
P55 AR28
GRAPHICS
VAXG[30] VDDQ[16]
P56 VAXG[31] VDDQ[17] AR30
P61 AR32 CC82 CC81 CC80 CC79 CC78 CC87 CC86 CC85 CC84 CC83
VAXG[32] VDDQ[18]
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
T48 VAXG[33] VDDQ[19] AR34 1 1 1 1 1 1 1 1 1 1
T58 VAXG[34] VDDQ[20] AR36
T59 VAXG[35] VDDQ[21] AR40
T61 AV41 @ @
2 VAXG[36] VDDQ[22] 2 2 2 2 2 2 2 2 2 2 2
U46 VAXG[37] VDDQ[23] AW26
V47 VAXG[38] VDDQ[24] BA40
V48 VAXG[39] VDDQ[25] BB28
V50 VAXG[40] VDDQ[26] BG33
V51 VAXG[41]
V52 VAXG[42]
V53 VAXG[43]
V55 VAXG[44]
V56 VAXG[45]
V58 VAXG[46]
V59
W50
VAXG[47] 1mA
VAXG[48]
W51 VAXG[49]
W52 VAXG[50]
W53 VAXG[51]
W55 VAXG[52]
+GFX_CORE W56 VAXG[53]
W61 VAXG[54]
Y48 VAXG[55] VCCSA_VID0 VCCSA_VID1 +VCCSA
Y61 VAXG[56]
1
RC105 0 0 0.90 V
100_0402_1% For Sandy Bridge
+1.5V_CPU
Close to CPU 0 1 0.80 V
2
QUIET RAILS
AM28
SENSE
LINES
VCC_AXG_SENSE VCCDQ[1]
<49> VCC_AXG_SENSE F45 VAXG_SENSE VCCDQ[2] AN26
VSS_AXG_SENSE G45 1 1 0 0.725 V
<49> VSS_AXG_SENSE VSSAXG_SENSE
RC106 CC72
1 2 1U_0402_6.3V6K
100_0402_1% 1 1 0.675 V
VCCPLL Decoupling: 2
3 3
1X 330U (6m ohm), 1X 10U, 2x1U 1.2A
1.8V RAIL
+1.8VS 1 @ 2 +1.8VS_VCCPLL BB3

RC119 0_0805_5% CC59 CC60 CC61 VCCPLL[1]
BC1 VCCPLL[2]
10U_0805_10V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 BC4 VCCPLL[3]
+1.5V_CPU +1.5V
2 2 2
VDDQ_SENSE BC43
BA43 CC46 1 2 0.1U_0402_10V7K
VSS_SENSE_VDDQ
SENSE LINES
+1.5V_CPU +1.5VS C464

+VCCSA L17
6A CC47 1 2 0.1U_0402_10V7K PJ1 @ 4.7U_0805_10V4Z
VCCSA[1]
Place TOP IN BGA L21 VCCSA[2] 2 2 1 1 1 2
N16 CC48 1 2 0.1U_0402_10V7K @
VCCSA[3] JUMP_43X118 C463
N20 VCCSA[4]
CC42 CC41 CC43 CC40 CC58 N22 CC45 1 2 0.1U_0402_10V7K +1.5V 1 2
1
SA RAIL
VCCSA[5]
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
CC44 1 1 1 1 1 P17 Vgs=10V,Id=14.5A,Rds=6mohm QC4 @

VCCSA[6]
330U_D2_2VM_R6M
+ P20 U10 1 8 1U_0402_6.3V6K

VCCSA[7] VCCSA_SENSE +VCCSA_SENSE <48> S D
R16 VCCSA[8] 2 S D 7 1 2
2
@ @ @ R18 1 @ 2 1 3 6 C469
2 2 2 2 2 2 VCCSA[9] RC111 0_0402_5% RC203 CC68 S D 4.7U_0805_10V4Z
R21 VCCSA[10] 4 G D 5
U15 470_0805_5% 10U_0805_10V6K
VCCSA VID
VCCSA[11] @ FDS6676AS_SO8 RC204

V16 VCCSA[12] H_VCCSA_VID0 2 RUN_ON_CPU1.5VS3
V17 D48 H_VCCSA_VID0 <48> 1 2 +VSB
3 1
VCCSA[13] VCCSA_VID[0]
lines
Place BOT OUT BGA V18 D49 H_VCCSA_VID1 220K_0402_5%

VCCSA[14] VCCSA_VID[1] H_VCCSA_VID1 <48>
V21 VCCSA[15]
6
W20 Please kindly check whether 2N7002KDWH_SOT363-6 1
CC77 CC76 CC75 CC74 CC73 VCCSA[16] QC5B CC69 RC205 QC5A
there is pull-down resister
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 in PWR-side or HW-side SUSP 5 0.1U_0402_25V6 820K_0402_5%

2 SUSP
2 SUSP <34,42,5>
2
1
4 2 2 2 2 2 2N7002KDWH_SOT363-6 4
+VCCSA Decoupling:
1X 330U (6m ohm), 3X 10U, 5X 1U
Ivy Bridge_POWER-2
Custom 1.0
VCUAA
A B C D E
A B C D E
UC1H
UC1I
CFG Straps for Processor
UC1E (CFG[17:0] internal pull high 5~15K to VCCIO)
A13 VSS[1] VSS[91] AM38 BG17 VSS[181] VSS[250] M4
A17 AM4 BG21 M58 CFG2
VSS[2] VSS[92] VSS[182] VSS[251] CFG0
A21 VSS[3] VSS[93] AM42 BG24 VSS[183] VSS[252] M6 B50 CFG[0] BCLK_ITP N59
1
A25 AM45 BG28 N1 @ T89 PAD C51 N58
VSS[4] VSS[94] VSS[184] VSS[253] CFG2 CFG[1] BCLK_ITP# RC79
A28 VSS[5] VSS[95] AM48 BG37 VSS[185] VSS[254] N17 B54 CFG[2]
A33 AM58 BG41 N21 D53 1K_0402_1%
VSS[6] VSS[96] VSS[186] VSS[255] CFG4 CFG[3] OPT@
A37 VSS[7] VSS[97] AN1 BG45 VSS[187] VSS[256] N25 A51 CFG[4] RSVD30 N42
A40 AN21 BG49 N28 CFG5 C53 L42
2
VSS[8] VSS[98] VSS[188] VSS[257] CFG6 CFG[5] RSVD31
A45 VSS[9] VSS[99] AN25 BG53 VSS[189] VSS[258] N33 C55 CFG[6] RSVD32 L45
A49 AN28 BG9 N36 CFG7 H49 L47
1 VSS[10] VSS[100] VSS[190] VSS[259] CFG[7] RSVD33 1
A53 VSS[11] VSS[101] AN33 C29 VSS[191] VSS[260] N40 A55 CFG[8]
A9 VSS[12] VSS[102] AN36 C35 VSS[192] VSS[261] N43 H51 CFG[9]
AA1 VSS[13] VSS[103] AN40 C40 VSS[193] VSS[262] N47 K49 CFG[10] RSVD34 M13 PEG Static Lane Reversal - CFG2 is for the 16x
AA13 VSS[14] VSS[104] AN43 D10 VSS[194] VSS[263] N48 K53 CFG[11] RSVD35 M14
AA50 VSS[15] VSS[105] AN47 D14 VSS[195] VSS[264] N51 F53 CFG[12] RSVD36 U14
AA51 VSS[16] VSS[106] AN50 D18 VSS[196] VSS[265] N52 G53 CFG[13] RSVD37 W14 1: Normal Operation; Lane # definition
AA52 AN54 D22 N56 L51 P13
AA53
VSS[17] VSS[107]
AP10 D26
VSS[197] VSS[266]
N61 F51
CFG[14] RSVD38
CFG2 matches socket pin map definition
VSS[18] VSS[108] VSS[198] VSS[267] CFG[15]
AA55 VSS[19] VSS[109] AP51 D29 VSS[199] VSS[268] P14 D52 CFG[16]
AA56 AP55 D35 P16 L53 AT49 0:Lane Reversed
AA8
AB16
VSS[20]
VSS[21]
VSS[22]
VSS[110]
VSS[111]
VSS[112]
AP7
AR13
D4
D40
VSS[200]
VSS[201]
VSS[202]
VSS[269]
VSS[270]
VSS[271]
P18
P21
CFG[17] RSVD39
RSVD40 K24 *
RESERVED
AB18 AR17 D43 P58 H43 CFG4
AB21
VSS[23]
VSS[24]
VSS[113]
VSS[114] AR21 D46
VSS[203]
VSS[204] VSS VSS[272]
VSS[273] P59 K43
VCC_VAL_SENSE
VSS_VAL_SENSE RSVD41 AH2
1
AB48 VSS[25] VSS[115] AR41 D50 VSS[205] VSS[274] P9 RSVD42 AG13
AB61 AR48 D54 R17 AM14 RC82
VSS[26] VSS[116] VSS[206] VSS[275] RSVD43 1K_0402_1%
AC10 VSS[27] VSS[117] AR61 D58 VSS[207] VSS[276] R20 H45 VAXG_VAL_SENSE RSVD44 AM15
AC14 AR7 D6 R4 K45 @
VSS[28] VSS[118] VSS[208] VSS[277] VSSAXG_VAL_SENSE
AC46 AT14 E25 R46
2
VSS[29] VSS[119] VSS[209] VSS[278]
AC6 VSS[30] VSS[120] AT19 E29 VSS[210] VSS[279] T1 N50
AD17 VSS[31] VSS[121] AT36 E3 VSS[211] VSS[280] T47 @ F48 VCC_DIE_SENSE These RSVD45
pins are for solder joint
AD20 AT4 E35 T50
AD4
VSS[32] VSS[122]
AT45 E40
VSS[212] VSS[281]
T51 PAD T87 reliability and non-critical to
AD61
AE13
VSS[33]
VSS[34]
VSS[35]
VSS VSS[123]
VSS[124]
VSS[125]
AT52
AT58
F13
F15
VSS[213]
VSS[214]
VSS[215]
VSS[282]
VSS[283]
VSS[284]
T52
T53
H48
K48
RSVD6
RSVD7
function. For BGA only. Embedded Display Port Presence Strap
AE8 VSS[36] VSS[126] AU1 F19 VSS[216] VSS[285] T55 DC_TEST_A4 A4
AF1 AU11 F29 T56 C4 1 : Disabled; No Physical Display Port
AF17
AF21
VSS[37]
VSS[38]
VSS[39]
VSS[127]
VSS[128]
VSS[129]
AU28
AU32
F35
F40
VSS[217]
VSS[218]
VSS[219]
VSS[286]
VSS[287]
VSS[288]
U13
U8
BA19
AV19
RSVD8
RSVD9
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
D3
D1
DC_TEST_C4_D3
* attached to Embedded Display Port
AF47 VSS[40] VSS[130] AU51 F55 VSS[220] VSS[289] V20 AT21 RSVD10 DC_TEST_A58 A58 CFG4
AF48 VSS[41] VSS[131] AU7 G51 VSS[221] VSS[290] V61 BB21 RSVD11 DC_TEST_A59 A59 0 : Enabled; An external Display Port
AF50 AV17 G6 W13 BB19 C59 DC_TEST_A59_C59
2
AF51
VSS[42] VSS[132]
AV21 G61
VSS[222] VSS[291]
W15 AY21
RSVD12 DC_TEST_C59
A61
device is connected to the Embedded 2
VSS[43] VSS[133] VSS[223] VSS[292] RSVD13 DC_TEST_A61
AF52 VSS[44] VSS[134] AV22 H10 VSS[224] VSS[293] W18 BA22 RSVD14 DC_TEST_C61 C61 DC_TEST_A61_C61 Display Port
AF53 VSS[45] VSS[135] AV34 H14 VSS[225] VSS[294] W21 AY22 RSVD15 DC_TEST_D61 D61
AF55 VSS[46] VSS[136] AV40 H17 VSS[226] VSS[295] W46 AU19 RSVD16 DC_TEST_BD61 BD61
AF56 VSS[47] VSS[137] AV48 H21 VSS[227] VSS[296] W8 AU21 RSVD17 DC_TEST_BE61 BE61
AF58 VSS[48] VSS[138] AV55 H4 VSS[228] VSS[297] Y4 BD21 RSVD18 DC_TEST_BE59 BE59 DC_TEST_BE61_BE59
AF59 VSS[49] VSS[139] AW13 H53 VSS[229] VSS[298] Y47 BD22 RSVD19 DC_TEST_BG61 BG61
AG10 VSS[50] VSS[140] AW43 H58 VSS[230] VSS[299] Y58 BD25 RSVD20 DC_TEST_BG59 BG59 DC_TEST_BG61_BG59
AG14 VSS[51] VSS[141] AW61 J1 VSS[231] VSS[300] Y59 BD26 RSVD21 DC_TEST_BG58 BG58
AG18 VSS[52] VSS[142] AW7 J49 VSS[232] VSS[301] G48 BG22 RSVD22 DC_TEST_BG4 BG4
AG47 VSS[53] VSS[143] AY14 J55 VSS[233] BE22 RSVD23 DC_TEST_BG3 BG3
AG52 VSS[54] VSS[144] AY19 K11 VSS[234] BG26 RSVD24 DC_TEST_BE3 BE3 DC_TEST_BG3_BE3
AG61 VSS[55] VSS[145] AY30 K21 VSS[235] BE26 RSVD25 DC_TEST_BG1 BG1
AG7 VSS[56] VSS[146] AY36 K51 VSS[236] BF23 RSVD26 DC_TEST_BE1 BE1 DC_TEST_BG1_BE1
AH4 VSS[57] VSS[147] AY4 K8 VSS[237] VSS_NCTF_1 A5 BE24 RSVD27 DC_TEST_BD1 BD1
AH58 VSS[58] VSS[148] AY41 L16 VSS[238] VSS_NCTF_2 A57
AJ13 AY45 L20 BC61 CFG7
VSS[59] VSS[149] VSS[239] VSS_NCTF_3
AJ16 VSS[60] VSS[150] AY49 L22 VSS[240] VSS_NCTF_4 BD3
1
AJ20 VSS[61] VSS[151] AY55 L26 VSS[241] VSS_NCTF_5 BD59
AJ22 AY58 L30 BE4 IVY-BRIDGE_BGA1023 <BOM> RC85
NCTF
VSS[62] VSS[152] VSS[242] VSS_NCTF_6 1K_0402_1%

AJ26 VSS[63] VSS[153] AY9 L34 VSS[243] VSS_NCTF_7 BE58
AJ30 BA1 L38 BG5 @
AJ34 BA11 L43 BG57
2
AJ38 VSS[66] VSS[156] BA17 L48 VSS[246] VSS_NCTF_10 C3
AJ42 VSS[67] VSS[157] BA21 L61 VSS[247] VSS_NCTF_11 C58
AJ45 VSS[68] VSS[158] BA26 M11 VSS[248] VSS_NCTF_12 D59
AJ48 VSS[69] VSS[159] BA32 M15 VSS[249] VSS_NCTF_13 E1
AJ7 VSS[70] VSS[160] BA48 VSS_NCTF_14 E61 PEG DEFER TRAINING
AK1 VSS[71] VSS[161] BA51
AK52 VSS[72] VSS[162] BB53
AL10 BC13 1: (Default) PEG Train immediately
3
AL13
AL17
VSS[73]
VSS[74]
VSS[75]
VSS[163]
VSS[164]
VSS[165]
BC5
BC57 CFG7
* following xxRESETB de assertion 3
AL21 BD12 IVY-BRIDGE_BGA1023 <BOM>
VSS[76] VSS[166]
AL25 VSS[77] VSS[167] BD16 0: PEG Wait for BIOS for training
AL28 VSS[78] VSS[168] BD19
AL33 VSS[79] VSS[169] BD23
AL36 BD27 CFG6
VSS[80] VSS[170]
AL40 VSS[81] VSS[171] BD32
AL43 BD36 CFG5
VSS[82] VSS[172]
AL47 VSS[83] VSS[173] BD40
1
AL61 VSS[84] VSS[174] BD44
AM13 BD48 RC83 RC84
VSS[85] VSS[175] 1K_0402_1% 1K_0402_1%
AM20 VSS[86] VSS[176] BD52
AM22 BD56 @ @
VSS[87] VSS[177]
AM26 BD8
2
VSS[88] VSS[178]
AM30 VSS[89] VSS[179] BE5
AM34 VSS[90] VSS[180] BG13
PCIE Port Bifurcation Straps
IVY-BRIDGE_BGA1023 <BOM> 11: (Default) x16 - Device 1 functions 1 and 2

* disabled
CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled;

function 2 disabled
01: Reserved - (Device 1 function 1 disabled;
function 2 enabled)
4 4
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

Ivy Bridge_GND/RSVD/CFG
Custom 1.0
VCUAA
A B C D E
A B C D E
+1.5V +1.5V
JDDR3R DDR3 SO-DIMM A
1 2
+VREF_DQA
DDR_A_D0
3
VREF_DQ
VSS
VSS
DQ4 4 DDR_A_D4
DDR_A_D5
Reverse Type DDR_A_DQS[0..7] <7>
5 DQ0 DQ5 6 DDR_A_DQS#[0..7] <7>
1 1 DDR_A_D1 7 8
CD1 CD2 DQ1 VSS DDR_A_DQS#0
9 VSS DQS0# 10 DDR_A_D[0..63] <7>
11 12 DDR_A_DQS0
DM0 DQS0
0.1U_0402_10V7K
2.2U_0402_6.3V6M
13 VSS VSS 14 DDR_A_MA[0..15] <7>
2 2 DDR_A_D2 DDR_A_D6
15 DQ2 DQ6 16
DDR_A_D3 17 18 DDR_A_D7
19
DQ3
VSS
DQ7
VSS 20 Intel DDR Vref M3 +1.5V
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 DQ9 DQ13 24
25 26 2 @ 1
VSS VSS
1
1 DDR_A_DQS#1 0_0402_5% 1
27 DQS1# DM1 28
Close to JDDR3R.1 DDR_A_DQS1 29 30 SM_DRAMRST# RC115 RD1
DQS1 RESET# SM_DRAMRST# <12,7>
31 32 1K_0402_1%
DDR_A_D10 VSS VSS DDR_A_D14 BSS138_NL_SOT23-3
33 DQ10 DQ14 34
DDR_A_D11 35 36 DDR_A_D15 QC7
2
DQ11 DQ15
D
37 VSS VSS 38 +VREF_DQA_M3 3 1 +VREF_DQA +VREF_DQA
DQ16 DQ20
1
DQ17 DQ21 @ RD2
G
43 44 1 2
2
DDR_A_DQS#2 VSS VSS RC117 1K_0402_1% 1K_0402_1%
45 DQS2# DM2 46
DDR_A_DQS2 47 48
DQS2 VSS DDR_A_D22
49 50 DRAMRST_CNTRL_PCH <25,7>
2
DDR_A_D18 VSS DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54 1 @ 2
DQ19 VSS
2
G
55 56 DDR_A_D28 RC118 1K_0402_1%
57 DQ24 DQ29 58
DDR_A_D25 59 60 +VREF_DQB_M3 3 1 +VREF_DQB
DQ25 VSS DDR_A_DQS#3
D
61 VSS DQS3# 62
63 64 DDR_A_DQS3 QC8
DM3 DQS3 BSS138_NL_SOT23-3
65 VSS VSS 66
DDR_A_D27 DQ26 DQ30 DDR_A_D31 @ 1 +1.5V
69 DQ27 DQ31 70 2
71 72 0_0402_5%
VSS VSS RC116
1
DDRA_CKE0 73 74 DDRA_CKE1 RD10
<7> DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 <7>
75 76 1K_0402_1%
VDD VDD DDR_A_MA15
77 NC A15 78
DDR_A_BS2 79 80 DDR_A_MA14
<7> DDR_A_BS2
2
BA2 A14
81 VDD VDD 82
DDR_A_MA12 83 84 DDR_A_MA11 +VREF_DQB
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
2 2
87 VDD VDD 88
1
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4 RD11
91 A5 A4 92
93 94 1K_0402_1%
DDR_A_MA3 VDD VDD DDR_A_MA2
95 A3 A2 96
DDR_A_MA1 97 98 DDR_A_MA0
2
A1 A0
99 VDD VDD 100
DDRA_CLK0 DDRA_CLK1 +1.5V
<7> DDRA_CLK0 101 CK0 CK1 102 DDRA_CLK1 <7>
DDRA_CLK0# 103 104 DDRA_CLK1#
<7> DDRA_CLK0# CK0# CK1# DDRA_CLK1# <7>
105 VDD VDD 106 1 2
DDR_A_MA10 DDR_A_BS1 +1.5V CD50 33P_0402_50V8K
107 A10/AP BA1 108 DDR_A_BS1 <7>
DDR_A_BS0 109 110 DDR_A_RAS#
<7> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <7>
111 VDD VDD 112 1 2
1
DDR_A_WE# 113 114 DDRA_SCS0# CD51 33P_0402_50V8K
<7> DDR_A_WE# WE# S0# DDRA_SCS0# <7>
DDR_A_CAS# 115 116 DDRA_ODT0 RD6
<7> DDR_A_CAS# CAS# ODT0 DDRA_ODT0 <7>
117 118 1K_0402_1% 1 2
DDR_A_MA13 VDD VDD DDRA_ODT1 CD52 33P_0402_50V8K
119 A13 ODT1 120 DDRA_ODT1 <7>
DDRA_SCS1# 121 122
2
<7> DDRA_SCS1# S1# NC
123 VDD VDD 124 1 2
125 126 +VREF_CAA CD53 33P_0402_50V8K
TEST VREF_CA
127 VSS VSS 128
1
DDR_A_D32 129 130 DDR_A_D36 1 2
DDR_A_D33 DQ32 DQ36 DDR_A_D37 RD7 CD54 33P_0402_50V8K
131 DQ33 DQ37 132
133 134 1K_0402_1%
DDR_A_DQS#4 VSS VSS
135 DQS4# DM4 136 1 2
DDR_A_DQS4 137 138 1 1 CD55 33P_0402_50V8K
2
DQS4 VSS DDR_A_D38 CD15 CD16
139 VSS DQ38 140
DDR_A_D34 141 142 DDR_A_D39 please place these caps near the
DQ34 DQ39
2.2U_0402_6.3V6M
0.1U_0402_10V7K
DDR_A_D35 143 144

145
DQ35 VSS
146 DDR_A_D44 2 2 reference power plane of CMD/AD
147 DQ40 DQ45 148
DDR_A_D41 149 150
3 DQ41 VSS DDR_A_DQS#5 3
151 VSS DQS5# 152
153 154 DDR_A_DQS5
DM5 DQS5
155 VSS VSS 156
DDR_A_D42 157 158 DDR_A_D46
159 DQ43 DQ47 160 close to JDDR3R.126
161 VSS VSS 162
DDR_A_D48 163 164 DDR_A_D52 Layout Note: Layout Note: Place these 4 Caps near Layout Note:
165 DQ49 DQ53 166
167 168 Place near JDDRH Command and Control signals of DIMMA Place near JDDRH.203 and 204
DDR_A_DQS#6 VSS VSS
169 DQS6# DM6 170
DDR_A_DQS6 171 172
DQS6 VSS DDR_A_D54
173 VSS DQ54 174
DDR_A_D50 175 176 DDR_A_D55 +1.5V
DDR_A_D51 DQ50 DQ55 @ +1.5V +0.75VS
177 DQ51 VSS 178
179 180 DDR_A_D60 1 2
DDR_A_D56 VSS DQ60 DDR_A_D61 CD3 330U_D2_2VM_R6M
181 182
+
DDR_A_D57 DQ56 DQ61 CD20 1
183 DQ57 VSS 184 2 0.1U_0402_10V7K CD56 1 2 10U_0603_6.3V6M
185 186 DDR_A_DQS#7 CD8 1 2 10U_0603_6.3V6M
VSS DQS7# DDR_A_DQS7 CD17 1
187 DM7 DQS7 188 2 0.1U_0402_10V7K
189 190 CD9 1 2 10U_0603_6.3V6M CD24 2 1 1U_0402_6.3V6K
DDR_A_D58 VSS VSS DDR_A_D62 CD18 1
191 DQ58 DQ62 192 2 0.1U_0402_10V7K
DDR_A_D59 193 194 DDR_A_D63 CD10 1 2 10U_0603_6.3V6M CD21 2 1 1U_0402_6.3V6K
RD8 1 DQ59 DQ63 CD19 1
2 195 VSS VSS 196 2 0.1U_0402_10V7K
10K_0402_5% 197 198 CD11 1 2 10U_0603_6.3V6M CD22 2 1 1U_0402_6.3V6K
SA0 EVENT# PM_SMBDATA
+3VS 199 VDDSPD SDA 200 PM_SMBDATA <12,25,34,41>
0.1U_0402_10V7K
2 1 201 202 PM_SMBCLK CD12 1 2 10U_0603_6.3V6M CD23 2 1 1U_0402_6.3V6K

SA1 SCL PM_SMBCLK <12,25,34,41>
1 1 RD9 +0.75VS 203 204 +0.75VS
CD25 CD26 10K_0402_5% VTT VTT CD13 1 2 10U_0603_6.3V6M
205 GND1 GND2 206
2.2U_0402_6.3V6M
@ 207 208
2 2 BOSS1 BOSS2
4 LCN_DAN06-K4406-0103 4
@
SPD setting (SA0, SA1)

PU/PD by Channel A/B
->Channel A 00
->Channel B 01 Security Classification Compal Secret Data Compal Electronics, Inc.
DDRIII-SODIMM0
Custom 1.0
VCUAA
A B C D E
A B C D E
+1.5V +1.5V
JDDR3S
1 2
+VREF_DQB
DDR_B_D0
3
VREF_DQ
VSS2
VSS1
DQ4 4 DDR_B_D4
DDR_B_D5
Standard Type
5 6
DDR_B_D1 7
DQ0
DQ1
DQ5
VSS3 8
DDR_B_DQS#0
DDR3 SO-DIMM B
9 VSS4 DQS#0 10
11 12 DDR_B_DQS0
DM0 DQS0
1 1 13 VSS5 VSS6 14
CD28 CD27 DDR_B_D2 15 16 DDR_B_D6 DDR_B_DQS#[0..7] <7>
DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
2.2U_0402_6.3V6M
0.1U_0402_10V7K
19 VSS7 VSS8 20 DDR_B_DQS[0..7] <7>
2 2 DDR_B_D8 DDR_B_D12
21 DQ8 DQ12 22
DDR_B_D9 23 24 DDR_B_D13 DDR_B_D[0..63] <7>
DQ9 DQ13
25 VSS9 VSS10 26
1 DDR_B_DQS#1 1
27 DQS#1 DM1 28 DDR_B_MA[0..15] <7>
DDR_B_DQS1 29 30 SM_DRAMRST#
DQS1 RESET# SM_DRAMRST# <11,7>
31 VSS11 VSS12 32
DDR_B_D10 33 34 DDR_B_D14
Close to JDDR3S.1 35 DQ11 DQ15 36
37 VSS13 VSS14 38
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_B_DQS#2 45 46
DDR_B_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_B_D22
DDR_B_D18 VSS18 DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS19 DDR_B_D28
55 VSS20 DQ28 56
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_B_DQS#3
VSS22 DQS#3 DDR_B_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
69 DQ27 DQ31 70
71 VSS25 VSS26 72
DDRB_CKE0 73 74 DDRB_CKE1
<7> DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 <7>
75 VDD1 VDD2 76
77 78 DDR_B_MA15
DDR_B_BS2 NC1 A15 DDR_B_MA14
<7> DDR_B_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
2 DDR_B_MA9 A12/BC# A11 DDR_B_MA7 2
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD9 VDD10 100
DDRB_CLK0 101 102 DDRB_CLK1
<7> DDRB_CLK0 CK0 CK1 DDRB_CLK1 <7>
DDRB_CLK0# 103 104 DDRB_CLK1#
<7> DDRB_CLK0# CK0# CK1# DDRB_CLK1# <7> +1.5V
105 VDD11 VDD12 106
DDR_B_MA10 107 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <7>
DDR_B_BS0 109 110 DDR_B_RAS#
<7> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <7>
1
111 VDD13 VDD14 112
DDR_B_WE# 113 114 DDRB_SCS0# RD12
<7> DDR_B_WE# WE# S0# DDRB_SCS0# <7>
DDR_B_CAS# 115 116 DDRB_ODT0 1K_0402_1%
<7> DDR_B_CAS# CAS# ODT0 DDRB_ODT0 <7>
117 VDD15 VDD16 118
DDR_B_MA13 119 120 DDRB_ODT1
DDRB_ODT1 <7>
2
DDRB_SCS1# A13 ODT1
<7> DDRB_SCS1# 121 S1# NC2 122
123 VDD17 VDD18 124
125 126 +VREF_CAB
NCTEST VREF_CA
1
127 VSS27 VSS28 128
DDR_B_D32 129 130 DDR_B_D36 RD13
DDR_B_D33 DQ32 DQ36 DDR_B_D37 1K_0402_1%
131 DQ33 DQ37 132
133 VSS29 VSS30 134
DDR_B_DQS#4 135 136 1
2
DDR_B_DQS4 DQS#4 DM4 CD47
137 DQS4 VSS31 138 1
139 140 DDR_B_D38 CD46
VSS32 DQ38
0.1U_0402_10V7K
DDR_B_D34 141 142 DDR_B_D39

DQ34 DQ39 2
2.2U_0402_6.3V6M
DDR_B_D35 143 144

DQ35 VSS33 DDR_B_D44 2
145 VSS34 DQ44 146
DDR_B_D40 147 148 DDR_B_D45
3 DDR_B_D41 DQ40 DQ45 3
149 DQ41 VSS35 150
151 152 DDR_B_DQS#5
VSS36 DQS#5 DDR_B_DQS5
153 DM5 DQS5 154
155 VSS37 VSS38 156
DDR_B_D42 157 158 DDR_B_D46 Close to JDDR3S.126
159 DQ43 DQ47 160 Layout Note: Layout Note: Place these 4 Caps near Layout Note:
161 VSS39 VSS40 162
DDR_B_D48 163 164 DDR_B_D52 Place near JDDRL Command and Control signals of DIMMB Place near JDDRL.203 and 204
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_B_DQS#6 169 170 +1.5V
DDR_B_DQS6 DQS#6 DM6 +1.5V +0.75VS
171 DQS6 VSS43 172
173 174 DDR_B_D54 1 2
DDR_B_D50 VSS44 DQ54 DDR_B_D55 CD31 330U_D2_2VM_R6M
175 176
DDR_B_D51 177
DQ50 DQ55
178 + CD33 1 2 0.1U_0402_10V7K
DQ51 VSS45 DDR_B_D60 CD41 1
179 VSS46 DQ60 180 2 10U_0603_6.3V6M CD57 1 2 10U_0603_6.3V6M
DDR_B_D56 181 182 DDR_B_D61 CD29 1 2 0.1U_0402_10V7K
DDR_B_D57 DQ56 DQ61 CD36 1
183 DQ57 VSS47 184 2 10U_0603_6.3V6M CD45 2 1 1U_0402_6.3V6K
185 186 DDR_B_DQS#7 CD30 1 2 0.1U_0402_10V7K
VSS48 DQS#7 DDR_B_DQS7 CD37 1
187 DM7 DQS7 188 2 10U_0603_6.3V6M CD42 2 1 1U_0402_6.3V6K
189 190 CD32 1 2 0.1U_0402_10V7K
DDR_B_D58 VSS49 VSS50 DDR_B_D62 CD38 1
191 DQ58 DQ62 192 2 10U_0603_6.3V6M CD43 2 1 1U_0402_6.3V6K
DDR_B_D59 193 194 DDR_B_D63
RD14 1 DQ59 DQ63 CD39 1
2 195 VSS51 VSS52 196 2 10U_0603_6.3V6M CD44 2 1 1U_0402_6.3V6K
10K_0402_5% 197 198
SA0 EVENT# PM_SMBDATA CD40 1
+3VS 199 VDDSPD SDA 200 PM_SMBDATA <11,25,34,41> 2 10U_0603_6.3V6M
RD15 1 2 201 202 PM_SMBCLK
SA1 SCL PM_SMBCLK <11,25,34,41>
1 1 10K_0402_5% +0.75VS 203 204 +0.75VS
CD48 VTT1 VTT2
205 G1 G2 206
2.2U_0402_6.3V6M
CD49
2 2 LCN_DAN06-K4406-0102
4 0.1U_0402_10V7K @ 4
SPD setting (SA0, SA1)

PU/PD by Channel A/B
->Channel A 00
->Channel B 01
DDRIII-SODIMM1
Custom 1.0
VCUAA
A B C D E
A B C D E
PCIE_GTX_C_CRX_P[0..15]
<6> PCIE_GTX_C_CRX_P[0..15]
UV4A
+3VS_DGPU
PCIE_GTX_C_CRX_N[0..15]
PCIE_CTX_C_GRX_P15 AN12 Part 1 of 7 <6> PCIE_GTX_C_CRX_N[0..15]
PCIE_CTX_C_GRX_N15 PEX_RX0 VGA_VID_4
AM12 PEX_RX0_N GPIO0 P6 VGA_VID_4 <51>
PCIE_CTX_C_GRX_P14 AN14 M3 VGA_VID_3 PCIE_CTX_C_GRX_P[0..15]
PEX_RX1 GPIO1 VGA_VID_3 <51> <6> PCIE_CTX_C_GRX_P[0..15]
PCIE_CTX_C_GRX_N14 AM14 L6
PCIE_CTX_C_GRX_P13 PEX_RX1_N GPIO2
AP14 PEX_RX2 GPIO3 P5
PCIE_CTX_C_GRX_N13 AP15 P7 PCIE_CTX_C_GRX_N[0..15]
PCIE_CTX_C_GRX_P12 PEX_RX2_N GPIO4 VGA_VID_1 <6> PCIE_CTX_C_GRX_N[0..15]
AN15 PEX_RX3 GPIO5 L7 VGA_VID_1 <51>
PCIE_CTX_C_GRX_N12 AM15 M7 VGA_VID_2 VGA_EDID_CLK 1 OPT@ 2
PEX_RX3_N GPIO6 VGA_VID_2 <51>
PCIE_CTX_C_GRX_P11 AN17 N8 RV6 2.2K_0402_5%
PCIE_CTX_C_GRX_N11 PEX_RX4 GPIO7 OVERT#_VGA VGA_EDID_DATA
AM17 PEX_RX4_N GPIO8 M1 1 OPT@ 2
PCIE_CTX_C_GRX_P10 AP17 M2 GPU_EVENT RV7 2.2K_0402_5%
1 PCIE_CTX_C_GRX_N10 PEX_RX5 GPIO9 GPS_DOWN# OPT@ 2 1
AP18 PEX_RX5_N GPIO10 L1 1
PCIE_CTX_C_GRX_P9 AN18 M5 VGA_VID_0 RV32 10K_0402_5%
GPIO
PEX_RX6 GPIO11 VGA_VID_0 <51>
PCIE_CTX_C_GRX_N9 AM18 N3 GPS_DOWN# GPU_EVENT 1 OPT@ 2
PEX_RX6_N GPIO12 GPS_DOWN# <40>
PCIE_CTX_C_GRX_P8 AN20 M4 VGA_VID_5 RV10 10K_0402_5%
PEX_RX7 GPIO13 VGA_VID_5 <51> EC GPS_DOWN# must be OD\Low
PCIE_CTX_C_GRX_N8 AM20 N4 OVERT#_VGA 1 OPT@ 2
PCIE_CTX_C_GRX_P7 PEX_RX7_N GPIO14 RV37 10K_0402_5%
PCIE_CTX_C_GRX_N7
AP20 PEX_RX8 GPIO15 P2 to avoid leakage on OPT SKU. HDCP_SCL OPT@ 2
AP21 PEX_RX8_N GPIO16 R8 1
PCIE_CTX_C_GRX_P6 AN21 M6 RV11 2.2K_0402_5%
PCIE_CTX_C_GRX_N6 PEX_RX9 GPIO17 HDMI_HPD_VGA HDCP_SDA OPT@ 2
AM21 PEX_RX9_N GPIO18 R1 1
PCIE_CTX_C_GRX_P5 AN23 P3 RV12 2.2K_0402_5%
PCIE_CTX_C_GRX_N5 PEX_RX10 GPIO19
AM23 PEX_RX10_N GPIO20 P4
PCIE_CTX_C_GRX_P4 AP23 P1
PCIE_CTX_C_GRX_N4 PEX_RX11 GPIO21 VGA_CRT_DATA OPT@ 2
AP24 PEX_RX11_N 1
PCIE_CTX_C_GRX_P3 AN24 RV13 2.2K_0402_5%
PCIE_CTX_C_GRX_N3 PEX_RX12 VGA_CRT_CLK OPT@ 2
AM24 PEX_RX12_N 1
PCIE_CTX_C_GRX_P2 AN26 RV14 2.2K_0402_5%
PCIE_CTX_C_GRX_N2 PEX_RX13
AM26 PEX_RX13_N
PCIE_CTX_C_GRX_P1 AP26
PCIE_CTX_C_GRX_N1 PEX_RX14 HDMI_HPD_VGA
AP27 PEX_RX14_N 2 OPT@ 1
PCIE_CTX_C_GRX_P0 AN27 AK9 RV608 100K_0402_5%
PCIE_CTX_C_GRX_N0 PEX_RX15 DACA_RED
AM27 PEX_RX15_N DACA_GREEN AL10
DACA_BLUE AL9
DACs
PCIE_GTX_C_CRX_P15 OPT@ CV35 1 2 0.22U_0402_16V7K PCIE_GTX_CRX_P15 AK14
PCIE_GTX_C_CRX_N15 OPT@ CV37 1 0.22U_0402_16V7K PCIE_GTX_CRX_N15 PEX_TX0
2 AJ14 PEX_TX0_N DACA_HSYNC AM9
PCIE_GTX_C_CRX_P14 OPT@ CV39 1 2 0.22U_0402_16V7K PCIE_GTX_CRX_P14 AH14 AN9
PCIE_GTX_C_CRX_N14 OPT@ CV45 1 0.22U_0402_16V7K PCIE_GTX_CRX_N14 PEX_TX1 DACA_VSYNC
2 AG14 PEX_TX1_N
PCIE_GTX_C_CRX_P13 OPT@ CV93 1 2 0.22U_0402_16V7K PCIE_GTX_CRX_P13 AK15
2 AJ15 PEX_TX2_N 120mA DACA_VDD AG10
PCI EXPRESS
PCIE_GTX_C_CRX_P12 OPT@ CV94 1 2 0.22U_0402_16V7K PCIE_GTX_CRX_P12 AL16 AP9
PEX_TX3 DACA_VREF
1
PCIE_GTX_C_CRX_N12 OPT@ CV99 1 2 0.22U_0402_16V7K PCIE_GTX_CRX_N12 AK16 AP8
PCIE_GTX_C_CRX_P11 OPT@ CV107 1 0.22U_0402_16V7K PCIE_GTX_CRX_P11 PEX_TX3_N DACA_RSET CV225
2 AK17 PEX_TX4
2 PCIE_GTX_C_CRX_N11 OPT@ CV105 1 0.22U_0402_16V7K PCIE_GTX_CRX_N11 10K_0402_5% 2
2 AJ17 PEX_TX4_N
PCIE_GTX_C_CRX_P10 OPT@ CV199 1 2 0.22U_0402_16V7K PCIE_GTX_CRX_P10 AH17 OPT@
2 AG17
2
PCIE_GTX_C_CRX_P9 OPT@ CV200 1 0.22U_0402_16V7K PCIE_GTX_CRX_P9 PEX_TX5_N 110804 check with NV pull down 10k if DAC unused
2 AK18 PEX_TX6
PCIE_GTX_C_CRX_N9 OPT@ CV202 1 2 0.22U_0402_16V7K PCIE_GTX_CRX_N9 AJ18
PCIE_GTX_C_CRX_P8 OPT@ CV201 1 0.22U_0402_16V7K PCIE_GTX_CRX_P8 PEX_TX6_N
2 AL19 PEX_TX7
PCIE_GTX_C_CRX_N8 OPT@ CV204 1 2 0.22U_0402_16V7K PCIE_GTX_CRX_N8 AK19 R4 VGA_CRT_CLK
PCIE_GTX_C_CRX_P7 OPT@ CV203 1 0.22U_0402_16V7K PCIE_GTX_CRX_P7 PEX_TX7_N I2CA_SCL VGA_CRT_DATA
2 AK20 PEX_TX8 I2CA_SDA R5
PCIE_GTX_C_CRX_N7 OPT@ CV205 1 2 0.22U_0402_16V7K PCIE_GTX_CRX_N7 AJ20
PCIE_GTX_C_CRX_P6 OPT@ CV207 1 0.22U_0402_16V7K PCIE_GTX_CRX_P6 PEX_TX8_N HDCP_SCL
2 AH20 PEX_TX9 I2CB_SCL R7
PCIE_GTX_C_CRX_N6 OPT@ CV206 1 2 0.22U_0402_16V7K PCIE_GTX_CRX_N6 AG20 R6 HDCP_SDA +1.05VS_DGPU
PCIE_GTX_C_CRX_P5 OPT@ CV209 1 0.22U_0402_16V7K PCIE_GTX_CRX_P5 PEX_TX9_N I2CB_SDA LV10
I2C
2 AK21 PEX_TX10
PCIE_GTX_C_CRX_N5 OPT@ CV208 1 2 0.22U_0402_16V7K PCIE_GTX_CRX_N5 AJ21 R2 VGA_EDID_CLK +PLLVDD 1 2
PEX_TX10_N I2CC_SCL
22U_0805_6.3V6M
10U_0603_6.3V6M
CV47
CV197
CV109
4.7U_0402_6.3V6M
0.1U_0402_10V7K
PCIE_GTX_C_CRX_P4 OPT@ CV210 1 2 0.22U_0402_16V7K PCIE_GTX_CRX_P4 AL22 R3 VGA_EDID_DATA LVDS BLM18PG330SN1D_0603
PEX_TX11 I2CC_SDA
OPT@ CV53
PCIE_GTX_C_CRX_N4 OPT@ CV212 1 2 0.22U_0402_16V7K PCIE_GTX_CRX_N4 AK22 1 1 1 OPT@ 1
PCIE_GTX_C_CRX_P3 OPT@ CV211 1 0.22U_0402_16V7K PCIE_GTX_CRX_P3 PEX_TX11_N SMB_CLK_GPU
2 AK23 PEX_TX12 I2CS_SCL T4
PCIE_GTX_C_CRX_N3 OPT@ CV214 1 2 0.22U_0402_16V7K PCIE_GTX_CRX_N3 AJ23 T3 SMB_DATA_GPU
PCIE_GTX_C_CRX_P2 OPT@ CV213 1 0.22U_0402_16V7K PCIE_GTX_CRX_P2 PEX_TX12_N I2CS_SDA
2 AH23 PEX_TX13 Internal Thermal Sensor 2 2 2 2
OPT@
OPT@
OPT@
PCIE_GTX_C_CRX_N2 OPT@ CV215 1 2 0.22U_0402_16V7K PCIE_GTX_CRX_N2 AG23
2 AK24 PEX_TX14
PCIE_GTX_C_CRX_N1 OPT@ CV216 1 2 0.22U_0402_16V7K PCIE_GTX_CRX_N1 AJ24 CV1971 under GPU
2 AL25
PCIE_GTX_C_CRX_N0 OPT@ CV220 1 2 0.22U_0402_16V7K PCIE_GTX_CRX_N0 AK25
PEX_TX15 close to ball : ADB
PEX_TX15_N
60mA AD8 +PLLVDD
PLLVDD
AJ11 PEX_WAKE_N LV15 +1.05VS_DGPU
CLK_PCIE_VGA
45mA SP_PLLVDD AE8
BLM18PG181SN1D_2P
<25> CLK_PCIE_VGA AL13 PEX_REFCLK
<25> CLK_PCIE_VGA# CLK_PCIE_VGA# AK13 45mA AD7 +GPU_PLLVDD 1 2
PEX_REFCLK_N VID_PLLVDD
22U_0805_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
4.7U_0402_6.3V6M
CLK_REQ_GPU# OPT@
CLK
AK12 PEX_CLKREQ_N
CV38
CV40
CV41
CV42
CV43
OPT@ CV44
1 1 1 1 1 1
1 @ 2 PEX_TSTCLK_OUT AJ26 H3 XTALIN
3 RV16 200_0402_1% PEX_TSTCLK_OUT# PEX_TSTCLK_OUT XTAL_IN XTAL_OUT 3
AK26 PEX_TSTCLK_OUT_N XTAL_OUT H2
2 2 2 2 2 2
OPT@
OPT@
OPT@
OPT@
OPT@
<28> PLTRST_VGA# AJ12 J4 XTAL_OUTBUFF
PEX_RST_N XTAL_OUTBUFF XTAL_SSIN
AP29 H1
1
PEX_TERMP XTAL_SSIN
10K_0402_5%
1 OPT@ 2
10K_0402_5%
OPT@ RV45
1
OPT@ RV52
RV19 2.49K_0402_1%
CV38,CV40, CV41 under GPU

N13P-PES-A2_FCBGA908 N13PGLR1@
2
close to ball : AE8,AD7
2
1 2 XTALIN
<34> VGA_X1 +3VS_DGPU
RV5 0_0402_5%
OPT@
+3VS_DGPU
Close to VGA side
2
+3VS_DGPU
RV22 RV24
YV3 NOGCLK@ 2.2K_0402_5% 2.2K_0402_5%
OPT@ OPT@
5
XTALIN 1 3 XTAL_OUT OPT@
1 3
1
2
QV1B
GND GND SMB_CLK_GPU
<25> CLK_REQ_VGA# RV179 4 3 EC_SMB_CK2 <25,40>
10K_0402_5% 1 2 4 1
2
CV48 27MHZ_16PF_7V27000011 CV49 OPT@ 2N7002DW-T/R7_SOT363-6
OPT@ 18P_0402_50V8J 18P_0402_50V8J QV1A
1
NOGCLK@ NOGCLK@ SMB_DATA_GPU 1 6 EC_SMB_DA2 <25,40>

1
D QV3 RV182 0_0402_5% 2 2

CLK_REQ_GPU#
2 1 @ 2 +3VS_DGPU 2N7002DW-T/R7_SOT363-6
G 1
4 CV46 4
2N7002KW_SOT323-3 S OPT@ 0.1U_0402_10V7K
3

VGA_N13P PEG & DAC
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
A B C D E
A
VRAM Interface <19> MDA[15..0]
<19> MDA[31..16]
MDA[15..0]
MDA[31..16] <20> MDC[15..0]

MDC[15..0]
MDC[31..16]
MDA[47..32] <20> MDC[31..16]
<18> MDA[47..32] MDC[47..32]
MDA[63..48] <21> MDC[47..32]
<18> MDA[63..48] MDC[63..48]
<21> MDC[63..48]
UV4B UV4C
CMDA[30..0] <18,19> CMDC[30..0] <20,21>
Part 2 of 7 Part 3 of 7
MDA0 L28 U30 CMDA0 MDC0 G9 D13 CMDC0
MDA1 FBA_D0 FBA_CMD0 CMDA1 MDC1 FBB_D0 FBB_CMD0 CMDC1
M29 FBA_D1 FBA_CMD1 T31 E9 FBB_D1 FBB_CMD1 E14
MDA2 L29 U29 CMDA2 MDC2 G8 F14 CMDC2
M28 FBA_D3 FBA_CMD3 R34 F9 FBB_D3 FBB_CMD3 A12
MDA4 N31 R33 CMDA4 MDC4 F11 B12 CMDC4
P29 FBA_D5 FBA_CMD5 U32 G11 FBB_D5 FBB_CMD5 C14
MDA6 R29 U33 CMDA6 MDC6 F12 B14 CMDC6
P28 FBA_D7 FBA_CMD7 U28 G12 FBB_D7 FBB_CMD7 G15
MDA8 J28 V28 CMDA8 MDC8 G6 F15 CMDC8
H29 FBA_D9 FBA_CMD9 V29 F5 FBB_D9 FBB_CMD9 E15
MDA10 J29 V30 CMDA10 MDC10 E6 D15 CMDC10
H28 FBA_D11 FBA_CMD11 U34 F6 FBB_D11 FBB_CMD11 A14
MDA12 G29 U31 CMDA12 MDC12 F4 D14 CMDC12
E31 FBA_D13 FBA_CMD13 V34 G4 FBB_D13 FBB_CMD13 A15
MDA14 E32 V33 CMDA14 MDC14 E2 B15 CMDC14
F30 FBA_D15 FBA_CMD15 Y32 F3 FBB_D15 FBB_CMD15 C17
MDA16 C34 AA31 CMDA16 MDC16 C2 D18 CMDC16
D32 FBA_D17 FBA_CMD17 AA29 D4 FBB_D17 FBB_CMD17 E18
MDA18 B33 AA28 CMDA18 MDC18 D3 F18 CMDC18
C33 FBA_D19 FBA_CMD19 AC34 C1 FBB_D19 FBB_CMD19 A20
MDA20 F33 AC33 CMDA20 MDC20 B3 B20 CMDC20
F32 FBA_D21 FBA_CMD21 AA32 C4 FBB_D21 FBB_CMD21 C18
MDA22 H33 AA33 CMDA22 MDC22 B5 B18 CMDC22
H32 FBA_D23 FBA_CMD23 Y28 C5 FBB_D23 FBB_CMD23 G18
MEMORY INTERFACE
MDA24 P34 Y29 CMDA24 MDC24 A11 G17 CMDC24
P32 W31 C11 F17
MEMORY INTERFACE B
P31 FBA_D26 FBA_CMD26 Y30 D11 FBB_D26 FBB_CMD26 D16
MDA27 P33 AA34 CMDA27 MDC27 B11 A18 CMDC27
L31 FBA_D28 FBA_CMD28 Y31 D8 FBB_D28 FBB_CMD28 D17
MDA29 L34 Y34 CMDA29 MDC29 A8 A17 CMDC29
L32 FBA_D30 FBA_CMD30 Y33 C8 FBB_D30 FBB_CMD30 B17
MDA31 L33 V31 MDC31 B8 E17
MDA32 FBA_D31 FBA_CMD31 MDC32 FBB_D31 FBB_CMD31
AG28 FBA_D32 F24 FBB_D32
MDA33 AF29 MDC33 G23
MDA34 FBA_D33 MDC34 FBB_D33
AG29 FBA_D34 E24 FBB_D34
MDA35 AF28 R32 MDC35 G24 C12
MDA36 FBA_D35 FBA_CMD_RFU0 MDC36 FBB_D35 FBB_CMD_RFU0
AD30 FBA_D36 FBA_CMD_RFU1 AC32 D21 FBB_D36 FBB_CMD_RFU1 C20
MDA37 AD29 MDC37 E21
MDA38 FBA_D37 +VRAM_1.5VS MDC38 FBB_D37 +VRAM_1.5VS
AC29 FBA_D38 G21 FBB_D38
MDA39 AD28 RV57 60.4_0402_1% MDC39 F21 RV58 60.4_0402_1%
FBA_D39 FBB_D39
A
MDA40 AJ29 R28 FBA_DEBUG0 2 @ 1 MDC40 G27 G14 FBB_DEBUG0 2 @ 1

MDA41 FBA_D40 FBA_DEBUG0 FBB_D40 FBB_DEBUG0
AK29 FBA_D41 FBA_DEBUG1 AC28 FBA_DEBUG1 2 @ 1 MDC41 D27 FBB_D41 FBB_DEBUG1 G20 FBB_DEBUG1 2 @ 1
MDA42 AJ30 RV59 60.4_0402_1% MDC42 G26 RV60 60.4_0402_1%
AK28 FBA_D43 E27 FBB_D43
1 MDA44 AM29 MDC44 E29 1

AM31 FBA_D45 FBA_CLK0 R30 CLKA0 <19> F29 FBB_D45 FBB_CLK0 D12 CLKC0 <20>
MDA46 AN29 R31 CLKA0# <19> MDC46 E30 E12 CLKC0# <20>
MDA47 FBA_D46 FBA_CLK0_N MDC47 FBB_D46 FBB_CLK0_N
AM30 FBA_D47 FBA_CLK1 AB31 CLKA1 <18> D30 FBB_D47 FBB_CLK1 E20 CLKC1 <21>
MDA48 AN31 AC31 CLKA1# <18> MDC48 A32 F20 CLKC1# <21>
MDA49 FBA_D48 FBA_CLK1_N MDC49 FBB_D48 FBB_CLK1_N
AN32 FBA_D49 C31 FBB_D49
MDA50 AP30 MDC50 C32
AP32 FBA_D51 B32 FBB_D51
MDA52 AM33 K31 MDC52 D29 F8
MDA53 FBA_D52 FBA_WCK01 MDC53 FBB_D52 FBB_WCK01
AL31 FBA_D53 FBA_WCK01_N L30 A29 FBB_D53 FBB_WCK01_N E8
MDA54 AK33 H34 MDC54 C29 A5
AK32 FBA_D55 FBA_WCK23_N J34 B29 FBB_D55 FBB_WCK23_N A6
MDA56 AD34 AG30 MDC56 B21 D24
AD32 FBA_D57 FBA_WCK45_N AG31 C23 FBB_D57 FBB_WCK45_N D25
MDA58 AC30 AJ34 MDC58 A21 B27
AD33 FBA_D59 FBA_WCK67_N AK34 C21 FBB_D59 FBB_WCK67_N C27
MDA60 AF31 MDC60 B24
AG34 FBA_D61 C24 FBB_D61
MDA62 AG32 MDC62 B26
AG33 FBA_D63 FBA_WCKB01 J30 C26 FBB_D63 FBB_WCKB01 D6
<19> DQMA[3..0] FBA_WCKB01_N J31 <20> DQMC[3..0] FBB_WCKB01_N D7
DQMA0 P30 J32 DQMC0 E11 C6
DQMA1 FBA_DQM0 FBA_WCKB23 DQMC1 FBB_DQM0 FBB_WCKB23
F31 FBA_DQM1 FBA_WCKB23_N J33 E3 FBB_DQM1 FBB_WCKB23_N B6
DQMA2 F34 AH31 DQMC2 A3 F26
<18> DQMA[7..4] M32 FBA_DQM3 FBA_WCKB45_N AJ31 <21> DQMC[7..4] C9 FBB_DQM3 FBB_WCKB45_N E26
DQMA4 AD31 AJ32 DQMC4 F23 A26
AL29 FBA_DQM5 FBA_WCKB67_N AJ33 F27 FBB_DQM5 FBB_WCKB67_N A27
DQMA6 AM32 DQMC6 C30
DQMA7 FBA_DQM6 DQMC7 FBB_DQM6
AF34 FBA_DQM7 A24 FBB_DQM7
<19> DQSA[3..0] <20> DQSC[3..0]
DQSA0 M31 E1 FB_CLAMP 1 OPT@ 2 DQSC0 D10
DQSA1 FBA_DQS_WP0 FB_CLAMP 10K_0402_1% RV74 DQSC1 FBB_DQS_WP0
G31 FBA_DQS_WP1 D5 FBB_DQS_WP1
DQSA2 E33 DQSC2 C3
DQSA3 FBA_DQS_WP2 DQSC3 FBB_DQS_WP2
<18> DQSA[7..4] M33 FBA_DQS_WP3 <21> DQSC[7..4] B9 FBB_DQS_WP3 66mA
DQSA4 AE31 35mA K27 DQSC4 E23 H17 +FB_AVDD
FBA_DQS_WP4 FB_DLL_AVDD FBB_DQS_WP4 FBB_PLL_AVDD
CV50
0.1U_0402_10V7K
DQSA5 AK30 1 DQSC5 E28

DQSA6 FBA_DQS_WP5 DQSC6 FBB_DQS_WP5
AN33 FBA_DQS_WP6 B30 FBB_DQS_WP6
DQSA7 AF33 DQSC7 A23
FBA_DQS_WP7 +FB_AVDD FBB_DQS_WP7
<19> DQSA#[3..0] 66mA FBA_PLL_AVDD U27 <20> DQSC#[3..0]
0.1U_0402_10V7K
2
OPT@
CV51
0.1U_0402_10V7K
DQSA#0 M30 DQSC#0 D9 +1.05VS_DGPU
OPT@ CV52
DQSA#1 FBA_DQS_RN0 DQSC#1 FBB_DQS_RN0 1 +FB_AVDD
H30 FBA_DQS_RN1 1 E4 FBB_DQS_RN1 BLM18PG330SN1D_0603
DQSA#2 E34 DQSC#2 B2 100mA
FBA_DQS_RN2 FBB_DQS_RN2 LV5
DQSA#3 M34 H26 DQSC#3 A9
<18> DQSA#[7..4] FBA_DQS_RN3 FB_VREF <21> DQSC#[7..4] FBB_DQS_RN3 1 2 +FB_AVDD
DQSA#4 AF30 DQSC#4 D22 2
1U_0402_6.3V6K
22U_0805_6.3V6M
FBA_DQS_RN4 FBB_DQS_RN4
OPT@
DQSA#5 AK31 2 DQSC#5 D28 OPT@
OPT@ CV86
OPT@ CV233
DQSA#6 FBA_DQS_RN5 DQSC#6 FBB_DQS_RN5 1 1
AM34 FBA_DQS_RN6 A30 FBB_DQS_RN6
DQSA#7 AF32 DQSC#7 B23
FBA_DQS_RN7 FBB_DQS_RN7
2 2
N13P-PES-A2_FCBGA908 N13PGLR1@ N13P-PES-A2_FCBGA908 N13PGLR1@
12mil

N13P VRAM Interface
A
5 4 3 2 1
Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SO +3VS_DGPU XCLK_417 for GL FB_0_BAR_SIZE for GL SMB_ALT_ADDR VGA_DEVICE
, FB[1] , FB[0]
ROM_SCLK +3VS_DGPU PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG for GL PEX_PLLEN_TERM
PCI_DEVID[5]
ROM_SI +3VS_DGPU RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0]
STRAP0 +3VS_DGPU USER[3] USER[2] USER[1] USER[0]
D UV4D D
STRAP1 +3VS_DGPU 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
Part 4 of 7
AM6 +3VS_DGPU PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
AN6
IFPA_TXC
P8
STRAP2
IFPA_TXC_N NC
AP3 AC6 +3VS_DGPU SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
AN3
IFPA_TXD0 NC
AJ28
STRAP3
IFPA_TXD0_N NC
AN5 IFPA_TXD1 NC AJ4
AM5 AJ5 STRAP4 +3VS_DGPU RESERVED PCIE_SPEED_CHANGE_GEN3 PCIE_MAX_SPEED DP_PLL_VDD33V
IFPA_TXD1_N NC
AL6 IFPA_TXD2 NC AL11
AK6 IFPA_TXD2_N NC C15
NC
AJ6 IFPA_TXD3 NC D19
AH6 IFPA_TXD3_N NC D20 Pull-up to +3VS
NC D23 Resistor Values Pull-down to Gnd
D26 SKU Device ID biit5 to bit0 _DGPU
NC
AJ9 IFPB_TXC NC H31 5K 1000 0000
AH9 T8 +VGA_CORE
IFPB_TXC_N NC
AP6 IFPB_TXD4 NC V32 N13P-GL ES2 0x0DE9 101001 10K 1001 0001
AP5 IFPB_TXD4_N
2
AM7 IFPB_TXD5 15K 1010 0010
AL7 RV15 N13P-GS ES1 0x0FDB 011011
IFPB_TXD5_N 100_0402_1%
AN8 IFPB_TXD6 20K 1011 0011
AM8 OPT@
IFPB_TXD6_N
AK8 N13P-GS QS 0x0FD2 010010 25K 1100 0100
1
IFPB_TXD7
AL8 IFPB_TXD7_N
L4 GCORE_SEN_R 1 @ 2
VDD_SENSE RV80 0_0402_5% VGA_VCC_SENSE <51> 30K 1101 0101
AK1 IFPC_L0 35K 1110 0110
AJ1 IFPC_L0_N
AJ3 L5 FB_GND_R 1 @ 2
IFPC_L1 GND_SENSE RV81 0_0402_5%
VGA_VSS_SENSE <51> 45K 1111 0111
AJ2 IFPC_L1_N
AH3 IFPC_L2 MULTI LEVEL STRAPS
C C
AH4 IFPC_L2_N 2 OPT@ 1
AG5 RV17 +3VS_DGPU +3VS_DGPU
AG4
IFPC_L3 100_0402_1% Straps
IFPC_L3_N
TEST
@ 1
1
10K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
2 OPT@ 1
@ 1
1
RV82 1 OPT@ 2 10K_0402_5%
10K_0402_1%
10K_0402_1%
45.3K_0402_1%
4.99K_0402_1%
AM1 IFPD_L0 TESTMODE AK11
N13PGS@
N13PGL@
N13PGS@
AM2 IFPD_L0_N
@
2 RV98
GSDIS@
AM3 AM10 JTAG_TCK PAD @
IFPD_L1 JTAG_TCK TV4
AM4 AM11 JTAG_TDI PAD @
IFPD_L1_N JTAG_TDI TV1
RV69
RV78
RV70
AL3 AP12 JTAG_TDO
RV64
RV65
RV79
RV68
PAD TV2 @
2
IFPD_L2 JTAG_TDO
2
AL4 AP11 JTAG_TMS PAD
IFPD_L2_N JTAG_TMS TV3 @
AK4 AN11 JTAG_TRST 1 OPT@ 2 STRAP0 ROM_SI
IFPD_L3 JTAG_TRST_N RV84 10K_0402_5% ROM_SO
AK5 IFPD_L3_N STRAP1 STRAP3
LVDS/TMDS
STRAP2 STRAP4 ROM_SCLK
15K_0402_1%
AD2
15K_0402_1%
10K_0402_1%
IFPE_L0
@ 1
2N13PGL@ 1
2
4.99K_0402_1%
45.3K_0402_1%
34.8K_0402_1%
@ 1
N13PGS@ 2
RV75 1
1
4.99K_0402_1%
45.3K_0402_1%
AD3
N13PGL@
IFPE_L0_N
GSOPT@
N13PGS@
RV53
SERIAL
N13PGL@
AD1
RV54
IFPE_L1
2 RV76
AC1 IFPE_L1_N
AC2 H6 ROM_CS# 1 @ 2 +3VS_DGPU
IFPE_L2 ROM_CS_N
RV77
RV89
AC3 H4 ROM_SCLK RV85 10K_0402_5%
RV72
RV73
1
IFPE_L2_N ROM_SCLK
2
AC4 H5 ROM_SI RV73
IFPE_L3 ROM_SI ROM_SO 4.99K_0402_1%
AC5 IFPE_L3_N ROM_SO H7
N13PGS@ For X76
AE3 IFPF_L0
AE4 IFPF_L0_N
AF4 IFPF_L1
AF5
AD4
IFPF_L1_N GENERAL
AD5
IFPF_L2
L2 RV153 1 OPT@ 2 10K_0402_5%
Hynix (900MHZ) RV77 PD 15K
IFPF_L2_N BUFRST_N
B
AG1
AF1
IFPF_L3
L3 RV86 1N13PGL@ 2 10K_0402_5%
64MX16 H5TQ1G63DFR-11C 1GB 0010 B
IFPF_L3_N CEC +3VS_DGPU (SD034150280)
J1 MULTI_STRAP_REF0_GND 1 OPT@ 2
SA000041S20
MULTI_STRAP_REF0_GND RV87 40.2K_0402_1%
AG3 IFPC_AUX_I2CW_SCL Hynix (900MHZ)
AG2 IFPC_AUX_I2CW_SDA_N RV77 PD 34.8k
STRAP0
STRAP0 J2
J7 STRAP1
128MX16 H5TQ2G63BFR-11C 2GB 0110
AK3
STRAP1
J6 STRAP2 (SD034348280)
AK2
IFPD_AUX_I2CX_SCL STRAP2
J5 STRAP3 SA00003YO00
IFPD_AUX_I2CX_SDA_N STRAP3 STRAP4
STRAP4 J3
AB3
Hynix (900MHZ)
IFPE_AUX_I2CY_SCL RV77 PD 30k
N13P-GL
AB4 IFPE_AUX_I2CY_SDA_N 128MX16 H5TQ2G63DFR-11C 2GB 0101
ROM_SI
THERMDP K3 (SD034300280)
THERMDN K4 SA00003YO70
AF3 IFPF_AUX_I2CZ_SCL
AF2 IFPF_AUX_I2CZ_SDA_N
Samsung (900MHZ)
RV77 PD 20K
64MX16 K4W1G1646G-BC11 1GB 0011
N13P-PES-A2_FCBGA908 N13PGLR1@ (SD034200280)
SA00004GS00
Samsung (900MHZ)
RV77 PD 45.3K
128M16 K4W2G1646C-HC11 2GB 0111
(SD034453280)
SA000047Q00
A A
Samsung (900MHZ) RV77 PD 10K
2GB 0001
128M16 K4W2G1646E-BC11 (SD028100280)
SA00005SH00
VGA_N13P LVDS&TMDS
5 4 3 2 1
5 4 3 2 1
Under GPU midway between GPU +1.05VS_DGPU

Near GPU and Power supply
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
4.7U_0402_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
OPT@ CV54
OPT@ CV55
OPT@ CV56
OPT@ CV57
OPT@ CV58
OPT@ CV59
OPT@ CV60
1 1 1 1 1 1 1
2 2 2 2 2 2 2
UV4E
+VRAM_1.5VS Under GPU Part 5 of 7
D D
7200 mA 3300 mA midway between GPU +1.05VS_DGPU
AA27 AG19 Under GPU
FBVDDQ_0 PEX_IOVDD_0 and Power supply
4.7U_0402_6.3V6M
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
OPT@ CV61 AA30 FBVDDQ_1 PEX_IOVDD_1 AG21 Near GPU
OPT@ CV62
OPT@ CV63
OPT@ CV64
OPT@ CV65
OPT@ CV66
1 1 1 1 1 1 AB27 FBVDDQ_2 PEX_IOVDD_2 AG22
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
4.7U_0402_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
AB33 FBVDDQ_3 PEX_IOVDD_3 AG24 total 6600mA
OPT@ CV74
OPT@ CV75
OPT@ CV76
OPT@ CV77
OPT@ CV67
OPT@ CV78
OPT@ CV68
AC27 AH21 1 1 1 1 1 1 1
AD27
FBVDDQ_4 PEX_IOVDD_4
AH25
Design guide page.74
2 2 2 2 2 2 FBVDDQ_5 PEX_IOVDD_5
AE27 FBVDDQ_6
AF27 FBVDDQ_7 3300mA 2 2 2 2 2 2 2
AG27 FBVDDQ_8 PEX_IOVDDQ_0 AG13
B13 FBVDDQ_9 PEX_IOVDDQ_1 AG15
Under GPU B16 AG16
FBVDDQ_10 PEX_IOVDDQ_2
B19 FBVDDQ_11 PEX_IOVDDQ_3 AG18
E13 FBVDDQ_12 PEX_IOVDDQ_4 AG25
4.7U_0402_6.3V6M
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
E16 FBVDDQ_13 PEX_IOVDDQ_5 AH15
+3VS_DGPU
OPT@ CV69
OPT@ CV70
OPT@ CV79
OPT@ CV71
OPT@ CV72
OPT@ CV73
1 1 1 1 1 1 E19 FBVDDQ_14 PEX_IOVDDQ_6 AH18
H10 AH26 Near GPU
H11 FBVDDQ_16 PEX_IOVDDQ_8 AH27
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
H12 FBVDDQ_17 PEX_IOVDDQ_9 AJ27
2 2 2 2 2 2
CV81
CV82
H13 FBVDDQ_18 PEX_IOVDDQ_10 AK27 1 1
H14 AL27
POWER
H15 FBVDDQ_20 PEX_IOVDDQ_12 AM28
H16 FBVDDQ_21 PEX_IOVDDQ_13 AN28
2 2
OPT@
OPT@
Near GPU H18 FBVDDQ_22
H19 FBVDDQ_23 N13PGS@
H20 FBVDDQ_24 210mA 420mA 2 1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
H21 AH12 +3VS_DGPU

FBVDDQ_25 PEX_PLL_HVDD
OPT@ CV244
OPT@ CV243
OPT@ CV83
OPT@ CV84
RV101
@ CV85
@ CV231
1 1 1 1 1 1 H22 FBVDDQ_26
H23 1 2 OPT@ 0_0603_5%
FBVDDQ_27 CV80 0.1U_0402_10V7K
CV80,CV198 Under GPU +1.05VS_DGPU
H24 FBVDDQ_28 210mA close to ball LV7
H8 FBVDDQ_29 PEX_SVDD_3V3 AG12 Under GPU Near GPU
2 2 2 2 2 2 H9 FBVDDQ_30 2 1
4.7U_0402_6.3V6M
0.1U_0402_10V7K
1U_0402_6.3V6K
C C
L27 FBVDDQ_31 1 2 OPT@ BLM18PG121SN1D_0603
N13PGL@
CV87
CV88
CV89
M27 150mA CV198 0.1U_0402_10V7K 1 1 1
FBVDDQ_32 +PEX_PLLVDD
N27 AG26
P27
FBVDDQ_33 PEX_PLLVDD PCIE2.0 N13P-GL N13M-GS
FBVDDQ_34 PCIE3.0 N13P-GS/GT N13E-GE
R27 FBVDDQ_35 2 2 2
OPT@
OPT@
OPT@
T27 FBVDDQ_36 85mA +3VS_DGPU
85mA
T30 FBVDDQ_37 VDD33_0 J8
T33 FBVDDQ_38 VDD33_1 K8
V27 FBVDDQ_39 VDD33_2 L8
W27 M8 +3VS_DGPU
FBVDDQ_40 VDD33_3
W30 FBVDDQ_41
Under GPU Near GPU
W33 FBVDDQ_42
4.7U_0402_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
Y27 FBVDDQ_43 125mA
CV90
CV91
CV92
CV95
CV96
OPT@ CV97
AH8 +IFPAB_PLLVDD CV101 1 OPT@ 2 10K_0402_5% 1 1 1 1 1 1
IFPAB_PLLVDD RV90 @
IFPAB_RSET AJ8 1 2 1K_0402_5%
115mA AG8 +IFPAB_IOVDD CV104 1 OPT@ 2 10K_0402_5%

IFPA_IOVDD 2 2 2 2 2 2
OPT@
OPT@
OPT@
OPT@
OPT@
IFPB_IOVDD AG9
F1 FB_VDDQ_SENSE
100mA IFPC_PLLVDD AF7 +IFPC_PLLVDD RV298 1 OPT@ 2 10K_0402_5%

F2 FB_GND_SENSE IFPC_RSET AF8
+VRAM_1.5VS
72mA AF6 +IFPC_IOVDD RV295 1 OPT@ 2 10K_0402_5%
IFPC_IOVDD
2 OPT@ 1 FB_CAL_PD_VDDQ J27
FB_CAL_PD_VDDQ
RV96 40.2_0402_1%
AG7 +IFPD_PLLVDD RV297 1 OPT@ 2 10K_0402_5%
IFPD_PLLVDD
1 OPT@ 2 FB_CAL_PU_GND H27
FB_CAL_PU_GND IFPD_RSET AN2
RV605 42.2_0402_1%
AG6 +IFPD_IOVDD RV296 1 OPT@ 2 10K_0402_5%
FB_CAL_TERM_GND H25 IFPD_IOVDD
1 OPT@ 2 FB_CAL_TERM_GND
RV609 51.1_0402_1%
B +IFPEF_PLLVDD CV286 B
200mA IFPEF_PLVDD AB8 1 OPT@ 2 10K_0402_5%
AD6 RV103 1 @ 2 1K_0402_5%
IFPEF_RSET
AC7 +IFPEF_IOVDD CV234 1 OPT@ 2 10K_0402_5%
IFPE_IOVDD
144mA IFPF_IOVDD AC8
N13P-PES-A2_FCBGA908 N13PGLR1@
A A

VGA_N13P POWER
5 4 3 2 1
5 4 3 2 1
UV4F +VGA_CORE UV4G +VGA_CORE
Part 6 of 7
A2 D2 50A Part 7 of 7 V17
D GND_0 GND_100 VDD_56 D
AA17 GND_1 GND_101 D31 AA12 VDD_0 VDD_57 V18
AA18 GND_2 GND_102 D33 AA14 VDD_1 VDD_58 V20
AA20 GND_3 GND_103 E10 AA16 VDD_2 VDD_59 V22
AA22 E22 AA19 W12
VGA_CORE cap. ought to power pate

GND_4 GND_104 VDD_3 VDD_60
AB12 GND_5 GND_105 E25 AA21 VDD_4 VDD_61 W14
AB14 GND_6 GND_106 E5 AA23 VDD_5 VDD_62 W16
AB16 GND_7 GND_107 E7 AB13 VDD_6 VDD_63 W19
AB19 GND_8 GND_108 F28 AB15 VDD_7 VDD_64 W21
AB2 GND_9 GND_109 F7 AB17 VDD_8 VDD_65 W23
AB21 GND_10 GND_110 G10 AB18 VDD_9 VDD_66 Y13
A33 GND_11 GND_111 G13 AB20 VDD_10 VDD_67 Y15
AB23 GND_12 GND_112 G16 AB22 VDD_11 VDD_68 Y17
AB28 GND_13 GND_113 G19 AC12 VDD_12 VDD_69 Y18
AB5 GND_16 GND_116 G25 AC19 VDD_15
AB7 GND_17 GND_117 G28 AC21 VDD_16
AC13 GND_18 GND_118 G3 AC23 VDD_17 XVDD_1 U1
AC15 GND_19 GND_119 G30 M12 VDD_18 XVDD_2 U2
POWER
AA13 GND_22 GND_122 G5 M19 VDD_21 XVDD_5 U5
AC22 GND_24 GND_124 K2 M23 VDD_23 XVDD_7 U7
AE2 GND_25 GND_125 K28 N13 VDD_24 XVDD_8 U8
AE28 GND_26 GND_126 K30 N15 VDD_25
AE30 GND_27 GND_127 K32 N17 VDD_26
AE32 GND_28 GND_128 K33 N18 VDD_27 XVDD_9 V1
AE7 GND_31 GND_131 M13 P12 VDD_30 XVDD_12 V4
AH10 GND_32 GND_132 M15 P14 VDD_31 XVDD_13 V5
C C
AA15 GND_33 GND_133 M17 P16 VDD_32 XVDD_14 V6
AH19 GND_36 GND_136 M22 P23 VDD_35
AH2 GND_37 GND_137 N12 R13 VDD_36
AH22 GND_38 GND_138 N14 R15 VDD_37 XVDD_17 W2
GND
AH32 GND_43 GND_143 N23 T12 VDD_42 XVDD_22 W8

AH33 GND_44 GND_144 N28 T14 VDD_43
AH5 GND_45 GND_145 N30 T16 VDD_44
AH7 GND_46 GND_146 N32 T19 VDD_45 XVDD_23 Y1
AJ7 GND_47 GND_147 N33 T21 VDD_46 XVDD_24 Y2
AK10 GND_48 GND_148 N5 T23 VDD_47 XVDD_25 Y3
AK7 GND_49 GND_149 N7 U13 VDD_48 XVDD_26 Y4
AL12 GND_50 GND_150 P13 U15 VDD_49 XVDD_27 Y5
AL18 GND_54 GND_154 P20 U22 VDD_53
AL2 GND_55 GND_155 P22 V13 VDD_54
AL20 GND_56 GND_156 R12 V15 VDD_55 XVDD_31 AA1
AL21 GND_57 GND_157 R14 XVDD_32 AA2
AL30 GND_62 GND_162 T13 XVDD_37 AA7
AL32 GND_63 GND_163 T15 XVDD_38 AA8
AL33 GND_64 GND_164 T17
B B
AL5 GND_65 GND_165 T18
AM13 GND_66 GND_166 T2
AM16 T20 N13P-PES-A2_FCBGA908 N13PGLR1@
GND_67 GND_167
AM19 GND_68 GND_168 T22
AM22 GND_69 GND_169 AG11
AM25 GND_70 GND_170 T28
AN1 GND_71 GND_171 T32
AN16 GND_74 GND_174 U12
AN19 GND_75 GND_175 U14
AN22 GND_76 GND_176 U16
AN25 GND_77 GND_177 U19
AN30 GND_78 GND_178 U21
AN34 GND_79 GND_179 U23
AN4 GND_80 GND_180 V12
AN7 GND_81 GND_181 V14
AP2 GND_82 GND_182 V16
AP33 GND_83 GND_183 V19
B1 GND_84 GND_184 V21
B10 GND_85 GND_185 V23
B22 GND_86 GND_186 W13
B25 GND_87 GND_187 W15
B28 GND_88 GND_188 W17
B31 GND_89 GND_189 W18
B34 GND_90 GND_190 W20
B4 GND_91 GND_191 W22
B7 GND_92 GND_192 W28
C10 GND_93 GND_193 Y12
C13 GND_94 GND_194 Y14
C19 GND_95 GND_195 Y16
C22 GND_96 GND_196 Y19
A A
C25 GND_97 GND_197 Y21
C28 GND_98 GND_198 Y23
C7 GND_99 GND_199 AH11
GND_OPT C16
GND_OPT W32
N13P-PES-A2_FCBGA908 N13PGLR1@ Security Classification Compal Secret Data Compal Electronics, Inc.
VGA_N13P POWER & GND
5 4 3 2 1
5 4 3 2 1
VRAM DDR3 chips (1GB) Mode D

Address 0..31 32..63
64Mx16 DDR3 *8==>1GB CMD0 CS0_L#
CMD1
D D
CMD2 ODT_L
UV10 @ UV11 @
CMD3 CKE
+MEM_VREF_CA1 M8 E3 MDA39 +MEM_VREF_CA1 M8 E3 MDA45
+MEM_VREF_DQ1 VREFCA DQL0 MDA35 +MEM_VREF_DQ1 VREFCA DQL0 MDA40
DQMA[7..0]
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 CMD4 A14 A14
F2 MDA37 F2 MDA46
<14,19> DQMA[7..0] DQL2 DQL2
CMDA9 N3 F8 MDA33 CMDA9 N3 F8 MDA41 CMD5 RST RST
CMDA[30..0] CMDA11 A0 DQL3 MDA38 Group4 CMDA11 A0 DQL3 MDA47 Group5
<14,19> CMDA[30..0] P7 A1 DQL4 H3 P7 A1 DQL4 H3
CMDA8 P3 H8 MDA32 CMDA8 P3 H8 MDA43 CMD6 A9 A9
DQSA#[7..0] CMDA25 A2 DQL5 MDA36 CMDA25 A2 DQL5 MDA44
<14,19> DQSA#[7..0] N2 A3 DQL6 G2 N2 A3 DQL6 G2
CMDA10 P8 H7 MDA34 CMDA10 P8 H7 MDA42 CMD7 A7 A7
DQSA[7..0] CMDA24 A4 DQL7 CMDA24 A4 DQL7
<14,19> DQSA[7..0] P2 A5 P2 A5
CMDA22 R8 CMDA22 R8 CMD8 A2 A2
MDA[63..0] CMDA7 A6 MDA61 CMDA7 A6 MDA53
<14,19> MDA[63..0] R2 A7 DQU0 D7 R2 A7 DQU0 D7
CMDA21 T8 C3 MDA59 CMDA21 T8 C3 MDA49 CMD9 A0 A0
CMDA6 A8 DQU1 MDA60 CMDA6 A8 DQU1 MDA55
R3 A9 DQU2 C8 R3 A9 DQU2 C8
CMDA29 L7 C2 MDA57 CMDA29 L7 C2 MDA50 CMD10 A4 A4
CMDA23 A10/AP DQU3 MDA63 Group7 CMDA23 A10/AP DQU3 MDA52 Group6
R7 A11 DQU4 A7 R7 A11 DQU4 A7
CMDA28 N7 A2 MDA56 CMDA28 N7 A2 MDA48 CMD11 A1 A1
+VRAM_1.5VS CMDA20 A12 DQU5 MDA62 CMDA20 A12 DQU5 MDA54
T3 A13 DQU6 B8 T3 A13 DQU6 B8
CMDA4 T7 A3 MDA58 CMDA4 T7 A3 MDA51 CMD12 BA0 BA0
CMDA14 A14 DQU7 CMDA14 A14 DQU7
M7 A15/BA3 M7 A15/BA3
1
+VRAM_1.5VS +VRAM_1.5VS
CMD13 WE* WE*
RV107
1K_0402_1% CMDA12 M2 B2 CMDA12 M2 B2 CMD14 A15 A15
OPT@ CMDA27 BA0 VDD CMDA27 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
CMDA26 M3 G7 CMDA26 M3 G7 CMD15 CAS* CAS*
2
+MEM_VREF_CA1 BA2 VDD BA2 VDD

VDD K2 VDD K2
VDD K8 VDD K8 CMD16 CS0_H#
1
1 VDD N1 VDD N1
RV106 CV230 CLKA1 J7 N9 CLKA1 J7 N9 CMD17
1K_0402_1% 0.01U_0402_25V7K CLKA1# CK VDD CLKA1# CK VDD
K7 CK VDD R1 K7 CK VDD R1
C OPT@ OPT@ CMDA19 CMDA19 C
2
K9 CKE/CKE0 VDD R9
+VRAM_1.5VS
K9 CKE/CKE0 VDD R9
+VRAM_1.5VS
CMD18 ODT_H
2
CMD19 CKE_H
CMDA18 K1 A1 CMDA18 K1 A1
CMDA16 ODT/ODT0 VDDQ CMDA16 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8 CMD20 A13 A13
CMDA30 J3 C1 CMDA30 J3 C1
CMDA15 RAS VDDQ CMDA15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9 CMD21 A8 A8
CMDA13 L3 D2 CMDA13 L3 D2
+VRAM_1.5VS WE VDDQ WE VDDQ
310mAVDDQ E9 310mAVDDQ E9 CMD22 A6 A6
VDDQ F1 VDDQ F1
DQSA4 F3 H2 DQSA5 F3 H2 CMD23 A11 A11
DQSL VDDQ DQSL VDDQ
1
DQSA7 C7 H9 DQSA6 C7 H9
RV119 DQSU VDDQ DQSU VDDQ
CMD24 A5 A5
1K_0402_1%
OPT@ DQMA4 E7 A9 DQMA5 E7 A9 CMD25 A3 A3
DQMA7 DML VSS DQMA6 DML VSS
D3 B3 D3 B3
2
+MEM_VREF_DQ1 DMU VSS DMU VSS

VSS E1 VSS E1 CMD26 BA2 BA2
VSS G8 VSS G8
1
1 DQSA#4 G3 J2 DQSA#5 G3 J2 CMD27 BA1 BA1

RV108 CV301 DQSA#7 DQSL VSS DQSA#6 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8
1K_0402_1% 0.01U_0402_25V7K M1 M1 CMD28 A12 A12
OPT@ OPT@ VSS VSS
VSS M9 VSS M9
2
P1 P1 CMD29 A10 A10
2
CMDA5 VSS CMDA5 VSS

T2 RESET VSS P9 T2 RESET VSS P9
VSS T1 VSS T1 CMD30 RAS* RAS*
ZQ2 L8 T9 ZQ3 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
Not Available
1
1
OPT@
OPT@ J1 B1 RV124 J1 B1 LOW HIGH
RV123 NC/ODT1 VSSQ 243_0402_1% NC/ODT1 VSSQ
L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9
243_0402_1% J9 D1 J9 D1
NC/CE1 VSSQ NC/CE1 VSSQ
<14> CLKA1 L9 D8 L9 D8
2
2
B NCZQ1 VSSQ NCZQ1 VSSQ B
VSSQ E2 VSSQ E2
1
VSSQ E8 VSSQ E8
OPT@ F9 F9
RV126 VSSQ VSSQ
VSSQ G1 VSSQ G1
160_0402_1% G9 G9
VSSQ VSSQ
2
96-BALL 96-BALL
<14> CLKA1#
SDRAM DDR3 SDRAM DDR3
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
CV144
CV143
CV140
CV142
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
CV138
CV137
CV139
CV141
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV288
CV258
CV260
CV259
CV275
CV276
CV277
CV278
CV279
CV280
CV257
CV256
OPT@ CV255
CV238
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
A A

VGA_N13P VRAM Channel AH
5 4 3 2 1
5 4 3 2 1
VRAM DDR3 chips (1GB) Mode D

Address 0..31 32..63
CMD0 CS0_L#
D 64Mx16 DDR3 *8==>1GB CMD1 D
CMD2 ODT_L
CMD3 CKE
CMD4 A14 A14
DQSA[7..0] CMD5 RST RST
<14,18> DQSA[7..0]
UV8 @ UV9 @
DQSA#[7..0] swap 0329 CMD6 A9 A9
<14,18> DQSA#[7..0]
+MEM_VREF_CA0 M8 E3 MDA12 +MEM_VREF_CA0 M8 E3 MDA3
DQMA[7..0] +MEM_VREF_DQ0 VREFCA DQL0 MDA14 +MEM_VREF_DQ0 VREFCA DQL0 MDA4
<14,18> DQMA[7..0] H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 CMD7 A7 A7
F2 MDA8 F2 MDA2
MDA[63..0] CMDA9 DQL2 MDA15 CMDA9 DQL2 MDA7
<14,18> MDA[63..0] N3 A0 DQL3 F8 N3 A0 DQL3 F8 CMD8 A2 A2
CMDA11 P7 H3 MDA9 Group1 CMDA11 P7 H3 MDA0 Group0
CMDA[30..0] CMDA8 A1 DQL4 MDA13 CMDA8 A1 DQL4 MDA5
<14,18> CMDA[30..0] P3 A2 DQL5 H8 P3 A2 DQL5 H8 CMD9 A0 A0
CMDA25 N2 G2 MDA10 CMDA25 N2 G2 MDA1
CMDA10 A3 DQL6 MDA11 CMDA10 A3 DQL6 MDA6
P8 A4 DQL7 H7 P8 A4 DQL7 H7 CMD10 A4 A4
CMDA24 P2 CMDA24 P2
+VRAM_1.5VS CMDA22 A5 CMDA22 A5
R8 A6 R8 A6 CMD11 A1 A1
CMDA7 R2 D7 MDA17 CMDA7 R2 D7 MDA27
CMDA21 A7 DQU0 MDA21 CMDA21 A7 DQU0 MDA29
T8 A8 DQU1 C3 T8 A8 DQU1 C3 CMD12 BA0 BA0
1
CMDA6 R3 C8 MDA18 CMDA6 R3 C8 MDA25

RV62 CMDA29 A9 DQU2 MDA23 CMDA29 A9 DQU2 MDA30
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 CMD13 WE* WE*
1K_0402_1% CMDA23 R7 A7 MDA19 Group2 CMDA23 R7 A7 MDA24 Group3
OPT@ CMDA28 A11 DQU4 MDA22 CMDA28 A11 DQU4 MDA28
N7 A12 DQU5 A2 N7 A12 DQU5 A2 CMD14 A15 A15
CMDA20 T3 B8 MDA16 CMDA20 T3 B8 MDA26
2
+MEM_VREF_CA0 CMDA4 A13 DQU6 MDA20 CMDA4 A13 DQU6 MDA31

T7 A14 DQU7 A3 T7 A14 DQU7 A3 CMD15 CAS* CAS*
CMDA14 M7 CMDA14 M7
A15/BA3 A15/BA3
1
1 CMD16 CS0_H#
RV63 CV228
C 1K_0402_1% 0.01U_0402_25V7K CMDA12 CMDA12 C
M2 BA0 VDD B2 M2 BA0 VDD B2 CMD17
OPT@ OPT@ CMDA27 N8 D9 CMDA27 N8 D9
2 CMDA26 BA1 VDD CMDA26 BA1 VDD
M3 G7 M3 G7 CMD18 ODT_H
2
BA2 VDD BA2 VDD

VDD K2 VDD K2
VDD K8 VDD K8 CMD19 CKE_H
VDD N1 VDD N1
CLKA0 J7 N9 CLKA0 J7 N9 CMD20 A13 A13
CLKA0# CK VDD CLKA0# CK VDD
CMDA3 K9 R9 CMDA3 K9 R9 CMD21 A8 A8
+VRAM_1.5VS CKE/CKE0 VDD +VRAM_1.5VS CKE/CKE0 VDD +VRAM_1.5VS
CMD22 A6 A6
CMDA2 K1 A1 CMDA2 K1 A1
ODT/ODT0 VDDQ ODT/ODT0 VDDQ
1
CMDA0 L2 A8 CMDA0 L2 A8 CMD23 A11 A11

RV105 CMDA30 CS/CS0 VDDQ CMDA30 CS/CS0 VDDQ
J3 RAS VDDQ C1 J3 RAS VDDQ C1
1K_0402_1% CMDA15 K3 C9 CMDA15 K3 C9 CMD24 A5 A5
OPT@ CMDA13 CAS VDDQ CMDA13 CAS VDDQ
L3 WE VDDQ D2 L3 WE VDDQ D2
310mAVDDQ E9 E9 CMD25 A3 A3
2
+MEM_VREF_DQ0 VDDQ
DQSA1 VDDQ F1
DQSA0
310mAVDDQ F1
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2 CMD26 BA2 BA2
1
1 DQSA2 C7 H9 DQSA3 C7 H9
RV88 CV229 DQSU VDDQ DQSU VDDQ
CMD27 BA1 BA1
1K_0402_1% 0.01U_0402_25V7K
OPT@ OPT@ DQMA1 E7 A9 DQMA0 E7 A9 CMD28 A12 A12
2 DQMA2 DML VSS DQMA3 DML VSS
D3 B3 D3 B3
2
DMU VSS DMU VSS

VSS E1 VSS E1 CMD29 A10 A10
VSS G8 VSS G8
DQSA#1 G3 J2 DQSA#0 G3 J2 CMD30 RAS* RAS*
DQSA#2 DQSL VSS DQSA#3 DQSL VSS
VSS M1 VSS M1 Not Available
VSS M9 VSS M9
CMDA5 VSS P1
CMDA5 VSS P1 LOW HIGH
T2 RESET VSS P9 T2 RESET VSS P9
B B
VSS T1 VSS T1
ZQ0 L8 T9 ZQ1 L8 T9
1
1
<14> CLKA0
OPT@ J1 B1 OPT@ J1 B1 CMDA2 RV112 1 OPT@ 2 10K_0402_5% Command Bit Default Pull-down
NC/ODT1 VSSQ NC/ODT1 VSSQ
1
RV110 L1 B9 RV111 L1 B9 CMDA3 RV113 1 OPT@ 2 10K_0402_5%

OPT@ 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ CMDA5 RV115 1 OPT@ 10K_0402_5%
J9 NC/CE1 VSSQ D1 J9 NC/CE1 VSSQ D1 2 ODTx 10k
RV114 L9 D8 L9 D8 CMDA18 RV116 1 OPT@ 2 10K_0402_5%
2
2
160_0402_1% NCZQ1 VSSQ NCZQ1 VSSQ CMDA19 RV117 1 OPT@ 10K_0402_5% DDR3 CKEx 10k
VSSQ E2 VSSQ E2 2
E8 E8 RST 10k
2
VSSQ VSSQ
<14> CLKA0# VSSQ F9 VSSQ F9
CS* No Termination
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
96-BALL 96-BALL
+VRAM_1.5VS
+VRAM_1.5VS
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0603_6.3V6M
CV152
CV151
CV149
CV150
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1
10U_0603_6.3V6M
CV148
CV147
CV145
CV146
CV311
CV313
CV312
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CV241
1 1 1 1 1 1 1 1
CV261
CV310
CV262
CV240
2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
A A

VGA_N13P VRAM Channel AL
5 4 3 2 1
5 4 3 2 1
Mode D
Address 0..31 32..63
VRAM DDR3 chips (1GB) CMD0 CS0_L#
CMD1
64Mx16 DDR3 *8==>1GB CMD2 ODT_L
D D
CMD3 CKE
CMD4 A14 A14
DQSC[7..0]
CMD5 RST RST
<14,21> DQSC[7..0]
DQSC#[7..0]
CMD6 A9 A9
UV12 @ UV13 @
<14,21> DQSC#[7..0] swap 0329 CMD7 A7 A7
DQMC[7..0] +MEM_VREF_CA2 M8 E3 MDC8 +MEM_VREF_CA2 M8 E3 MDC3
<14,21> DQMC[7..0] VREFCA DQL0 VREFCA DQL0
+MEM_VREF_DQ2 H1 F7 MDC12 +MEM_VREF_DQ2 H1 F7 MDC7 CMD8 A2 A2
MDC[63..0] VREFDQ DQL1 MDC11 VREFDQ DQL1 MDC1
<14,21> MDC[63..0] DQL2 F2 DQL2 F2
CMDC9 N3 F8 MDC13 CMDC9 N3 F8 MDC4 CMD9 A0 A0
CMDC[30..0] CMDC11 A0 DQL3 MDC9 Group1 CMDC11 A0 DQL3 MDC2 Group0
<14,21> CMDC[30..0] P7 A1 DQL4 H3 P7 A1 DQL4 H3
CMDC8 P3 H8 MDC14 CMDC8 P3 H8 MDC6 CMD10 A4 A4
CMDC25 A2 DQL5 MDC10 CMDC25 A2 DQL5 MDC0
N2 A3 DQL6 G2 N2 A3 DQL6 G2
CMDC24 A4 DQL7 CMDC24 A4 DQL7
P2 A5 P2 A5
CMDC22 R8 CMDC22 R8 CMD12 BA0 BA0
CMDC7 A6 MDC18 CMDC7 A6 MDC26
R2 A7 DQU0 D7 R2 A7 DQU0 D7
CMDC21 T8 C3 MDC20 CMDC21 T8 C3 MDC31 CMD13 WE* WE*
CMDC6 A8 DQU1 MDC17 CMDC6 A8 DQU1 MDC25
+VRAM_1.5VS CMDC29 L7 C2 MDC22 CMDC29 L7 C2 MDC30 CMD14 A15 A15
CMDC23 A10/AP DQU3 MDC16 Group2 CMDC23 A10/AP DQU3 MDC27 Group3
CMDC28 N7 A2 MDC23 CMDC28 N7 A2 MDC28 CMD15 CAS* CAS*
A12 DQU5 A12 DQU5
1
CMDC20 T3 B8 MDC19 CMDC20 T3 B8 MDC24

RV121 CMDC4 A13 DQU6 MDC21 CMDC4 A13 DQU6 MDC29
T7 A14 DQU7 A3 T7 A14 DQU7 A3 CMD16 CS0_H#
1K_0402_1% CMDC14 M7 CMDC14 M7
OPT@ A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS CMD17
2
+MEM_VREF_CA2 CMDC12 M2 B2 CMDC12 M2 B2 CMD18 ODT_H

CMDC27 BA0 VDD CMDC27 BA0 VDD
1
C CMDC26 CMDC26 C
1 M3 BA2 VDD G7 M3 BA2 VDD G7 CMD19 CKE_H
RV120 CV302 K2 K2
1K_0402_1% 0.01U_0402_25V7K VDD VDD
VDD K8 VDD K8 CMD20 A13 A13
OPT@ OPT@ N1 N1
2 CLKC0 VDD CLKC0 VDD
J7 N9 J7 N9 CMD21 A8 A8
2
CLKC0# CK VDD CLKC0# CK VDD

CMDC3 K9 R9 CMDC3 K9 R9 CMD22 A6 A6
CKE/CKE0 VDD +VRAM_1.5VS CKE/CKE0 VDD +VRAM_1.5VS
CMD23 A11 A11
CMDC2 K1 A1 CMDC2 K1 A1
CMDC0 ODT/ODT0 VDDQ CMDC0 ODT/ODT0 VDDQ
+VRAM_1.5VS
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8 CMD24 A5 A5
CMDC30 J3 C1 CMDC30 J3 C1
CMDC15 RAS VDDQ CMDC15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9 CMD25 A3 A3
CMDC13 L3 D2 CMDC13 L3 D2
WE VDDQ WE VDDQ
1
310mAVDDQ E9 VDDQ E9 CMD26 BA2 BA2

RV128 F1 310mAVDDQ F1
1K_0402_1% DQSC1 VDDQ DQSC0
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2 CMD27 BA1 BA1
OPT@ DQSC2 C7 H9 DQSC3 C7 H9
DQSU VDDQ DQSU VDDQ
CMD28 A12 A12
2
+MEM_VREF_DQ2 CMDC2 RV134 1 OPT@ 2 10K_0402_5%

DQMC1 DQMC0 CMDC3 RV135 1 OPT@ 2 10K_0402_5%
E7 DML VSS A9 E7 DML VSS A9 CMDC5 RV136 1 10K_0402_5% CMD29 A10 A10
1
DQMC2 D3 B3 DQMC3 D3 B3 OPT@ 2

1 DMU VSS DMU VSS CMDC18 RV137 1 10K_0402_5%
RV122 CV303 OPT@ 2
VSS E1 VSS E1 CMDC19 RV138 1 2 10K_0402_5% CMD30 RAS* RAS*
1K_0402_1% 0.01U_0402_25V7K G8 G8 OPT@
OPT@ OPT@ DQSC#1 VSS DQSC#0 VSS
G3 DQSL VSS J2 G3 DQSL VSS J2 Not Available
2 DQSC#2 DQSC#3
B7 J8 B7 J8
2
DQSU VSS DQSU VSS

VSS M1 VSS M1 LOW HIGH
VSS M9 VSS M9
VSS P1 VSS P1
CMDC5 T2 P9 CMDC5 T2 P9
RESET VSS RESET VSS
VSS T1 VSS T1
ZQ4 L8 T9 ZQ5 L8 T9
B ZQ/ZQ0 VSS ZQ/ZQ0 VSS B
1
1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 Command Bit Default Pull-down
RV132 L1 B9 RV133 L1 B9
243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ
J9 NC/CE1 VSSQ D1 J9 NC/CE1 VSSQ D1 ODTx 10k
OPT@ L9 D8 OPT@ L9 D8
2
2
NCZQ1 VSSQ NCZQ1 VSSQ DDR3 CKEx 10k
VSSQ E2 VSSQ E2
VSSQ E8 VSSQ E8 RST 10k
VSSQ F9 VSSQ F9
CS* No Termination
VSSQ G1 VSSQ G1
<14> CLKC0 VSSQ G9 VSSQ G9
1
96-BALL 96-BALL
RV140 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
160_0402_1%
OPT@
2
<14> CLKC0# +VRAM_1.5VS

+VRAM_1.5VS
+VRAM_1.5VS
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0603_6.3V6M
CV156
CV155
CV153
CV154
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1 1 1 1 1 1 1 1
10U_0603_6.3V6M
CV263
CV265
OPT@ CV264
CV245
CV160
CV159
CV157
CV158
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 + + CV344
CV246
CV266
CV268
CV267 CV131 330U_B2_2.5VM_R15M

2 2 2 2 2 2 2 2 330U_2.5V_M @
2 2
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
2 2 2 2 2 2 2 2 @
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
A A

VGA_N13P VRAM Channel CL
5 4 3 2 1
5 4 3 2 1
VRAM DDR3 chips (1GB)

64Mx16 DDR3 *8==>1GB
D D
DQMC[7..0]
<14,20> DQMC[7..0]
CMDC[30..0] Mode D
<14,20> CMDC[30..0]
DQSC#[7..0]
Address 0..31 32..63
UV15 @ UV14 @
<14,20> DQSC#[7..0]
CMD0 CS0_L#
DQSC[7..0] +MEM_VREF_CA3 M8 E3 MDC39 +MEM_VREF_CA3 M8 E3 MDC63
<14,20> DQSC[7..0] VREFCA DQL0 VREFCA DQL0
+MEM_VREF_DQ3 H1 F7 MDC33 +MEM_VREF_DQ3 H1 F7 MDC58 CMD1
MDC[63..0] VREFDQ DQL1 MDC38 VREFDQ DQL1 MDC62
<14,20> MDC[63..0] DQL2 F2 DQL2 F2
CMDC9 N3 F8 MDC32 CMDC9 N3 F8 MDC59 CMD2 ODT_L
CMDC11 A0 DQL3 MDC36 Group4 CMDC11 A0 DQL3 MDC60 Group7
P7 A1 DQL4 H3 P7 A1 DQL4 H3
CMDC8 P3 H8 MDC34 CMDC8 P3 H8 MDC61 CMD3 CKE
CMDC25 A2 DQL5 MDC37 CMDC25 A2 DQL5 MDC57
N2 A3 DQL6 G2 N2 A3 DQL6 G2
CMDC24 A4 DQL7 CMDC24 A4 DQL7
P2 A5 P2 A5
CMDC22 R8 CMDC22 R8 CMD5 RST RST
+VRAM_1.5VS CMDC7 A6 MDC44 CMDC7 A6 MDC54
R2 A7 DQU0 D7 R2 A7 DQU0 D7
CMDC21 T8 C3 MDC43 CMDC21 T8 C3 MDC48 CMD6 A9 A9
CMDC6 A8 DQU1 MDC47 CMDC6 A8 DQU1 MDC52
1
CMDC29 L7 C2 MDC40 CMDC29 L7 C2 MDC50 CMD7 A7 A7

RV130 CMDC23 A10/AP DQU3 MDC45 Group5 CMDC23 A10/AP DQU3 MDC53 Group6
1K_0402_1% CMDC28 N7 A2 MDC42 CMDC28 N7 A2 MDC51 CMD8 A2 A2
OPT@ CMDC20 A12 DQU5 MDC46 CMDC20 A12 DQU5 MDC55
T3 A13 DQU6 B8 T3 A13 DQU6 B8
CMDC4 T7 A3 MDC41 CMDC4 T7 A3 MDC49 CMD9 A0 A0
2
+MEM_VREF_CA3 CMDC14 A14 DQU7 CMDC14 A14 DQU7

M7 A15/BA3 M7 A15/BA3
+VRAM_1.5VS +VRAM_1.5VS CMD10 A4 A4
1
1
RV129 CV304 CMDC12 M2 B2 CMDC12 M2 B2 CMD11 A1 A1
1K_0402_1% 0.01U_0402_25V7K CMDC27 BA0 VDD CMDC27 BA0 VDD
C OPT@ OPT@ CMDC26 CMDC26 C
2
M3 BA2 VDD G7 M3 BA2 VDD G7 CMD12 BA0 BA0
K2 K2
2
VDD VDD
VDD K8 VDD K8 CMD13 WE* WE*
VDD N1 VDD N1
CLKC1 J7 N9 CLKC1 J7 N9 CMD14 A15 A15
CLKC1# CK VDD CLKC1# CK VDD
CMDC19 K9 R9 CMDC19 K9 R9 CMD15 CAS* CAS*
CKE/CKE0 VDD +VRAM_1.5VS CKE/CKE0 VDD +VRAM_1.5VS
+VRAM_1.5VS
CMD16 CS0_H#
CMDC18 K1 A1 CMDC18 K1 A1
CMDC16 ODT/ODT0 VDDQ CMDC16 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8 CMD17
1
CMDC30 J3 C1 CMDC30 J3 C1
RV142 CMDC15 RAS VDDQ CMDC15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9 CMD18 ODT_H
1K_0402_1% CMDC13 L3 D2 CMDC13 L3 D2
OPT@ WE VDDQ WE VDDQ
310mAVDDQ E9 310mAVDDQ E9 CMD19 CKE_H
F1 F1
2
+MEM_VREF_DQ3 DQSC4 VDDQ DQSC7 VDDQ

F3 DQSL VDDQ H2 F3 DQSL VDDQ H2 CMD20 A13 A13
DQSC5 C7 H9 DQSC6 C7 H9
DQSU VDDQ DQSU VDDQ
1
1 CMD21 A8 A8
RV131 CV305
1K_0402_1% 0.01U_0402_25V7K DQMC4 E7 A9 DQMC7 E7 A9 CMD22 A6 A6
OPT@ OPT@ DQMC5 DML VSS DQMC6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3
2
E1 E1 CMD23 A11 A11
2
VSS VSS
VSS G8 VSS G8
DQSC#4 G3 J2 DQSC#7 G3 J2 CMD24 A5 A5
DQSC#5 DQSL VSS DQSC#6 DQSL VSS
VSS M1 VSS M1 CMD25 A3 A3
VSS M9 VSS M9
VSS P1 VSS P1 CMD26 BA2 BA2
CMDC5 T2 P9 CMDC5 T2 P9
RESET VSS RESET VSS
<14> CLKC1 VSS T1 VSS T1 CMD27 BA1 BA1
ZQ6 L8 T9 ZQ7 L8 T9
1
B B
CMD28 A12 A12
1
1
RV149 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 CMD29 A10 A10

160_0402_1% L1 B9 RV147 L1 B9
OPT@ RV146 NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ
J9 NC/CE1 VSSQ D1 J9 NC/CE1 VSSQ D1 CMD30 RAS* RAS*
2
243_0402_1% L9 D8 OPT@ L9 D8
2
<14> CLKC1# OPT@ NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 Not Available
2
VSSQ VSSQ
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 LOW HIGH
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
96-BALL 96-BALL
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0603_6.3V6M
CV164
CV163
CV161
CV162
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
CV168
CV167
CV165
CV166
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV247
CV269
CV271
OPT@ CV270
CV272
CV274
OPT@ CV273
CV248
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
A A

VGA_N13P VRAM Channel CH
5 4 3 2 1
A B C D E
+LCD_VDD +3VS
1
R109
100_0805_5% R108
100K_0402_5% +3VS
2
6
1 1
Q1A C228
1 W=80mils
2 0.047U_0402_25V7K
3
S
2N7002KDWH_SOT363-6
2 G
1 R110 2LCDPWR_GATE 2 Q17
1
68K_0402_5% 1 AO3413_SOT23
3
D
1
1 2 C230 +LCD_VDD
R78 CAM@ 0_0402_5% 4700P_0402_25V7K
@ LCD_ENVDD 2 W=80mils
<27> LCD_ENVDD 5
USB20_P11_R 1 USB20_P11 <28> Q1B
1 2 2 2N7002KDWH_SOT363-6
1
C233
4
0.1U_0402_10V7K
2
USB20_N11_R 4 3 USB20_N11 <28>
4 3 R112 2
L55 WCM-2012-900T_0805 100K_0402_5%
1 2
1
R96 CAM@ 0_0402_5%
Reserve for EMI request
For RF @
C256 47P_0402_50V8J
EMI request 1 2
W=20mils CAM@
R388 0.1U_0402_10V7K
+3VS 2 1 +3VS_LVDS_CAM 1 2
301LMA20T_0603 C225
2 JLVDS @ 2
2
1 1 1
2 USB20_N11_R 3
2 USB20_P11_R D84 AZ5125-02S.R7G_SOT23-3
3 3
4 4 @
5 INT_MIC_CLK
5 INT_MIC_CLK <38>
6 INT_MIC_DATA
6 INT_MIC_DATA <38>
7 7
8 +LCD_VDD +LCD_VDD
8
0.1U_0402_10V7K
4.7U_0805_10V4Z
9 1 1 2A For RF @
9 +3VS C226 C227 C258 47P_0402_50V8J
10 10
11 11 +LCD_VDD 1 2
12 LCD_EDID_CLK LCD_EDID_CLK <27>
12 LCD_EDID_DATA 2 2
13 13 LCD_EDID_DATA <27>
14 LCD_TXOUT0- LCD_TXOUT0- <27>
14 LCD_TXOUT0+
15 15 LCD_TXOUT0+ <27>
16 16
17 LCD_TXOUT1- +3VS
17 LCD_TXOUT1- <27>
18 LCD_TXOUT1+ LCD_TXOUT1+ <27>
18 LCD_TXOUT2-
19 19 LCD_TXOUT2- <27> 1
20 LCD_TXOUT2+ LCD_TXOUT2+ <27>
20 LCD_TXCLK- C232
21 21 LCD_TXCLK- <27>
22 LCD_TXCLK+ LCD_TXCLK+ <27> 0.1U_0402_10V7K
22 2
23 23
24 LED_PWM
24 BKOFF#_R
25 25
26 26
27 27
28 28
29 29 1.5A
30 30 +LCD_INV
3 3
GND 31 1 2
32 @
GND C257 47P_0402_50V8J
GND 33
GND 34 For RF
GND 35
STARC_111H30-000000-G4-R LED_PWM 1 2 PCH_PWM <27>

RB751V40_SC76-2 D17
1
R131
47K_0402_5%
2
1.5A
+LCD_INV B+
L2
2 1
1 1 FBMA-L11-201209-221LMA30T_0805
C234 C235
68P_0402_50V8J 0.1U_0402_25V6
2 2 BKOFF#_R 1 2 BKOFF# <40>
D15 RB751V40_SC76-2
1
R113
10K_0402_5%
2
4 4

LVDS
Custom 1.0
VCUAA
A B C D E
A B C D E
+3VS +3VS
+HDMI_5V_OUT
CV336 1 2 0.1U_0402_10V7K UMA_DVI_TXC+

<27> UMA_HDMI_TXC+
CV337 1 2 0.1U_0402_10V7K UMA_DVI_TXC- JHDMI1 45@
<27> UMA_HDMI_TXC-
HDMI Royalty
1
CV338 1 2 0.1U_0402_10V7K UMA_DVI_TXD0+
<27> UMA_HDMI_TX0+
<27> UMA_HDMI_TX0-
CV339 1 2 0.1U_0402_10V7K UMA_DVI_TXD0- RO0000003HM R184
2.2K_0402_5%
R185
2.2K_0402_5%
2
CV340 1 2 0.1U_0402_10V7K UMA_DVI_TXD1+ HDMI W/Logo + HDCP
<27> UMA_HDMI_TX1+
2
G
1 1
CV341 1 2 0.1U_0402_10V7K UMA_DVI_TXD1- HDMI W/O Logo: RO0000001HM
<27> UMA_HDMI_TX1-
3 1 HDMI_SCLK
<27> UMA_HDMI_CLK
2
<27> UMA_HDMI_TX2+
CV342 1 2 0.1U_0402_10V7K UMA_DVI_TXD2+ HDMI W/Logo: RO0000002HM
D
Q18
CV343 1 2 0.1U_0402_10V7K UMA_DVI_TXD2- HDMI W/Logo + HDCP: RO0000003HM BSH111_SOT23-3
<27> UMA_HDMI_TX2-
3 1 HDMI_SDATA
<27> UMA_HDMI_DATA
D
Q19
BSH111_SOT23-3
UMA_DVI_TXC+ 1 @ 2 HDMI_R_CK+
R160 0_0402_5% 2 1 +3VS
WCM-2012HS-900T_4P R571
4 3 +HDMI_5V_OUT 2.2K_0402_5%
4 3 R145
HDMI_HPD_U 1 2 HDMI_HPD_C HDMI_HPD
HDMI_HPD <27,29>
1 2 2 1K_0402_5%
1 2 C264 2
2
L8 0.1U_0402_10V7K R186 C265
1
UMA_DVI_TXC- 1 @ 2 HDMI_R_CK- U9 100K_0402_5% 0.1U_0402_10V7K
R199 0_0402_5% 1
OE#
HDMI_HPD 1
2 A Y 4
D53 F2
1
G
UMA_DVI_TXD0- 1 @ 2 HDMI_R_D0- 74AHCT1G125GW_SOT353-5 +5VS 2 1 +HDMI_5V_OUT_F 1 2 +HDMI_5V_OUT
R208 0_0402_5% 1
3
2 L9 PMEG2010AEH_SOD123 0.5A_8V_KMC3S050RY C259 2
1 1 2 2
0.1U_0402_10V7K
2
4 4 3 3
WCM-2012HS-900T_4P
UMA_DVI_TXD0+ 1 @ 2 HDMI_R_D0+
R210 0_0402_5%
HDMI_R_CK+ 1 R195 2
680_0402_5%
HDMI Connector
UMA_DVI_TXD1+ 1 @ 2 HDMI_R_D1+ HDMI_R_CK- 1 R197 2 JHDMI @
R207 0_0402_5% 680_0402_5% HDMI_HPD_C 19
WCM-2012HS-900T_4P HDMI_R_D1- 1 R198 HP_DET
2 +HDMI_5V_OUT 18 +5V
4 3 680_0402_5% 17
4 3 HDMI_R_D1+ 1 R202 HDMI_SDATA DDC/CEC_GND
2 16 SDA
680_0402_5% HDMI_SCLK 15
HDMI_R_D0+ 1 R201 SCL
1 1 2 2 2 14 Reserved
680_0402_5% 13
L10 HDMI_R_D0- 1 R203 HDMI_R_CK- CEC
2 12 CK-
UMA_DVI_TXD1- 1 @ 2 HDMI_R_D1- 680_0402_5% 11
R196 0_0402_5% HDMI_R_D2- 1 R205 HDMI_R_CK+ CK_shield
2 10 CK+
680_0402_5% HDMI_R_D0- 9
HDMI_R_D2+ 1 R206 D0-
2 8 D0_shield
UMA_DVI_TXD2- 1 @ 2 HDMI_R_D2- 680_0402_5% HDMI_R_D0+ 7
R192 0_0402_5% HDMI_R_D1- D0+
6
1
Q24 D D1-
L11 5
HDMI_R_D1+ D1_shield
1 2 +5VS 2 4 23
1 2 G HDMI_R_D2- D1+ GND
3 D2- GND 22
2 D2_shield GND 21
4 3 S 2N7002KW_SOT323-3 HDMI_R_D2+ 1 20
3
3 4 3 D2+ GND 3
WCM-2012HS-900T_4P TYCO_2041343-1~D
UMA_DVI_TXD2+ 1 @ 2 HDMI_R_D2+
R209 0_0402_5%
common CHOKE use 67ohm

5/30 change to 90ohm EMI request
4 4

HDMI Conn.
1.0
VCUAA
A B C D E
A B C D E
UH1A
+3VS
CMOS Setting, near DDR Door Placement near to YH1
JCMOS @ 2 1 NOGCLK@ PCH_RTCX1 A20 C38 LPC_AD0
RTCX1 FWH0 / LAD0 LPC_AD0 <40,41>
+RTCVCC RH23 1 2 PCH_RTCRST# 1 2 CH2 15P_0402_50V8J A38 LPC_AD1
FWH1 / LAD1 LPC_AD1 <40,41>
LPC
20K_0402_5% PCH_RTCX2 C20 B37 LPC_AD2 SERIRQ 2 1
RTCX2 FWH2 / LAD2 LPC_AD2 <40,41>
1
10M_0402_5%
NOGCLK@
CH4 1 2 <34> PCH_RTCX1_R 1 GCLK@ 2 PCH_RTCX1 FWH3 / LAD3 C37 LPC_AD3
LPC_AD3 <40,41>
RH31 10K_0402_5%
1U_0402_6.3V6K RH26 0_0402_5% YH1 PCH_RTCRST# D20 RTCRST#
RH2
32.768KHZ_12.5P_1TJF125DP1A000D D36 LPC_FRAME#
FWH4 / LFRAME# LPC_FRAME# <40,41>
NOGCLK@ PCH_SRTCRST# G22
1
SRTCRST#
iME Setting. E36
2
LDRQ0#
RTC
JME @ 2 1 NOGCLK@ SM_INTRUDER# K22 K36
RH24 1 INTRUDER# LDRQ1# / GPIO23
2PCH_SRTCRST# 1 2 CH3 15P_0402_50V8J
20K_0402_5% PCH_INTVRMEN C17 V5 SERIRQ
INTVRMEN SERIRQ SERIRQ <40>
CH5 1 2
1U_0402_6.3V6K AZ_BITCLK_HD
1 SATA_PRX_C_DTX_N0 1
SATA0RXN AM3 SATA_PRX_C_DTX_N0 <33>
RH27 1 2 33_0402_5% AZ_BITCLK N34 AM1 SATA_PRX_C_DTX_P0
<38> AZ_BITCLK_HD HDA_BCLK SATA0RXP SATA_PRX_C_DTX_P0 <33>
SATA_PTX_DRX_N0
SATA 6G
AP7
Integrated SUS 1.05V VRM Enable 1 AZ_SYNC L34
SATA0TXN
AP5 SATA_PTX_DRX_P0
SATA_PTX_DRX_N0 <33> HDD
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0 <33>
High - Enable Internal VRs @ CH101 PCH_SPKR T10 AM10 SATA_PRX_C_DTX_N1
<38> PCH_SPKR SPKR SATA1RXN SATA_PRX_C_DTX_N1 <34>
PCH_INTVRMEN (must be always pulled high) 10P_0402_50V8J AM8 SATA_PRX_C_DTX_P1
2 SATA1RXP SATA_PRX_C_DTX_P1 <34>
RH30 1 2 33_0402_5% AZ_RST# K34 AP11 SATA_PTX_DRX_N1
<38> AZ_RST_HD# HDA_RST# SATA1TXN
AP10 SATA_PTX_DRX_P1
SATA_PTX_DRX_N1 <34> mSATA
SATA1TXP SATA_PTX_DRX_P1 <34>
+RTCVCC AZ_SDIN0_HD E34 AD7
<38> AZ_SDIN0_HD HDA_SDIN0 SATA2RXN
SATA2RXP AD5
RH12 1 2 SM_INTRUDER# G34 AH5
1M_0402_5% HDA_SDIN1 SATA2TXN
SATA2TXP AH4
RH33 1 2 PCH_INTVRMEN C34
330K_0402_5% HDA_SDIN2
IHDA
+3VS
PCH_SPKR SATA3RXN AB8
+3VALW_PCH 2 @ 1 A34 AB10
@ High = Enabled "No Reboot Mode" RH272 1K_0402_5% HDA_SDIN3 SATA3RXP
AF3 +3VS
SATA3TXN
1 2 PCH_SPKR Low = Disabled (Default) AF1
RH36 1K_0402_5% * <38> AZ_SDOUT_HD
RH32 1 2 33_0402_5% AZ_SDOUT A36 HDA_SDO
SATA3TXP
PCH_GPIO21 RH34 2 1 10K_0402_5%
SATA
SATA4RXN Y7
SATA4RXP Y5
1 @ 2 C36 AD3
<40> PWRME_CTRL HDA_DOCK_EN# / GPIO33 SATA4TXN
RH25 0_0402_5% AD1 PCH_GPIO19 RH28 1 2 10K_0402_5%
SATA4TXP
N32 HDA_DOCK_RST# / GPIO13
SATA5RXN Y3
Y1 SATA_LED# RH29 2 1 10K_0402_5%
SATA5RXP
HDA_SDO Change Net name due to
this function is high active PCH_JTAG_TCK J3
SATA5TXN AB3
AB1
JTAG_TCK SATA5TXP
ME debug mode,
T74 PAD PCH_JTAG_TMS H7 Y11
this signal has a weak internal pull down JTAG_TMS SATAICOMPO
JTAG
2 T75 PAD PCH_JTAG_TDI SATAICOMP 2
*Low = Disable (default)
High = Enable (flash descriptor security overide)
K5 JTAG_TDI SATAICOMPI Y10 1
RH43
2
37.4_0402_1%
+1.05VS_VCC_SATA
T88 PAD PCH_JTAG_TDO H1 JTAG_TDO
SATA3RCOMPO AB12
HDA_SYNC SATA3COMPI AB13 SATA3_COMP 1

RH48
2
49.9_0402_1%
+1.05VS_SATA3
*This signal has a weak internal pull

H=>On Die PLL is supplied by 1.5V
down
PCH_SPICLK T3 SPI_CLK SATA3RBIAS AH1 RBIAS_SATA3 1 2
RH41 750_0402_1%
L=>On Die PLL is supplied by 1.8V PCH_SPICS0# Y14 SPI_CS0#
Need to pull high for Chief River Mobile platform PCH_SPICS1# T1 SPI_CS1#
SPI
+3VALW_PCH 2 1 AZ_SYNC P3 SATA_LED#
RH55 1K_0402_5% SATALED#
BOOT BIOS Strap Bit 0
PCH_SPIDI V4 V14 PCH_GPIO21
+5VS SPI_MOSI SATA0GP / GPIO21
If use GCLK, please delete DH1
PCH_SPIDO U3 P1 PCH_GPIO19
SPI_MISO SATA1GP / GPIO19 PCH_GPIO19 <28>
2
G
QH1
1 2 AZ_SYNC_R 3 1 PANTHER-POINT_FCBGA989 HM77R1@
<38> AZ_SYNC_HD
RH54 33_0402_5%
S
1 2 BSS138_NL_SOT23-3 +RTCVCC +RTCBATT

RH56 1M_0402_5% 1 @ 2
0.1U_0402_10V7K
RB751V-40_SOD323-2
RH274 0_0402_5%
1
CH8
1
DH7
+3VS 2
DH1
RB751V-40_SOD323-2
+3VS
3
For RF 3
47P_0402_50V8J
SPI ROM for BIOS & ME (4MByte )
2
1 2
1
SPI ROM for Win8 (2MByte ) @ CH20 +RTCBATT +3VL
1
47P_0402_50V8J UH3 0.1U_0402_10V7K

CH19 CH6 8 4
4MB ROM P/N: UH4 1 2
@ 0.1U_0402_10V7K VCC VSS PCH_SPICS1# CH100
SA00003K800 1 8
2
2 PCH_SPIDO 1 CS# VCC

3 W 2 PCH_SPI1_DO 2 SO HOLD# 7 RH267 33_0402_5%
7
SA00004LI00 RH269 33_0402_5% +3VS 3
4
WP# SCLK 6
5
PCH_SPI1_CLK
PCH_SPI1_DI
1
1
2
2
PCH_SPICLK
PCH_SPIDI
HOLD GND SI RH271 33_0402_5%
For RF
PCH_SPICS0# 1 MX25L1606EM2I-12G_SO8
S
PCH_SPICLK PCH_SPI0_CLK
1
RH66
2
33_0402_5%
6 C 2MB ROM P/N: Un-mount for reduce power consumption at S0, S3 state
PCH_SPIDI PCH_SPI0_DI PCH_SPI0_DO PCH_SPIDO PCH_SPI0_CLK PCH_SPI1_CLK
1
RH67
2
33_0402_5%
5 D Q 2 1
RH68
2
33_0402_5%
for EMI SA000041N00 for EMI
1
1
MX25L3205DM2I-12G SO8
RH65
SA00003FO10 RH69
+3VALW_PCH +3VALW_PCH +3VALW_PCH
Socket: SP07000F500/SP07000H900 10_0402_5% 10_0402_5%
2
RH46 RH45 RH38
Please place U13 & U4 close to U2 PCH,
2
2
1 1 200_0402_5% 200_0402_5% 200_0402_5%
CH7 CH21 @ @ @
please place RH66, RH67, RH68 near UH3 10P_0402_50V8J 10P_0402_50V8J
1
PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI
Please place RH267 near RH66, Please place RH271 near RH67, 2 2
2
Please place RH269 near RH68. RH44 RH39 RH40
100_0402_1% 100_0402_1% 100_0402_1%
@ @ @
1
4 4
1 @ 2 PCH_JTAG_TCK
RH50 51_0402_1%

PCH_HDA/JTAG/SATA/SPI/LPC
Custom 1.0
VCUAA
A B C D E
A B C D E
UH1B
+3VALW_PCH 2 RH72 1 2.2K_0402_5% +3VS
PCIE_PRX_C_LANTX_N1 BG34 2 RH70 1 2.2K_0402_5% RH102 4.7K_0402_5%
<35> PCIE_PRX_C_LANTX_N1 PERN1
5
PCIE_PRX_C_LANTX_P1 BJ34 E12 PCH_SMBALERT# RH103 4.7K_0402_5%
<35> PCIE_PRX_C_LANTX_P1 PERP1 SMBALERT# / GPIO11
LAN <35> PCIE_PTX_C_LANRX_N1 CH13 2 1 0.1U_0402_10V7K PCIE_PTX_LANRX_N1 AV32
CH11 2 PETN1
<35> PCIE_PTX_C_LANRX_P1 1 0.1U_0402_10V7K PCIE_PTX_LANRX_P1 AU32 PETP1 SMBCLK H14 PCH_SMBCLK PCH_SMBDATA 3 4 PM_SMBDATA <11,12,34,41>
2
PCIE_PRX_WLANTX_N2 BE34 C9 PCH_SMBDATA
<34> PCIE_PRX_WLANTX_N2 PERN2 SMBDATA QH3B
PCIE_PRX_WLANTX_P2 BF34
<34> PCIE_PRX_WLANTX_P2 PERP2
WLAN <34> PCIE_PTX_C_WLANRX_N2 CH14 2 1 0.1U_0402_10V7K PCIE_PTX_WLANRX_N2 BB32 PETN2
PCH_SMBCLK 6 12N7002KDWH_SOT363-6 PM_SMBCLK <11,12,34,41>
<34> PCIE_PTX_C_WLANRX_P2 CH17 2 1 0.1U_0402_10V7K PCIE_PTX_WLANRX_P2 AY32 PETP2
SMBUS
SML0ALERT# / GPIO60 A12 DRAMRST_CNTRL_PCH DRAMRST_CNTRL_PCH <11,7> QH3A
BG36 PERN3
BJ36 C8 PCH_SMLCLK0 2N7002KDWH_SOT363-6
1 PERP3 SML0CLK 1
AV34 PETN3
AU34 G12 PCH_SMLDATA0 +3VALW_PCH 2 RH78 1 2.2K_0402_5% +3VS
PETP3 SML0DATA
BF36 PERN4 2 RH74 1 2.2K_0402_5%
5
BE36 PERP4
AY34 C13 LAN_EN
PETN4 SML1ALERT# / PCHHOT# / GPIO74 LAN_EN <35>
BB34 PCH_SMLDATA1 3 4
PETP4 EC_SMB_DA2 <13,40>
E14 PCH_SMLCLK1
SML1CLK / GPIO58
2
PCI-E*
BG37 PERN5 QH4B
BH37 M16 PCH_SMLDATA1
PERP5 SML1DATA / GPIO75
AY36 PETN5
PCH_SMLCLK1 6 12N7002KDWH_SOT363-6EC_SMB_CK2 <13,40>
BB36 PETP5
QH4A
BJ38 PERN6
BG38 2N7002KDWH_SOT363-6
PERP6
Controller
AU36 PETN6 CL_CLK1 M7
AV36 PETP6
+3VS
Control Link only for support Intel IAMT.
Link
BG40 PERN7 CL_DATA1 T11
BJ40 PERP7
AY40 +3VALW_PCH
PCH_GPIO20 PETN7
1 2 BB40 PETP7 CL_RST1# P10
RH99 10K_0402_5%
BE38 PCH_SMBALERT# RH2621 2 10K_0402_5%
CLKREQ_WLAN# PERN8
1 2 BC38 PERP8
RH104 10K_0402_5% AW38 DRAMRST_CNTRL_PCH RH76 1 2 1K_0402_5%
PETN8
AY38 PETP8
1 2 CLKREQ_LAN# LAN_EN RH75 1 2 10K_0402_5%
RH95 10K_0402_5% M10 CLK_REQ_VGA# CLK_REQ_VGA# <13>
CLK_LAN# PEG_A_CLKRQ# / GPIO47 PCH_SMLCLK0 RH73 2
Intel Spec: <35> CLK_LAN# Y40 CLKOUT_PCIE0N 1 2.2K_0402_5%
LAN CLK_LAN Y39
PCIECLK_RQ0# is suspend well, <35> CLK_LAN CLKOUT_PCIE0P
AB37 CLK_PCIE_VGA# PCH_SMLDATA0 RH77 2 1 2.2K_0402_5%
CLKOUT_PEG_A_N CLK_PCIE_VGA# <13>
2 but we pull high to +3VS CLKREQ_LAN# CLK_PCIE_VGA VGA 2
CLOCKS
<35> CLKREQ_LAN# J2 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P AB38 CLK_PCIE_VGA <13>
for LAN en/disable function
CLK_WLAN# AB49 AV22 CLK_CPU_DMI# +3VALW_PCH
<34> CLK_WLAN# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# <5>
WLAN CLK_WLAN AB47 AU22 CLK_CPU_DMI @
<34> CLK_WLAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <5>
2 1 CLK_REQ_VGA# 2 1
CLKREQ_WLAN# M1 RH275 10K_0402_5% RH89 10K_0402_5%
<34> CLKREQ_WLAN# PCIECLKRQ1# / GPIO18
CLKOUT_DP_N AM12
CLKOUT_DP_P AM13
AA48 CLKOUT_PCIE2N
AA47 CLKOUT_PCIE2P
BF18 PCH_CLK_DMI# PCH_CLK_DMI# RH79 1 2 10K_0402_5%
PCH_GPIO20 CLKIN_DMI_N PCH_CLK_DMI PCH_CLK_DMI RH82 1
V10 PCIECLKRQ2# / GPIO20 CLKIN_DMI_P BE18 2 10K_0402_5%
CLKIN_GND1# RH85 1 2 10K_0402_5%

Y37 BJ30 CLKIN_GND1# CLKIN_GND1 RH86 1 2 10K_0402_5%
CLKOUT_PCIE3N CLKIN_GND1_N CLKIN_GND1
Y36 CLKOUT_PCIE3P CLKIN_GND1_P BG30
CLK_DOT# RH80 1 2 10K_0402_5%
PCH_GPIO25 A8 CLK_DOT RH81 1 2 10K_0402_5%
PCIECLKRQ3# / GPIO25 CLK_DOT#
CLKIN_DOT_96N G24
E24 CLK_DOT From Clock Gen. CLK_SATA# RH83 1 2 10K_0402_5%
+3VALW_PCH CLKIN_DOT_96P CLK_SATA RH84 1
Y43 CLKOUT_PCIE4N 2 10K_0402_5%
Y45 CLKOUT_PCIE4P
AK7 CLK_SATA# CLK_14M_PCH RH87 1 2 10K_0402_5%
LVDS_SEL PCH_GPIO26 CLKIN_SATA_N CLK_SATA
1 2 L12 PCIECLKRQ4# / GPIO26 CLKIN_SATA_P AK5
RH116 10K_0402_5%
1 2 PCH_GPIO26 V45 K45 CLK_14M_PCH

For EMI
RH107 10K_0402_5% CLKOUT_PCIE5N REFCLK14IN
V46 CLKOUT_PCIE5P @
1 2 PCH_GPIO25 PCH_GPIO44 L14 H45 CLK_PCILOOP CLK_PCILOOP 2 @ 1 2 1
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCILOOP <28>
RH110 10K_0402_5% RH124 10_0402_5% CH28 22P_0402_50V8J
3 3
1 2 PCH_GPIO44 AB42 V47 PCH_X1
RH112 10K_0402_5% CLKOUT_PEG_B_N XTAL25_IN PCH_X2
AB40 CLKOUT_PEG_B_P XTAL25_OUT V49
1 2 PANEL_SEL PASSWORD_CLEAR# E6
RH119 10K_0402_5% PEG_B_CLKRQ# / GPIO56 RH37
1
JPW Y47 XCLK_RCOMP 1 2 +1.05VS_VCCDIFFCLKN 1 2 PCH_X1

XCLK_RCOMP <34> PCH_X1_R
1 2 PASSWORD_CLEAR# @ V40 RH115 90.9_0402_1% 0_0402_5%
RH114 10K_0402_5% CLKOUT_PCIE6N GCLK@
V42
2
CLKOUT_PCIE6P
LVDS_SEL T13 Placement near to YH2
PCIECLKRQ6# / GPIO45
V38 K43 CLK_FLEX0 T72 PAD
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 NOGCLK@
FLEX CLOCKS
V37 CLKOUT_PCIE7P
F47 PCH_48MCLK 1 2 RH117 2 1 1M_0402_5%
CLKOUTFLEX1 / GPIO65 CLK_48M_CR <36>
PANEL_SEL K12 RH1 22_0402_5%
PCIECLKRQ7# / GPIO46
H47 CLK_FLEX2 T73 PAD NOGCLK@YH2 25MHZ_20PF_7V25000016
CLKOUTFLEX2 / GPIO66
AK14 CLKOUT_ITPXDP_N
AK13 K49 DGPU_PRSNT# PCH_X1 1 3 PCH_X2
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 1 3
GND GND
1 1
PANTHER-POINT_FCBGA989 HM77R1@ Compal common design SW request to CH26 CH27
2 4
add DGPU_Present on this GPIO67 27P_0402_50V8J 27P_0402_50V8J
LVDS_SEL PANEL_SEL NOGCLK@ 2 2 NOGCLK@
DGPU_PRSNT#
LVDS_SEL H L PANEL_SEL H L
DGPU_PRSNT# H L UMA@
Single DGPU_PRSNT# 1 2 +3VS
Channel Dual Channel LVDS EDP RH227 10K_0402_5%
4 (Default) 4
M/B SKU UMA DIS/OPT 1 2

RH261 10K_0402_5%
OPT@

PCH_PCI-E/SMBUS/CLK
Custom 1.0
VCUAA
A B C D E
A B C D E
UH1C
<6> DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

+3VALW_PCH DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <6>
<6> DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <6>
<6> DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
<6> DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
2 1 PCH_SUSPWRDN#_R BC12 FDI_CTX_PRX_N4
FDI_RXN4 FDI_CTX_PRX_N4 <6>
RH234 10K_0402_5% <6> DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5
DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <6>
<6> DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <6> 1
2 1 RI# <6> DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7
DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <6>
RH157 10K_0402_5% <6> DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 BJ20 DMI3RXP FDI_CTX_PRX_P0
FDI_RXP0 BG14 FDI_CTX_PRX_P0 <6>
2 1 PCH_LOW_BAT# DMI_PTX_CRX_N0 AW24 BB14 FDI_CTX_PRX_P1
<6> DMI_PTX_CRX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <6>
RH155 10K_0402_5% DMI_PTX_CRX_N1 AW20 BF14 FDI_CTX_PRX_P2
DMI_PTX_CRX_N2 BB18 BG13 FDI_CTX_PRX_P3
DMI_PTX_CRX_N3 AV18 BE12 FDI_CTX_PRX_P4
DMI
FDI
BG12 FDI_CTX_PRX_P5 PCH_DPWROK 1 @ 2 PCH_RSMRST#
FDI_RXP5 FDI_CTX_PRX_P5 <6>
DMI_PTX_CRX_P0 AY24 BJ10 FDI_CTX_PRX_P6 RH128 0_0402_5%
<6> DMI_PTX_CRX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <6>
DMI_PTX_CRX_P1 AY20 BH9 FDI_CTX_PRX_P7
<6> DMI_PTX_CRX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <6>
2 1 PCH_RSMRST# DMI_PTX_CRX_P2 AY18 Stuff R222 if do not support DeepSX state
<6> DMI_PTX_CRX_P2 DMI2TXP
RH163 10K_0402_5% DMI_PTX_CRX_P3 AU18
<6> DMI_PTX_CRX_P3 DMI3TXP
AW16 FDI_INT
FDI_INT FDI_INT <6>
2 1 PM_PWROK
RH279 10K_0402_5% +1.05VS_PCH 1 2 DMI_COMP BJ24 AV12 FDI_FSYNC0
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <6>
RH126 49.9_0402_1%
2 @ 1 SYS_PWROK BG25 BC10 FDI_FSYNC1
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <6>
RH280 10K_0402_5%
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 +RTCVCC
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <6>
RH127 750_0402_1%
BB10 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 <6>
DSWVREN RH150 2 1 330K_0402_5%
Reserve 0 ohm for cost down plan
RH151 2 @ 1 330K_0402_5%
2010/08/25 0_0402_5% DSWVREN
Reserve this signal to EC by SW demand DSWVRMEN A18
1 RH2812
2011/10/18a
System Power Management

+3VS @ SUSACK#_R PCH_DPWROK
<40> SUSACK# 1 2 C12 SUSACK# DPWROK E22 DSWVREN must be always pulled high to +RTCVCC
0.1U_0402_10V7K RH133 0_0402_5%
1 2 DSWVREN - Internal Deep Sleep 1.05V regulator
CH103 @ 1 2 XDP_DBRESET# K3 B9 EC_SWI#
+3VS SYS_RESET# WAKE# EC_SWI# <35> * H：Enable
5
UH5 RH47 1K_0402_5%

2
1 L：Disable 2
P
<40,49> VGATE IN1

4 SYS_PWROK P12 N3 PCH_GPIO32
PM_PWROK O SYS_PWROK CLKRUN# / GPIO32
<40,5> PM_PWROK 2 IN2
G
SN74AHC1G08DCKR_SC70-5 PM_PWROK L22 G8 SUS_STAT# T76 PAD

3
@ PWROK SUS_STAT# / GPIO61

32.768 KHz
L10 APWROK SUSCLK / GPIO62 N14 CLK_EC <40> Follow EC check list demand,
but don't implement CLKRUN# this fuction
DRAMPWROK B13 D10 PM_SLP_S5#
<5> DRAMPWROK DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# <40>
SUSACK#_R 2 @ 1 PCH_SUSPWRDN#_R +3VS
RH282 0_0402_5% PCH_RSMRST# C21 H4 PM_SLP_S4#
<40> PCH_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <40>
PCH_GPIO32 RH2561 @ 2 8.2K_0402_5%
Stuff R137 if EC does not want to 1 @ 2 PCH_SUSPWRDN#_R K16 F4 PM_SLP_S3#
<40> PCH_SUSPWRDN# SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# <40>
RH132 0_0402_5%
involve in the handshake mechanism 1 2
for the DeepSX state entry and exit <40> PBTN_OUT# PBTN_OUT# E20 G10 PM_SLP_A# T77 PAD RH160 10K_0402_5%
PWRBTN# SLP_A#
1 2 PCH_ACIN H20 G16 PM_SLP_SUS# T78 PAD +3VALW_PCH

+3VALW_PCH ACPRESENT / GPIO31 SLP_SUS#
RH161 330K_0402_5%
DH2 PCH_LOW_BAT# E10 AP14 H_PM_SYNC EC_SWI# RH1591 2 10K_0402_5%

BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <5>
<40,44> ACIN 1 2
CH751H-40PT_SOD323-2 RI# A10 K14 PCH_GPIO29 PCH_GPIO29 RH1621 @ 2 10K_0402_5%

RI# SLP_LAN# / GPIO29
Reserve this signal to EC by SW demand PANTHER-POINT_FCBGA989 HM77R1@

3 3
2011/10/18a
DH5
PM_PWROK 2 1 PCH_RSMRST#
CH751H-40PT_SOD323-2
DH6
<43,45> POK 1 2
CH751H-40PT_SOD323-2
4 4

PCH_DMI/FDI/PM
Custom 1.0
VCUAA
A B C D E
A B C D E
UH1D
1 2 EC_ENBKL EC_ENBKL J47 AP43
<40> EC_ENBKL L_BKLTEN SDVO_TVCLKINN +3VS
RH125 100K_0402_5% LCD_ENVDD M45 AP45
<22> LCD_ENVDD L_VDD_EN SDVO_TVCLKINP
PCH_PWM P45 AM42
<22> PCH_PWM L_BKLTCTL SDVO_STALLN
SDVO_STALLP AM40
1
<22> LCD_EDID_CLK LCD_EDID_CLK T40
LCD_EDID_DATA L_DDC_CLK RH140 RH139
<22> LCD_EDID_DATA K47 L_DDC_DATA SDVO_INTN AP39
AP40 2.2K_0402_5% 2.2K_0402_5%
LCTL_CLK SDVO_INTP
T45 L_CTRL_CLK
LCTL_DATA P39
2
1 L_CTRL_DATA 1
1 2 LVDS_IBG AF37 P38
LVD_IBG SDVO_CTRLCLK UMA_HDMI_CLK <23>
RH143 2.37K_0402_1% AF36 M39
LVD_VBG SDVO_CTRLDATA UMA_HDMI_DATA <23>
T79 PAD
AE48 LVD_VREFH
AE47 LVD_VREFL DDPB_AUXN AT49
AT47 @
DDPB_AUXP HDMI_HPD HDMI_HPD
DDPB_HPD AT40 HDMI_HPD <23,29> 2 1
LCD_TXCLK- AK39 100K_0402_5%
<22> LCD_TXCLK- LVDSA_CLK#
LVDS
LCD_TXCLK+ AK40 AV42 UMA_HDMI_TX2- RH254
<22> LCD_TXCLK+ LVDSA_CLK DDPB_0N UMA_HDMI_TX2- <23>
AV40 UMA_HDMI_TX2+
+3VS DDPB_0P UMA_HDMI_TX2+ <23>
LCD_TXOUT0- AN48 AV45 UMA_HDMI_TX1-
<22> LCD_TXOUT0- LVDSA_DATA#0 DDPB_1N UMA_HDMI_TX1- <23>
LCD_TXOUT1- AM47 AV46 UMA_HDMI_TX1+
<22> LCD_TXOUT1- UMA_HDMI_TX1+ <23> HDMI
Digital Display Interface

LCD_TXOUT2- LVDSA_DATA#1 DDPB_1P UMA_HDMI_TX0-
<22> LCD_TXOUT2- AK47 LVDSA_DATA#2 DDPB_2N AU48 UMA_HDMI_TX0- <23>
2 1 LCTL_CLK AJ48 AU47 UMA_HDMI_TX0+
LVDSA_DATA#3 DDPB_2P UMA_HDMI_TX0+ <23>
RH145 2.2K_0402_5% AV47 UMA_HDMI_TXC-
DDPB_3N UMA_HDMI_TXC- <23>
LCD_TXOUT0+ AN47 AV49 UMA_HDMI_TXC+
<22> LCD_TXOUT0+ LVDSA_DATA0 DDPB_3P UMA_HDMI_TXC+ <23>
2 1 LCTL_DATA LCD_TXOUT1+ AM49
<22> LCD_TXOUT1+ LVDSA_DATA1
RH146 2.2K_0402_5% LCD_TXOUT2+ AK49
<22> LCD_TXOUT2+ LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
2 1 LCD_EDID_CLK P42
RH149 2.2K_0402_5% DDPC_CTRLDATA
AF40 LVDSB_CLK#
2 1 LCD_EDID_DATA AF39 AP47
RH148 2.2K_0402_5% LVDSB_CLK DDPC_AUXN
DDPC_AUXP AP49
AH45 AT38 RH141 2 1 100K_0402_5%
@ UMA_CRT_DATA LVDSB_DATA#0 DDPC_HPD
2 1 AH47 LVDSB_DATA#1
RH142 2.2K_0402_5% AF49 AY47
LVDSB_DATA#2 DDPC_0N
AF45 LVDSB_DATA#3 DDPC_0P AY49
2 @ 1 UMA_CRT_CLK AY43
RH144 2.2K_0402_5% DDPC_1N
AH43 LVDSB_DATA0 DDPC_1P AY45
AH49 LVDSB_DATA1 DDPC_2N BA47
2 2
AF47 LVDSB_DATA2 DDPC_2P BA48
AF43 LVDSB_DATA3 DDPC_3N BB47
DDPC_3P BB49
N48 CRT_BLUE DDPD_CTRLCLK M43

P49 CRT_GREEN DDPD_CTRLDATA M36
T49 CRT_RED
DDPD_AUXN AT45
CRT
UMA_CRT_CLK T39 AT43
UMA_CRT_DATA CRT_DDC_CLK DDPD_AUXP RH255
M40 CRT_DDC_DATA DDPD_HPD BH41 2 1 100K_0402_5%
DDPD_0N BB43
Disable CRT, use 5% M47 CRT_HSYNC DDPD_0P BB45
M49 CRT_VSYNC DDPD_1N BF44
DDPD_1P BE44
DDPD_2N BF42
1 2 CRT_IREF T43 BE42
RH138 1K_0402_5% DAC_IREF DDPD_2P
T42 CRT_IRTN DDPD_3N BJ42
DDPD_3P BG42
PANTHER-POINT_FCBGA989 HM77R1@
3 3
4 4

PCH_CRT/LVDS/HDMI
Custom 1.0
VCUAA
A B C D E
A B C D E
+3VS
For Optimus
8.2K_0402_5% RH318
1 2 PCH_GPIO4
8.2K_0402_5% RH319 UH1E

1 2 PCH_GPIO52 AY7 +3VS
RSVD1 OPT@
RSVD2 AV7
8.2K_0402_5% RH320 BG26 AU3 1 2
PCH_GPIO2 TP1 RSVD3 CH30 0.1U_0402_10V7K
1 2 BJ26 TP2 RSVD4 BG4
5
BH25 UH6
8.2K_0402_5% RH321 TP3 PLT_RST#
BJ16 AT10 1
P
PCH_GPIO53 TP4 RSVD5 IN1 @
1 2 BG16 TP5 RSVD6 BC8 O 4 1 2 PLTRST_VGA# <13>
AH38 DGPU_RST# 2 RH286 0_0402_5%
TP6 IN2
G
1 8.2K_0402_5% RH324 1
AH37 TP7 RSVD7 AU2
1
1 2 PCH_GPIO51 AK43 AT4 2 SN74AHC1G08DCKR_SC70-5
3
TP8 RSVD8
2
AK45 AT3 CH12 OPT@
8.2K_0402_5% RH323 TP9 RSVD9 RH287 0.47U_0402_6.3V6K RH288
C18 TP10 RSVD10 AT1
1 2 PCI_PIRQA# N30 AY3 1K_0402_5% OPT@ 100K_0402_5%
TP11 RSVD11 @ 1 OPT@
H3 AT5
2
8.2K_0402_5% RH325 TP12 RSVD12
AH12 AV3
1
PCI_PIRQB# TP13 RSVD13
1 2 AM4 TP14 RSVD14 AV1
AM5 TP15 RSVD15 BB1
8.2K_0402_5% RH322 Y13 BA3
PCI_PIRQC# TP16 RSVD16
1 2 K24 TP17 RSVD17 BB5
L24 TP18 RSVD18 BB3
8.2K_0402_5% RH299 AB46 BB7 PLT_RST#
PCH_GPIO55 TP19 RSVD19
2 1 AB45 TP20 RSVD20 BE8
RSVD
RSVD21 BD4
2
8.2K_0402_5% RH305 BF6
PCH_GPIO3 RSVD22 RH173
1 2
B21 AV5 NV_ALE 100K_0402_5%
8.2K_0402_5% RH326 TP21 RSVD23
M20 TP22 RSVD24 AV10
2 1 PCH_GPIO5 AY16
1
TP23
BG46 TP24 RSVD25 AT8
8.2K_0402_5% RH290
1 2 PCI_PIRQD# AY5
RSVD26
RSVD27 BA2
10K_0402_5% RH175 U3RXDN1 BE28
<37> U3RXDN1 USB3Rn1
1 2 DGPU_RST# U3RXDN2 BC30 AT12
<37> U3RXDN2 USB3Rn2 RSVD28
BE32 USB3Rn3 RSVD29 BF3
10K_0402_5% RH176 BJ32
DGPU_PWR_EN U3RXDP1 USB3Rn4
1 2 <37> U3RXDP1 BC28 USB3Rp1
U3RXDP2 BE30
<37> U3RXDP2 USB3Rp2
BF32 USB3Rp3
BG32 C24 USB20_N0
2 USB3Rp4 USBP0N USB20_N0 <37> 2
U3TXDN1 AV26 A24 USB20_P0 USB-Right1 Intel Anti-Theft Techonlogy
<37> U3TXDN1 USB3Tn1 USBP0P USB20_P0 <37>
U3TXDN2 BB26 C25 USB20_N1
<37> U3TXDN2 USB3Tn2 USBP1N USB20_N1 <37>
AU28 B25 USB20_P1 USB-Right2 High=Endabled
USB3Tn3 USBP1P USB20_P1 <37>
AY30 C26 USB20_N2 NV_ALE
USB3Tn4 USBP2N USB20_N2 <37>
U3TXDP1 AU26 A26 USB20_P2 USB-Left Low=Disable(floating)
<37> U3TXDP1
<37> U3TXDP2
U3TXDP2 AY26
USB3Tp1
USB3Tp2
USBP2P
USBP3N K28 USB20_N3
USB20_P2
USB20_N3
<37>
<36>
*
1K_0402_5% RH291 AV28 H28 USB20_P3 CardReader
USB3Tp3 USBP3P USB20_P3 <36> +1.8VS
1 2 DGPU_PWR_EN AW30 EHCI 1 E28
@ USB3Tp4 USBP4N
USBP4P D28
C28 NV_ALE 1 @ 2
USBP5N RH164 1K_0402_5%
USBP5P A28
USBP6N C29
USBP6P B29
PCI_PIRQA# K40 N28
PCI_PIRQB# PIRQA# USBP7N
K38 PIRQB# USBP7P M28
PCI
PCI_PIRQC# H38 L30 USB20_N8 T18 PAD @
PCI_PIRQD# PIRQC# USBP8N USB20_P8 T19 PAD @
G38 PIRQD# USBP8P K30
G30 USB20_N9
USBP9N USB20_N9 <34>
DGPU_RST# C46 E30 USB20_P9 BT
REQ1# / GPIO50 USBP9P USB20_P9 <34>
USB
PCH_GPIO52 C44 C30
DGPU_PWR_EN REQ2# / GPIO52 USBP10N
<42,51> DGPU_PWR_EN E40 REQ3# / GPIO54 EHCI 2 USBP10P A30
USB20_N11
USBP11N L32 USB20_N11 <22>
PCH_GPIO51 D47 K32 USB20_P11 Int. Camera
GNT1# / GPIO51 USBP11P USB20_P11 <22>
PCH_GPIO53 E42 G32
PCH_GPIO55 GNT2# / GPIO53 USBP12N
F46 GNT3# / GPIO55 USBP12P E32
USBP13N C32
USBP13P A32
PCH_GPIO2 G42
PCH_GPIO3 PIRQE# / GPIO2
G40 PIRQF# / GPIO3
PCH_GPIO4 C42 C33 USBBIAS 1 2
PCH_GPIO5 PIRQG# / GPIO4 USBRBIAS# RH165 22.6_0402_1%
D44 PIRQH# / GPIO5
3
Within 500 mils 3
USBRBIAS B33
T80 PAD PCI_PME# K10 PME#
PLT_RST# C6 A14 USB_OC#0 USB_OC#0 <37,40> USB-Right Front
<34,35,40,41,5> PLT_RST# PLTRST# OC0# / GPIO59
K20 USB_OC#1 USB_OC#1 <37,40> USB-Right Rear
OC1# / GPIO40 USB_OC#2 +3VALW_PCH
OC2# / GPIO41 B17 USB_OC#2 <37,40> USB-Left
<40> CLK_PCI_EC
22_0402_5% 1 2 RH167 CLK_EC_R H49 CLKOUT_PCI0 OC3# / GPIO42 C16 SLP_CHG_M3
SLP_CHG_M3 <37>
22_0402_5% 1 2 RH166 CLK_PCH H43 L16 SLP_CHG_M4 USB_OC#7 1 2
<25> CLK_PCILOOP CLKOUT_PCI1 OC4# / GPIO43 SLP_CHG_M4 <37>
<41> CLK_PCI_DDR
22_0402_5% 1 2 RH292 CLK_SIO J48 CLKOUT_PCI2 OC5# / GPIO9 A16 USB_OC#5 RH215 10K_0402_5%
@ K42 D14 USB_OC#6
CLKOUT_PCI3 OC6# / GPIO10
1
H40 C14 USB_OC#7 USB_OC#0 1 2

CH22 CLKOUT_PCI4 OC7# / GPIO14 RH209 10K_0402_5%
47P_0402_50V8J
2
@ PANTHER-POINT_FCBGA989 HM77R1@ SLP_CHG_M3 1 2

RH210 10K_0402_5%
SLP_CHG_M4 1 2
RH211 10K_0402_5%
Boot BIOS Strap USB_OC#6 1 2

RH212 10K_0402_5%
@ RF_OFF# PCH_GPIO19 Boot BIOS Loaction
2 1 PLT_RST# PCH_GPIO51 USB_OC#1 1 2
100P_0402_50V8J CH104 LPC RH177 10K_0402_5%
0 0
1K_0402_5% 2 @ 1 RH293 PCH_GPIO51 Reserved USB_OC#2
0 1 1
RH183
2
10K_0402_5%
1K_0402_5% 2 @ PCH_GPIO19 1 0 PCI USB_OC#5

1 RH294 PCH_GPIO19 <24> 1 2
SPI RH186 10K_0402_5%
1 1 *
1K_0402_5% 2 @ 1 RH295 PCH_GPIO55
4 4
A16 Swap Override Strap

Low= A16 swap override Enable
WL_OFF# * High= A16 swap override Disable
PCH_PCI/USB/NAND
Custom 1.0
VCUAA
A B C D E
A B C D E
+3VALW_PCH
+3VS
2 1 EC_LID_OUT#
RH204 1K_0402_5% UH1F
1 2 EC_SMI# <23,27> HDMI_HPD HDMI_HPD T7 C40 PCH_GPIO68

RH205 10K_0402_5% BMBUSY# / GPIO0 TACH4 / GPIO68 PCH_GPIO68 1 2
PCH_GPIO1 A42 B41 RH297 10K_0402_5%
PCH_GPIO12 TACH1 / GPIO1 TACH5 / GPIO69 GATEA20
1 2 1 2
RH298 10K_0402_5% PCH_GPIO6 H36 C41 RH182 10K_0402_5%
TACH2 / GPIO6 TACH6 / GPIO70 KB_RST# 1 2
1 2 PCH_GPIO28 <40> EC_SCI# EC_SCI# E38 A40 PCH_GPIO71 RH184 10K_0402_5%
RH202 10K_0402_5% TACH3 / GPIO7 TACH7 / GPIO71 PCH_GPIO71 1 2
<40> EC_SMI# EC_SMI# C10 RH203 10K_0402_5%
1 PCH_GPIO57 GPIO8 1
1 2
RH207 10K_0402_5% PCH_GPIO12 C4 LAN_PHY_PWR_CTRL / GPIO12
+3VS EC_LID_OUT# G2 P4 GATEA20
<40> EC_LID_OUT# GPIO15 A20GATE GATEA20 <40>
1 2 BT_ON# AU16
RH180 10K_0402_5% PCH_GPIO16 PECI
U2 SATA4GP / GPIO16
P5 KB_RST#
1 2 PCH_GPIO1
For OPT RCIN# KB_RST# <40>
GPIO
RH190 10K_0402_5% VGA_PWROK D40 AY11 H_PWRGOOD
<42,51> VGA_PWROK TACH0 / GPIO17 PROCPWRGD H_PWRGOOD <5>
CPU/MISC
1 2 PCH_GPIO22 PCH_GPIO22 T5 AY10 PCH_THRMTRIP# 1 2
SCLOCK / GPIO22 THRMTRIP# H_THERMTRIP# <5>
RH185 10K_0402_5% RH191 390_0402_5%
E8 GPIO24 INIT3_3V# T14
1 2 PCH_GPIO36 This signal has weak internal
RH178 200K_0402_5% PCH_GPIO27 E16 AY1 NV_CLE
GPIO27 DF_TVS pull-up, can't be pulled low
1 2 PCH_GPIO6 PCH_GPIO28 P8
RH197 10K_0402_5% GPIO28
TS_VSS1 AH8
BT_ON# K1
<34> BT_ON# STP_PCI# / GPIO34
1 2 PCH_GPIO16 AK11
RH179 10K_0402_5% PCH_GPIO35 TS_VSS2
T81 PAD K4 GPIO35
TS_VSS3 AH10
1 2 EC_SCI# PCH_GPIO36 V8
RH303 10K_0402_5% SATA2GP / GPIO36
TS_VSS4 AK10
PCH_GPIO37 M5
PCH_GPIO39 SATA3GP / GPIO37
1 2
RH194 10K_0402_5% OPTIMUS_EN# N2 P37
SLOAD / GPIO38 NC_1
1 @ 2 PCH_GPIO48 PCH_GPIO39 M3
RH304 10K_0402_5% SDATAOUT0 / GPIO39
PCH_GPIO48 V13 BG2
2 PCH_GPIO49 SDATAOUT1 / GPIO48 VSS_NCTF_15 2
1 2
RH195 10K_0402_5% PCH_GPIO49 V3 BG48
SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
DMI & FDI Termination Voltage
2 @ 1 HDMI_HPD PCH_GPIO57 D6 BH3
RH216 10K_0402_5% GPIO57 VSS_NCTF_17
VSS_NCTF_18 BH47 Set to VCC when HIGH

1 UMA@ 2 OPTIMUS_EN# NV_CLE
RH196 10K_0402_5% A4 BJ4 Set to VSS when LOW
VSS_NCTF_1 VSS_NCTF_19
1 2 PCH_GPIO37 A44 BJ44
RH198 10K_0402_5% VSS_NCTF_2 VSS_NCTF_20
Follow Compal ORB A45 VSS_NCTF_3 VSS_NCTF_21 BJ45
2 @ 1 PCH_GPIO27
and Intel Check list 460603 V1.5
NCTF
RH199 10K_0402_5% A46 BJ46
2 1 PCH_GPIO48 A5 BJ5 +1.8VS
RH307 47K_0402_5% VSS_NCTF_5 VSS_NCTF_23
A6 VSS_NCTF_6 VSS_NCTF_24 BJ6
1
2 OPT@ 1 OPTIMUS_EN#
RH201 10K_0402_5% B3 C2 RH187
2.2K_0402_5%
B47 VSS_NCTF_8 VSS_NCTF_26 C48
2
BD1 VSS_NCTF_9 VSS_NCTF_27 D1
NV_CLE 2 1 H_SNB_IVB# <5>
GPIO28 BD49 D49 RH189 1K_0402_5%
On-Die PLL Voltage Regulator BE1 VSS_NCTF_11 VSS_NCTF_29 E1
* H: Enable BE49 VSS_NCTF_12 VSS_NCTF_30 E49
L: Disable
BF1 VSS_NCTF_13 VSS_NCTF_31 F1
3 3
RH206 1 @ 2 1K_0402_5% PCH_GPIO28 BF49 VSS_NCTF_14 VSS_NCTF_32 F49
GPIO8 OPTIMUS_EN# PCH_GPIO57 PCH_GPIO71

Integrated Clock Chip Enable (Removed)
H: Disable OPTIMUS_EN# H L HDD2_DET# H L 3D_DET# H L
* L: Enable
SKU NonOPT Optimus SKU ONE HDD TWO HDD SKU Non3D 3D
RH3081 @ 2 1K_0402_5% EC_SMI#
Integrated clock enable functionality

is achieved by soft-strap
The current default is clock enable
4 4

PCH_CPU/GPIO
Custom 1.0
VCUAA
A B C D E
A B C D E
+1.05VS_VCCP UH1G POWER +3VS
PJ4 @ RH309 LH1

PCH Power Rail Table
1700mA
2 2 1 1 1U_0402_6.3V6K +1.05VS_PCH AA23 VCCCORE[1] 1mA VCCADAC U48 +VCCA_DAC 0.1U_0402_10V7K 1 2+VCCA_DAC_R2 1 Refer to PCH EDS R1.0
AC23 1 1 1 1_0603_1% BLM18PG181SN1D_0603
JUMP_43X118 VCCCORE[2] CH35 CH36 CH37
1 1 1 1 AD21 S0 Iccmax
CRT
CH32 CH33 CH31 CH34 VCCCORE[3] 0.01U_0402_25V7K 10U_0603_6.3V6M
AD23 VCCCORE[4] VSSADAC U47 Voltage Rail Voltage Current (A)
1 1
AF21
VCC CORE
10U_0603_6.3V6M VCCCORE[5] 2 2 2
AF23 VCCCORE[6]
2 2 2 2 +3VS V_PROC_IO 1.05 0.001
AG21 VCCCORE[7]
AG23 VCCCORE[8]
1U_0402_6.3V6K 1U_0402_6.3V6K AG24 1mA AK36 +VCCA_LVDS 1 @ 2
VCCCORE[9] VCCALVDS RH208 0_0603_5%
AG26 VCCCORE[10]
V5REF 5 0.001
AG27 VCCCORE[11] VSSALVDS AK37
AG29 VCCCORE[12]
AJ23 VCCCORE[13]
V5REF_Sus 5 0.001
+1.8VS
LVDS
AJ26 VCCCORE[14] VCCTX_LVDS[1] AM37
AJ27 0.01U_0402_25V7K LH2
VCCCORE[15] +VCCTX_LVDS
AJ29 VCCCORE[16] VCCTX_LVDS[2] AM38 2 1 Vcc3_3 3.3 0.228
AJ31 1 1 BLM18PG181SN1D_0603
+1.05VS_PCH VCCCORE[17] CH39 CH40
60mA VCCTX_LVDS[3] AP36
CH38 22U_0805_6.3V6M VccADAC 3.3 0.063
VCCTX_LVDS[4] AP37 0.01U_0402_25V7K
2 2
AN19 VCCIO[28]
VccADPLLA 1.05 0.08
This pin can be left as NC if +3VS
PAD T82 BJ22 VCCAPLLEXP
On-Die VR is enabled (Default) VccADPLLB 1.05 0.08
VCC3_3[6] V33
HVCMOS
AN16 VCCIO[15]
1 VccCore 1.05 1.7
AN17 CH42
VCCIO[16] 0.1U_0402_10V7K
VCC3_3[7] V34
VccDMI 1.1 0.047
2
AN21 VCCIO[17] +VCCAFDI_VRM +1.5VS
AN26 VCCIO[18]
VccIO 1.05 3.711
+VCCAFDI_VRM @
2
AN27 VCCIO[19] 3709mA VCCVRM[3] AT16 1
RH221
2
0_0603_5% 2
VccASW 1.05 0.903
+1.05VS_PCH AP21 +VCCP_VCCDMI +1.05VS_VCCP
VCCIO[20]
1U_0402_6.3V6K AP23 AT20 +VCCP_VCCDMI 1 @ 2 VccSPI 3.3 0.01
VCCIO[21] VCCDMI[1]
1 RH213 0_0603_5%
+1.05VS_PCH
DMI
1 1 1 1 1 AP24 VCCIO[22]
VCCIO
CH43 CH45 CH46 CH47 CH44 CH48 VccDSW 3.3 0.001
AP26 AB36 +1.05VS_VCC_DMI 1 @ 2 1U_0402_6.3V6K
10U_0603_6.3V6M 1U_0402_6.3V6K VCCIO[23] 75mA VCCCLKDMI RH214 0_0603_5% 2
2 2 2 2 2 1
AT24 VCCIO[24]
VccDFTERM 1.8 0.002
CH49
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
2 VccRTC 3.3 N/A
AN33 VCCIO[25]
VCCDFTERM
AN34 AG16 +1.8VS
+3VS VCCIO[26] VCCDFTERM[1]
VccSus3_3 3.3 0.095
BH29 VCC3_3[3] VCCDFTERM[2] AG17
1
CH50 DFT / SPI 190mA
1 VccSusHDA 3.3 0.01
0.1U_0402_10V7K AJ16 CH51
VCCDFTERM[3] 0.1U_0402_10V7K VccVRM 1.5 0.167
2 +VCCAFDI_VRM 2
AP16 VCCVRM[2]
VCCDFTERM[4] AJ17
VccCLKDMI 1.05 0.07
This pin can be left as NC if PAD T83 BG6 VccAFDIPLL +3VS
On-Die VR is enabled (Default) VccSSC 1.05 0.095
+1.05VS_PCH AP17 VCCIO[27]
V1
FDI
20mA VCCSPI
VccDIFFCLKN 1.05 0.055
+VCCP_VCCDMI AU20 VCCDMI[2] 1
3 3
CH53 VccALVDS 3.3 0.001
PANTHER-POINT_FCBGA989 HM77R1@ 1U_0402_6.3V6K
2
VccTX_LVDS 1.8 0.04
+3VALW to +3V_PCH
+3VALW +3VALW_PCH
@
2 2 1
1 JUMP_43X79
PJ2
QH2
AO3413_SOT23
20K_0402_5%
S
3 1
CH111
CH112
CH113
G
1 1
2
1
0.01U_0402_25V7K
CH1140.1U_0402_25V6
0.1U_0402_10V7K
@
2 2
RH4
2
4 4
PCH_PWR_EN# 2 1
<31,42> PCH_PWR_EN#
RH3 47K_0402_5%
1
@
0.1U_0402_25V6
2
PCH_POWER-1
Custom 1.0
VCUAA
A B C D E
A B C D E
+5VALW +5VALW_PCH
+3VS
@
LH5 2 1
+3VS_VCC_CLKF33 PJ5 2 1 JUMP_43X39
1 2
10UH_LB2012T100MR_20% 1 1
CH73 CH74
This pin can be left as NC if
+3VALW_PCH On-Die VR is enabled (Default)
20K_0402_5%
10U_0603_6.3V6M 1U_0402_6.3V6K QH6
2 2 UH1J POWER +1.05VS_PCH AO3413_SOT23
CH115
D
PAD 3 1
0.1U_0402_10V7K CH59
1 T84 AD49 VCCACLK VCCIO[29] N26 1 1
CH55 1
1
1 0.1U_0402_10V7K 1
G
P26
2
VCCIO[30]
0.1U_0402_25V6
T16 CH56
@ 2 VCCDSW3_3 3mA 1U_0402_6.3V6K 2 2 @
"@" Avoid leakage CH58 VCCIO[31] P28
2
RH228
2 1 +PCH_VCCDSW V12 T27
2
DCPSUSBYP VCCIO[32]
0.1U_0402_10V7K T29 2 1
VCCIO[33] +3VALW_PCH <30,42> PCH_PWR_EN#
+3VS_VCC_CLKF33 T38 RH5 47K_0402_5%
VCC3_3[5]
This pin can be left as NC if VCCSUS3_3[7] T23 Change RH232, RH237 to 10 ohm by follow Compal ORB abd Intel CRB
PAD T85 BH23 VCCAPLLDMI2 1
On-Die VR is enabled (Default) 119mA VCCSUS3_3[8] T24 CH60 +3VALW_PCH
+1.05VS_PCH AL29 0.1U_0402_10V7K
VCCIO[14] +5VALW_PCH +3VALW_PCH
VCCSUS3_3[9] V23
2
USB
1
+VCCSUS AL24 V24
DCPSUS[3] VCCSUS3_3[10]
2
1 CH61
CH54 P24 0.1U_0402_10V7K RH232 DH3
1U_0402_6.3V6K VCCSUS3_3[6] 2
10_0402_5%
@ AA19 CH751H-40PT_SOD323-2
+1.05VS_PCH 2 VCCASW[1]
T26 +1.05VS_PCH
1
VCCIO[34] +PCH_V5REF_SUS
AA21 VCCASW[2] 1010mA
1
AA24 1mA M26 +PCH_V5REF_SUS CH63
VCCASW[3] V5REF_SUS
1 1 AA26 @ 0.1U_0402_10V7K
Clock and Miscellaneous

CH64 CH65 VCCASW[4] +VCCA_USBSUS CH62 1 2
DCPSUS[4] AN23 2 1U_0402_6.3V6K
AA27 VCCASW[5]
22U_0805_6.3V6M AN24 +3VALW_PCH
2 2 VCCSUS3_3[1]
AA29 VCCASW[6]
22U_0805_6.3V6M 1 2
AA31 CH66 0.1U_0402_10V7K
2 VCCASW[7] +5VS +3VS 2
CH63 & CH71 are
1U_0402_6.3V6K AC26 P34 +PCH_V5REF_RUN
VCCASW[8] 1mA V5REF +3VALW_PCH different by Intel CRB.
1 1 1
2
CH67 CH68 CH69 AC27 VCCASW[9] RH237 DH4
VCCSUS3_3[2] N20
+1.05VS_PCH
PCI/GPIO/LPC
1U_0402_6.3V6K 1U_0402_6.3V6K AC29 1 10_0402_5%
2 2 2 VCCASW[10] CH70 CH751H-40PT_SOD323-2
VCCSUS3_3[3] N22
LH7 AC31 1U_0402_6.3V6K
1
+1.05VS_VCCADPLLA VCCASW[11] +PCH_V5REF_RUN
1 2 VCCSUS3_3[4] P20
BLM18PG181SN1D_0603 2
AD29 VCCASW[12]
LH8 P22 1
+1.05VS_VCCADPLLB VCCSUS3_3[5] +3VS CH71
1 2 AD31 VCCASW[13]
BLM18PG181SN1D_0603
W21 AA16 1U_0402_6.3V6K
VCCASW[14] VCC3_3[1] 2
1 1 1 1 +3VS 1
CH93 CH94 CH95 CH96 W23 W16 CH72
1U_0402_6.3V6K VCCASW[15] VCC3_3[8] 0.1U_0402_10V7K
1U_0402_6.3V6K W24 T34
2 2 2 2 VCCASW[16] VCC3_3[4] 2
10U_0603_6.3V6M 10U_0603_6.3V6M W26 1 2
VCCASW[17] CH75
0.1U_0402_10V7K +3VS
W29 VCCASW[18]
W31 VCCASW[19] VCC3_3[2] AJ2
+1.05VS_PCH +1.05VS_SATA3 +1.05VS_PCH
1
W33 VCCASW[20]
1 @ 2 +VCCDIFFCLK AF13 CH76 1 @ 2
RH244 0_0603_5% VCCIO[5] 0.1U_0402_10V7K RH242 0_0805_5%
+VCCRTCEXT 2
1 N16 DCPRTC 1
CH79 1 AH13 CH77
1U_0402_6.3V6K CH78 VCCIO[12] 1U_0402_6.3V6K
0.1U_0402_10V7K +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3
3 2 VCCVRM[4] VCCIO[13] 2 3
2
+1.05VS_PCH +1.05VS_VCCDIFFCLKN +1.05VS_VCCADPLLA VCCIO[6] AF14 This pin can be left as NC if

BD47 VCCADPLLA 80mA On-Die VR is enabled (Default)
SATA
VCCAPLLSATA AK1 T86 PAD
1 @ 2 +1.05VS_VCCDIFFCLKN +1.05VS_VCCADPLLB BF47 +VCCAFDI_VRM
RH247 0_0603_5% VCCADPLLB 80mA
1
CH81 AF11 +VCCAFDI_VRM
1U_0402_6.3V6K +VCCDIFFCLK VCCVRM[1] +1.05VS_VCC_SATA +1.05VS_PCH
AF17 VCCIO[7] 55mA
AF33 VCCDIFFCLKN[1]
2 +1.05VS_VCC_SATA @
AF34 VCCDIFFCLKN[2] VCCIO[2] AC16 1 2
+1.05VS_VCCDIFFCLKN AG34 RH246 0_0805_5%
+1.05VS_PCH VCCDIFFCLKN[3]
VCCIO[3] AC17 1
CH82
AG33 AD17 1U_0402_6.3V6K
VCCSSC 95mA VCCIO[4]
1 2
CH84
1U_0402_6.3V6K +VCCSST V16 +1.05VS_PCH
DCPSST
2 1
0.1U_0402_10V7K
+1.05VM_VCCSUS T17 T21 +VCCME_22 1 @ 2
CH85 DCPSUS[1] VCCASW[22] RH311 0_0402_5%
V19 DCPSUS[2]
2
MISC
+1.05VS_VCCP V21 +VCCME_23 1 @ 2

VCCASW[23] RH312 0_0402_5%
+1.05VS_PCH
1mA
CPU
1 @ 2 0.1U_0402_10V7K +V_CPU_IO BJ8

RH313 @ RH249 0_0603_5% V_PROC_IO +VCCME_21 @
VCCASW[21] T19 1 2
2 1 +1.05VM_VCCSUS 1 1 1 RH314 0_0402_5%
CH86 CH87 CH88 +RTCVCC
0_0603_5% +3VALW_PCH
1
CH83 4.7U_0402_6.3V6M 0.1U_0402_10V7K 0.1U_0402_10V7K A22 10mA P32
RTC
2 2 2 VCCRTC VCCSUSHDA
HDA
1U_0402_6.3V6K
4 @ 4
2 1 1 1 1
CH89 CH90 CH91 PANTHER-POINT_FCBGA989 HM77R1@ CH92
0.1U_0402_10V7K
1U_0402_6.3V6K 0.1U_0402_10V7K
2 2 2 2
unmount CH83 by follow Compal ORB abd Intel CRB

PCH_POWER-2
Custom 1.0
VCUAA
A B C D E
A B C D E
UH1I
AY4 VSS[159] VSS[259] H46

AY42 VSS[160] VSS[260] K18
AY46 VSS[161] VSS[261] K26
AY8 VSS[162] VSS[262] K39
B11 VSS[163] VSS[263] K46
UH1H B15 K7
VSS[164] VSS[264]
H5 VSS[0] B19 VSS[165] VSS[265] L18
B23 VSS[166] VSS[266] L2
AA17 VSS[1] VSS[80] AK38 B27 VSS[167] VSS[267] L20
1 1
AB11 VSS[6] VSS[85] AL16 F45 VSS[172] VSS[272] M12
AB14 VSS[7] VSS[86] AL17 BB12 VSS[173] VSS[273] P16
AB39 VSS[8] VSS[87] AL19 BB16 VSS[174] VSS[274] M18
AC19 VSS[13] VSS[92] AL27 BB30 VSS[179] VSS[279] M34
AC33 VSS[17] VSS[96] AL48 BC14 VSS[183] VSS[283] M46
AC34 VSS[18] VSS[97] AM11 BC18 VSS[184] VSS[284] M8
AC48 VSS[19] VSS[98] AM14 BC2 VSS[185] VSS[285] N18
AD10 VSS[20] VSS[99] AM36 BC22 VSS[186] VSS[286] P30
AD11 VSS[21] VSS[100] AM39 BC26 VSS[187] VSS[287] N47
AD19 VSS[24] VSS[103] AM46 BC36 VSS[190] VSS[290] T33
AD26 VSS[26] VSS[105] AN2 BC42 VSS[192] VSS[292] P43
AD27 VSS[27] VSS[106] AN29 BC48 VSS[193] VSS[293] P47
AD33 VSS[28] VSS[107] AN3 BD46 VSS[194] VSS[294] P7
AD34 VSS[29] VSS[108] AN31 BD5 VSS[195] VSS[295] R2
AD36 VSS[30] VSS[109] AP12 BE22 VSS[196] VSS[296] R48
AD37 VSS[31] VSS[110] AP19 BE26 VSS[197] VSS[297] T12
AD38 VSS[32] VSS[111] AP28 BE40 VSS[198] VSS[298] T31
AD39 VSS[33] VSS[112] AP30 BF10 VSS[199] VSS[299] T37
AD40 VSS[35] VSS[114] AP38 BF16 VSS[201] VSS[301] W34
2 2
AD46 VSS[39] VSS[118] AP8 BF26 VSS[205] VSS[305] V11
AD8 VSS[40] VSS[119] AR2 BF28 VSS[206] VSS[306] V17
AE2 VSS[41] VSS[120] AR48 BD3 VSS[207] VSS[307] V26
AE3 VSS[42] VSS[121] AT11 BF30 VSS[208] VSS[308] V27
AF10 VSS[43] VSS[122] AT13 BF38 VSS[209] VSS[309] V29
AF12 VSS[44] VSS[123] AT18 BF40 VSS[210] VSS[310] V31
AD14 VSS[45] VSS[124] AT22 BF8 VSS[211] VSS[311] V36
AD16 VSS[46] VSS[125] AT26 BG17 VSS[212] VSS[312] V39
AF16 VSS[47] VSS[126] AT28 BG21 VSS[213] VSS[313] V43
AF19 VSS[48] VSS[127] AT30 BG33 VSS[214] VSS[314] V7
AF24 VSS[49] VSS[128] AT32 BG44 VSS[215] VSS[315] W17
AF26 VSS[50] VSS[129] AT34 BG8 VSS[216] VSS[316] W19
AF27 VSS[51] VSS[130] AT39 BH11 VSS[217] VSS[317] W2
AF38 VSS[54] VSS[133] AT7 BH19 VSS[220] VSS[320] Y12
AF4 VSS[55] VSS[134] AU24 H10 VSS[221] VSS[321] Y38
AF42 VSS[56] VSS[135] AU30 BH27 VSS[222] VSS[322] Y4
AF46 VSS[57] VSS[136] AV16 BH31 VSS[223] VSS[323] Y42
AF8 VSS[60] VSS[139] AV30 BH39 VSS[226] VSS[328] BG29
AG19 VSS[61] VSS[140] AV38 BH43 VSS[227] VSS[329] N24
AG2 VSS[62] VSS[141] AV4 BH7 VSS[228] VSS[330] AJ3
AG31 VSS[63] VSS[142] AV43 D3 VSS[229] VSS[331] AD47
AG48 VSS[64] VSS[143] AV8 D12 VSS[230] VSS[333] B43
AH11 VSS[65] VSS[144] AW14 D16 VSS[231] VSS[334] BE10
AH3 VSS[66] VSS[145] AW18 D18 VSS[232] VSS[335] BG41
AH36 VSS[67] VSS[146] AW2 D22 VSS[233] VSS[337] G14
AH39 VSS[68] VSS[147] AW22 D24 VSS[234] VSS[338] H16
3 3
AH40 VSS[69] VSS[148] AW26 D26 VSS[235] VSS[340] T36
AH7 VSS[72] VSS[151] AW34 D34 VSS[238] VSS[344] C22
AJ19 VSS[73] VSS[152] AW36 D38 VSS[239] VSS[345] AP13
AJ21 VSS[74] VSS[153] AW40 D42 VSS[240] VSS[346] M14
AJ24 VSS[75] VSS[154] AW48 D8 VSS[241] VSS[347] AP3
AJ33 VSS[76] VSS[155] AV11 E18 VSS[242] VSS[348] AP1
AJ34 VSS[77] VSS[156] AY12 E26 VSS[243] VSS[349] BE16
AK12 VSS[78] VSS[157] AY22 G18 VSS[244] VSS[350] BC16
AK3 VSS[79] VSS[158] AY28 G20 VSS[245] VSS[351] BG28
G26 VSS[246] VSS[352] BJ28
PANTHER-POINT_FCBGA989 HM77R1@ G28 VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
H24 VSS[253]
H26 VSS[254]
H30 VSS[255]
H32 VSS[256]
H34 VSS[257]
F3 VSS[258]
4 4

PCH_GND
Custom 1.0
VCUAA
A B C D E
A B C D E
SATA HDD Conn.

Close to JHDD
JHDD @
GND 1
2 SATA_PTX_C_DRX_P0 C369 1 2 0.01U_0402_25V7K
RX+ SATA_PTX_DRX_P0 <24>
3 SATA_PTX_C_DRX_N0 C367 1 2 0.01U_0402_25V7K
RX- SATA_PTX_DRX_N0 <24>
GND 4
5 SATA_PRX_DTX_N0 C368 1 2 0.01U_0402_25V7K
TX- SATA_PRX_C_DTX_N0 <24>
6 SATA_PRX_DTX_P0 C370 1 2 0.01U_0402_25V7K
TX+ SATA_PRX_C_DTX_P0 <24>
GND 7
1
8 +5VS 1
3.3V
26 boss 3.3V 9
25 boss 3.3V 10 1 1
11 C371 C360
GND 0.1U_0402_10V7K 0.1U_0402_10V7K
24 GND GND 12
23 13 @ @
GND GND 2 2
5V 14
5V 15
5V 16 +5VS
GND 17 reserve for HDD noise,
18
Rsv
19
place close to HDD connector
GND +5VS
12V 20 Place closely JHDD SATA CONN.
12V 21 1.2A
12V 22
1 1 1
1
C357 C358 C359

C356 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K
10U_0805_6.3V6M
2
2 2 2
2 2
3 3
4 4

HDD
1.0
VCUAA
A B C D E
A B C D E
40 mils
Slot 1 Half PCIe Mini Card-WLAN +3V_WLAN
For SED WLAN&BT Combo module circuits Slot 2 Full PCIe Mini Card- mSATA +3VS For RF +3VS
120 mils For SED
0.1U_0402_10V7K JMSATA @ 47P_0402_50V8J 0.1U_0402_10V7K
1 1 1 BT BT 1 1 2 2 1 1 1
1
+3VS +3V_WLAN 3 4 CM18 CM19 CM4 CM5 CM6 CM20
on module on module 3 4
2 1 CM1 CM2 CM3 C253 5 6 @ 47P_0402_50V8J
2 1 47P_0402_50V8J 5 6 @
Enable Disable 7 8
2
PJ6 @ JUMP_43X79 2 2 2 @ 7 8 2 2 2
9 9 10 10
0.01U_0402_25V7K 4.7U_0805_10V4Z 11 12 680P_0402_50V7K 0.01U_0402_25V7K 4.7U_0805_10V4Z
11 12
Short for WIFI BT_CTRL H L 13 13 14 14
15 15 16 16
+1.5VS
For SED
BT_ON# L H
0.1U_0402_10V7K 17 18
+3VALW +3V_WLAN 17 18
1 1 1 19 19 20 20
1
1 1
2 2 1 1 21 21 22 22
CM7 CM8 CM9 C254 BT_CTRL SATA_PRX_DTX_P1 23 24 EMI request 8/7
PJ9 @ JUMP_43X79 47P_0402_50V8J SATA_PRX_DTX_N1 23 24
25 26
2
25 26
3
2 2 2 @ 27 27 28 28
reserve for BT issue 0.01U_0402_25V7K 4.7U_0805_10V4Z QM1A QM1B 29 30
0_0402_5% SATA_PTX_C_DRX_N1 29 30
31 31 32 32
1 2 2 5 SATA_PTX_C_DRX_P1 33 34
<29> BT_ON# 33 34
R1444 35 36
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 35 36
37 38
4
0_0402_5% 37 38
+3VS 39 39 40 40
<40> EC_BT_ON# 1 2 41 41 42 42
R1445 @ 43 44
+1.5VS 43 44
<42,5,9> SUSP 45 45 46 46
47 47 48 48
+3V_WLAN 49 50
JWLAN @ 49 50
51 51 52 52
1 2 +3V_WLAN
1 2
G1
G2
G3
G4
3 3 4 4
BT_CTRL 10_0402_5%2BT_CTRL_R 5 6
5 6
2
@ R1443 7 8 BT_CTRL 1 R327 2 E51_RXD_R BELLW_80060-1021 CM21 0.01U_0402_25V7K
<25> CLKREQ_WLAN#
53
54
55
56
7 8 RM17 1K_0402_5% SATA_PRX_DTX_N1 SATA_PRX_C_DTX_N1
9 9 10 10 1 2 SATA_PRX_C_DTX_N1 <24>
11 12 8.2K_0402_5% SATA_PRX_DTX_P1 1 2 SATA_PRX_C_DTX_P1
<25> CLK_WLAN# 11 12 SATA_PRX_C_DTX_P1 <24>
13 14 For isolate Intel Rainbow Peak and CM22 0.01U_0402_25V7K
<25> CLK_WLAN 13 14
15 16 Compal Debug Card. CM23 0.01U_0402_25V7K
1
15 16 SATA_PTX_C_DRX_N1 SATA_PTX_DRX_N1
1 2 SATA_PTX_DRX_N1 <24>
+3V_WLAN SATA_PTX_C_DRX_P1 1 2 SATA_PTX_DRX_P1
SATA_PTX_DRX_P1 <24>
17 18 CM24 0.01U_0402_25V7K
17 18 WLAN_OFF#
19 19 20 20 WL_OFF# <40>
1
21 22 PLT_RST#
21 22 PLT_RST# <28,35,40,41,5>
C266 23 24
<25> PCIE_PRX_WLANTX_N2 23 24
47P_0402_50V8J 25 26
<25> PCIE_PRX_WLANTX_P2
2
@ 25 26
27 27 28 28
WLAN/ WiFi 29 29 30 30 PM_SMBCLK <11,12,25,41>
2 <25> PCIE_PTX_C_WLANRX_N2 31 31 32 32 PM_SMBDATA <11,12,25,41> 2
+1.5VS 33 34
<25> PCIE_PTX_C_WLANRX_P2 33 34
35 35 36 36 USB20_N9 <28>
37 37 38 38 USB20_P9 <28> BT
1
+3V_WLAN 39 39 40 40
C260 41 42
47P_0402_50V8J 41 42
43 44
2
@ 43 44
45 45 46 46
R16 0_0402_5% 47 48
@ 47 48
<40> E51_TXD 1 2 49 49 50 50
1 @ 2 E51_RXD_R 51 52
<40> E51_RXD 51 52
R17 0_0402_5%
G1
G2
G3
G4
Debug card using

BELLW_80060-1021
53
54
55
56
+3VL +3V_LAN
0.1U_0402_10V7K
0.1U_0402_10V7K
1 1
CCL1 CCL2
GCLK@ GCLK@
2 2
3 3
1
+1.05VS_VCCP +3VS_VDDIO +3VALW CCL7 PCH_X1_R_R 1 GCLK@ 2 PCH_X1_R PCH_X1_R <25>
1 2.2U_0402_6.3V6M RCL1 0_0402_5%
C16 GCLK@
22U_0805_6.3V6M UCL1 G300@ 2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
PJ8
1 1 1 GCLK@ @
2 +RTCVCC_GCLK LAN_X1_R_R
+RTCBATT 10 VBAT VDD_RTC_OUT 14 2 1 +RTCVCC 1 GCLK@ 2 LAN_X1_R 1 LAN_X1_R <35>
CCL3 CCL6 CCL8 RCL2 33_0402_5%
GCLK@ GCLK@ GCLK@ G304@ +3VL 15 CCL10
2 2 2 +V3.3A PAD-OPEN 2x2m 5P_0402_50V8C
1 2
RCL4 0_0603_5% 2 GCLK@
+3VALW 2 VDD
9 PCH_RTCX1_R
32kHz PCH_RTCX1_R <24>
AO3413_SOT23
EMI request 11/06
S
+3VS_DGPU 3 1 +3VS_VDDIO 11 12 VGA_X1_R 1 OPT@ 2

VDDIO_27M 27MHz VGA_X1 <13>
G300@ RCL3 22_0402_5%
QCL1 +3V_LAN 8 6 LAN_X1_R_R
VDDIO_25M_A 25MHz_A LAN_X1_R_R 1 @
G
2
2
PCH_X1_R_R RCL5 0_0402_5%

+1.05VS_VCCP 3 VDDIO_25M_B 25MHz_B 5
22 ohm for NV chip
CLK_X1 1
CLK_X2 XTAL_IN
<42> VGA_PWROK# 16 XTAL_OUT
GND1
GND2
GND3
GND4
Reserved for Swing Level adjustment

( Close GCLK side )
SLG3NB300VTR_TQFN16_2X3 UCL1
4
7
13
17
SLG3NB244VTR_TQFN16_2X3
GCLK@ UMA@
YCL1 25MHZ 12PF X3G025000DK1H-X
UCL1
4 CLK_X1 1 3 CLK_X2 SLG3NB304VTR_TQFN16_2X3 4
1 3 G304@
GND GND
1 2 4 1
CCL4
18P_0402_50V8J CCL5
GCLK@
2 2
15P_0402_50V8J OPT UMA
GCLK@
300(default) Security Classification Compal Secret Data Compal Electronics, Inc.
SA00005RS00 244 Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title
GCLK PCIe-WLAN/mSATA/GCLK
304(low power) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SA000057I00 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
VCUAA
A B C D E
A B C D E
UL1 +3V_LAN CL3 to CL6 close to Pin 27,39,47,48

PAD TL1 CL7 to CL8 close to Pin 12,42
<25> PCIE_PRX_C_LANTX_P1 CL1 1 2 0.1U_0402_10V7K PCIE_PRX_LANTX_P1 22 31 PAD TL2
HSOP LED3/EEDO PAD TL3
LED1/EESK 37 1 2
<25> PCIE_PRX_C_LANTX_N1 CL2 1 2 0.1U_0402_10V7K PCIE_PRX_LANTX_N1 23 HSON LED0 40 CL3 0.1U_0402_10V7K
@ 1 2
LAN_EN PCIE_PTX_C_LANRX_P1 17 RL2 2
<25> LAN_EN 30 1 10K_0402_5% CL4 0.1U_0402_10V7K
2
<25> PCIE_PTX_C_LANRX_P1 HSIP EECS/SCL
PCIE_PTX_C_LANRX_N1 18 RL1 2 1 10K_0402_5%
G
<25> PCIE_PTX_C_LANRX_N1 HSIN EEDI/SDA 32 1 2
@ CL5 0.1U_0402_10V7K
1 2
CLKREQ_LAN# 1 3 LANCLK_REQ# 16 1 LAN_MDI0+ CL6 0.1U_0402_10V7K
<25> CLKREQ_LAN# CLKREQB MDIP0
2 LAN_MDI0-
S
PLT_RST# MDIN0 LAN_MDI1+
<28,34,40,41,5> PLT_RST# 25 PERSTB RTL8105E/8111E MDIP1 4
5 LAN_MDI1-
1 QL53 CLK_LAN MDIN1 1
<25> CLK_LAN 19 REFCLK_P MDIP2(NC) 7
2N7002KW_SOT323-3 CLK_LAN# 20 8
<25> CLK_LAN# REFCLK_N MDIN2(NC)
MDIP3(NC) 10
MDIN3(NC) 11
LAN_X1 43 CKXTAL1 +LAN_VDD10 +LAN_EVDD10
LAN_X2 44 13 +LAN_VDD10 CL19, CL20,CL21 close to pin 13,29,45, respectively
CKXTAL2 DVDD10 +LAN_VDD10
29 1 @ 2 CL22 close to pin 3, respectively
DVDD10 LL2 0_0603_5%
DVDD10 41 CL23,CL24,CL25 close to pin 6,9,41, respectively
EC_SWI# 28 1 1
<26> EC_SWI# LANWAKEB
1 2
+3VS RL24 2 1 10K_0402_5% LANCLK_REQ# ISOLATE# 26 27 CL18 CL17 CL19 0.1U_0402_10V7K
ISOLATEB DVDD33 +3V_LAN
39 1U_0402_6.3V6K 0.1U_0402_10V7K 1 2
DVDD33 2 2 CL20 0.1U_0402_10V7K
+3V_LAN RL25 2 @ 1 10K_0402_5% EC_SWI# 14 12 1 2
SMBCLK(NC) AVDD33 +3V_LAN
15 42 CL21 0.1U_0402_10V7K
SMBDATA(NC) AVDD33
38 GPO/SMBALERT AVDD33 47 Close to Pin 21
AVDD33 48
33 ENSWREG
+3VS
EVDD10 21 +LAN_EVDD10 Placement near to YL1
34 VDDREG
35 VDDREG AVDD10 3 +LAN_VDD10
6 RL8 GCLK@
AVDD10
1
9 1 2 LAN_X2
AVDD10 <34> LAN_X1_R
1 2 46 45 0_0402_5%
1K_0402_5% RL5 2.49K_0402_1% RSET AVDD10
RL6 24 36 CL43 10P_0402_50V8J
@ GND REGOUT
49 1 2 1 2
2
GND RL29 22_0402_5%

ISOLATE# 1 @ 2 WOL_EN# GCLK@ GCLK@
RL433 0_0402_5% RTL8105E-GR_QFN48_6X6
2 2
EMI request 11/06
RL7
15K_0402_5% RTL8105E RTL8111E/F
Sx Enable Sx Disable S0
Wake up Wake up Pin14 NC NC 8105E-VL/VD 8105E-VL/VD
8111F/F-VB
Pin15 NC 10K ohm PD PWM Mode LDO Mode
WOL_EN# LOW HIGH HIGH
Pin38 NC 1K ohm PH NOGCLK@ YL1 25MHZ_20PF_7V25000016 RL4 0 ohm NC
(Pull High)
LAN_X1 1 3 LAN_X2
1 3
Reserve +3VALW_PCH NC 0 ohm
+3VALW TO +3V_LAN to +3V_LAN for saving
GND GND RL23 (Pull Down)
1 2 4 1
Vgs=-4.5V,Id=3A,Rds<97mohm power consumption on CL26 CL27
27P_0402_50V8J 27P_0402_50V8J
+3VALW DVT +3VALW_PCH NOGCLK@ NOGCLK@
+3VALW 2 2
1
2
RL147 CL483
100K_0402_5% @
@ 0.1U_0402_10V7K
2
1
2
S
@ RL432 @ QL51
G PJ29 PJ7
<40> WOL_EN# 1 2 2
@ @
47K_0402_5% AO3413_SOT23 D +3V_LAN
2
1
@ PAD-OPEN 2x2mPAD-OPEN 2x2m

LAN Conn.
1
3 CL482 3
0.01U_0402_25V7K
1
2
1 JLAN
CL682 8
CL681 PR4-
1U_0402_6.3V6K GND 10
4.7U_0805_10V4Z 1
7 PR4+ GND 9
@ 2 UL3
RJ45_MIDI1- 6 PR2-
2
LAN_MDI0+ 1 16 RJ45_MIDI0+
LAN_MDI0- TD+ TX+ RJ45_MIDI0- CL39 1000P_0402_50V7K D93
2 15 5
2
TD- TX- PR3-
3 CT CT 14 2 1 1 2 AZC199-02SPR7G_SOT23-3
4 13 RL11 75_0402_1% 4
NC NC PR3+
1
5 12 CL40 1000P_0402_50V7K
+3V_LAN rising time (10%~90%) need > 1ms and <100ms. 6
NC NC
11 2 1 1 2 RJ45_MIDI1+ 3
1
LAN_MDI1+ CT CT RJ45_MIDI1+ RL12 75_0402_1% PR2+
7 RD+ RX+ 10 For ESD
1 LAN_MDI1- 8 9 RJ45_MIDI1- RJ45_MIDI0- 2
RD- RX- PR1-
LAN WOLLAN_EN ISOLATEB CL34 RJ45_MIDI0+ 1 PR1+
S0 Sx S0 Sx 2
0.1U_0402_25V6 10/100M transformer_NS681695
SP050006N00 SANTA_130456-031 @
----------------------------------------------
0 0 0 0 1 1 Place CL34 colse
to LAN chip
0 1 0 0 1 1
1 0 1 1 1 1
1 1 1 1 1 0* RJ45_GND 1 2 LANGND
CL36 1000P_1808_3KV7K 1 1
CL37 CL38
4.7U_0402_6.3V6M
4 * 2
220P_0402_50V6K
2
@ 4
S3: after SUSP# assert low over 100ms

S4/S5: after SYSON assert low over 100ms

PCIe-LAN-RTL8105E
VCUAA
A B C D E
5 4 3 2 1
Close to IC
D D
2 1 USB20_P3_R For EMI request
<28> USB20_P3
RW1 0_0402_5% 1 2
@ LR4 @CW2
@ CW2 100P_0402_50V8J
2 @RW6
@ RW6 10_0402_5% @CW10
@ CW10 10P_0402_50V8J
2 1 1 CLK_48M_CR 1 2 1 2
RW2
3 4 6.19K_0402_1%
3 4
2 1
WCM-2012-900T_0805 UW1
2 1 USB20_N3_R 1
<28> USB20_N3 REFE
RW3 0_0402_5% 17
USB20_N3_R GPIO0
2 DM
USB20_P3_R 3 24 CLK_48M_CR < 48MHz >
DP CLK_IN CLK_48M_CR <25>
+3VS 4 3V3_IN XD_D7 23

+VCC_3IN1 5 CARD_3V3
1 1 +V1_8 6 22
CW3 CW1 V18 SP14 SD_DATA2_MS_DATA5
1 SP13 21
4.7U_0402_6.3V6M
0.1U_0402_10V7K
@ CW7 7 20 MS_DATA1_SD_DATA3
1U_0402_6.3V6K XD_CD# SP12
SP11 19
2 2 SDWP_MSCLK SDCMD
8 SP1 SP10 18
2
9 SP2 SP9 16
SD_DATA1 10 15 MS_DATA2_SDCLK
SP3 SP8
EPAD
SD_DATA0 11 14
SP4 SP7 SDCD#
12 SP5 SP6 13
FAE recommand RTS5137-GR_QFN24_4X4
25
C C
< 2 in 1 Card Reader >
JCARD @
1 MS_DATA1_SD_DATA3
DAT3
2 SDCMD
CMD
VSS1 3
VDD 4 +VCC_3IN1
5 MS_DATA2_SDCLK
CLK
1 1
6 CW6 CW5
VSS2
7 SD_DATA0 0.1U_0402_16V4Z 1U_0402_6.3V6K
DAT0 2 2
8 SD_DATA1
DAT1
9 SD_DATA2_MS_DATA5
DAT2
12 10 SDCD#
G1 CD
13 11 SDWP_MSCLK
B G2 WP B
TAITW_PSDAT0-09GLBS1ZZ4H1
For EMI request
@RW4
@ RW4 10_0402_5% @CW8
@ CW8 6.8P_0402_50V8C
MS_DATA2_SDCLK 1 2 1 2
@RW5
@ RW5 10_0402_5% @CW9
@ CW9 6.8P_0402_50V8C
SDWP_MSCLK 1 2 1 2
A A

USB-CardReader RTS5137
VCUAA
5 4 3 2 1
5 4 3 2 1
Left USB 2.0 x 1 Right side USB 3.0 x 2/ Sleep&Charge

+5VALW W=60mils
<28> USB20_P2 USB20_P2 RR26 1 @ 2 USB20_P2_L 2.0A +USB_VCCC For EMI USB Sleep & Charge Auto-Mode/Mode3
0_0402_5% U13
LR3 2 6 2 1
IN OUT CR38 1000P_0402_50V7K
2 2 1 1 3 IN OUT 7 MAX14600 & MAX14617
USB_EN#2 4 8
<40> USB_EN#2 EN/ENB OUT
1 GND OCB 5 USB_OC#2 <28,40> CB0 CB1 CB2
3 3 4 4 1 SLP_CHG_M4 STATUS
SY6288DCAC_MSOP8 SLP_CHG_M3 (14617 only)
WCM-2012-900T_0805 SA00004KB00 CR39
<28> USB20_N2 USB20_N2 RR25 1 2 USB20_N2_L 4.7U_0805_10V4Z AUTO MODE
0_0402_5% @ SA00003TV00 2 0 0 0
D D
Force Dedicated charger mode
0 1 0 (MODE3)
Pass-Through (USB) Mode:
1 0 0 Connect DP/DM to TDP/TDM
JUSBL
+USB_VCCC 1 VBUS G1 5 Pass-Through (USB) Mode with CDP Emulation:
USB20_N2_L 2 6
USB20_P2_L D- G2 1 1 0 Auto Connect DP/DM to TDP/TDM depending on CDP status
3 D+ G3 7
4 GND G4 8
X X 1 Force Apple 2A Charger Mode: Apple 2A resistor dividers
ACON_UARC9-4K1986
+USB_VCCC W=80mils
4.7U_0805_10V4Z 0.1U_0402_10V7K
DR1
@ 1 1 1 1 1 1 1 1 1 1 1 1
USB20_P2_L 2 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR46 CR45 CR44
2 @ + CR40
1 1
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
USB20_N2_L 3 @
3 2 2 2 2 2 2 2 2 2 2 2
2
AZC199-02SPR7G_SOT23-3 1000P_0402_50V7K
220U_6.3V_M
Co-lay OSCON +USB_VCCB
W=80mils
+5VALW 2.0A +USB_VCCB W=80mils
For EMI
U15 0.1U_0402_10V7K 4.7U_0805_10V4Z
2 IN OUT 6 2 1 1
3 7 C363 1000P_0402_50V7K 1 1 1
USB_EN#0 IN OUT + C900 C901 C902 C366
<40> USB_EN#0 4 EN/ENB OUT 8
1 5 USB_OC#0 <28,40> @
GND OCB
1 2 2 2 2
SY6288DCAC_MSOP8
SA00004KB00 C364
C C
4.7U_0805_10V4Z 220U_6.3V_M 1000P_0402_50V7K
SA00003TV00 2 @
U3RXDP1_L
W=80mils +USB_VCCA
1 @ 2 R1448
<28> U3RXDP1 0_0402_5%
KINGCORE WCM-2012HS-670T
+5VALW 2.0A +USB_VCCA For EMI W=80mils
U14
1 2 2 6 2 1 0.1U_0402_10V7K 4.7U_0805_10V4Z
1 2 IN OUT C361 1000P_0402_50V7K
3 IN OUT 7 1
USB_CHG_EN# 4 8 1 1 1
<40> USB_CHG_EN# EN/ENB OUT + C897
4 3 1 5 USB_OC#1 <28,40> C898 C899 C365
4 3 GND OCB @
1
L56 SY6288DCAC_MSOP8
U3RXDN1_L 2 2 2 2
1 2 R1449 SA00004KB00 C362
<28> U3RXDN1 @ 0_0402_5% 4.7U_0805_10V4Z
SA00003TV00 2 @ 220U_6.3V_M 1000P_0402_50V7K
U3TXDP1 1 2U3TXDP1_C 1 @ 2 R1450 U3TXDP1_C_L
<28> U3TXDP1
C903 0.1U_0402_10V7K 0_0402_5%
1 1 2 2
USB20_P0 1 @ 2 RR31 USB20_P0_R JUSBRF @
<28> USB20_P0
0_0402_5% +USB_VCCB 1
LR7 USB20_N0_R VBUS
4 4 3 3 2 D-
2 2 1 USB20_P0_R 3
L60 1 D+
4 GND
U3TXDN1 1 2U3TXDN1_C 1 2 R1451 U3TXDN1_C_L U3RXDN1_L 5
<28> U3TXDN1 StdA-SSRX-
C904 0.1U_0402_10V7K @ 0_0402_5% 3 4 U3RXDP1_L 6 10
3 4 StdA-SSRX+ GND
7 GND-DRAIN GND 11
WCM-2012-900T_0805 U3TXDN1_C_L 8 12
USB20_N0 USB20_N0_R U3TXDP1_C_L StdA-SSTX- GND
<28> USB20_N0 1 2 RR30 9 StdA-SSTX+ GND 13
@ 0_0402_5%
1 @ 2 R1452 U3RXDP2_L LOTES_AUSB0015-P001A
<28> U3RXDP2 0_0402_5%
1 1 2 2
B B
4 4 3 3
L58
1 2 R1453 U3RXDN2_L USB20_P1_S 1 @ 2 RR48 USB20_P1_R JUSBRR @
<28> U3RXDN2 @ 0_0402_5% 0_0402_5% 1
+USB_VCCA VBUS
LR8 USB20_N1_R 2
U3TXDP2 D-
<28> U3TXDP2 1 2U3TXDP2_C 1 @ 2 R1454 U3TXDP2_C_L 2 2 1 1 USB20_P1_R 3 D+
C905 0.1U_0402_10V7K 0_0402_5% 4
KINGCORE WCM-2012HS-670T U3RXDN2_L GND
5 StdA-SSRX-
1 2 3 4 U3RXDP2_L 6 10
1 2 3 4 StdA-SSRX+ GND
7 GND-DRAIN GND 11
WCM-2012-900T_0805 U3TXDN2_C_L 8 12
USB20_N1_S USB20_N1_R U3TXDP2_C_L StdA-SSTX- GND
4 4 3 3 1 2 RR47 9 StdA-SSTX+ GND 13
@ 0_0402_5%
L59 LOTES_AUSB0015-P001A
U3TXDN2 1 2U3TXDN2_C 1 2 R1455 U3TXDN2_C_L
<28> U3TXDN2
C906 0.1U_0402_10V7K @ 0_0402_5%
@ D85
USB20_P0_R 2 2
1 1
USB20_N0_R 3 D87 @ D88 @
3 U3TXDP1_C_L 1 1 109 U3TXDP1_C_L U3TXDP2_C_L 1 1 109 U3TXDP2_C_L
14617@ U5 AZC199-02SPR7G_SOT23-3
1 2 SLP_CHG_CB2 1 8 SLP_CHG_M4 SLP_CHG_M4 <28> U3TXDN1_C_L 2 2 98 U3TXDN1_C_L U3TXDN2_C_L 2 2 98 U3TXDN2_C_L
R1470 USB20_N1_S CEN CB0 USB20_N1
2 DM TDM 7 USB20_N1 <28>
0_0402_5% USB20_P1_S 3 6 USB20_P1 U3RXDP1_L 4 4 77 U3RXDP1_L U3RXDP2_L 4 4 77 U3RXDP2_L
DP TDP USB20_P1 <28>
<28> SLP_CHG_M3 SLP_CHG_M3 4 5 +5VALW @ D86
CB1 VCC USB20_P1_R U3RXDN1_L U3RXDN1_L U3RXDN2_L U3RXDN2_L
9 PGND 1 2 2 5 5 66 5 5 66
C892 1
MAX14600ETA+T_TDFN-EP8_2X2 USB20_N1_R 1
3 3 3 3 3 3
14600@ 0.1U_0402_10V7K
2 AZC199-02SPR7G_SOT23-3 8 8
YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9
A A
U5 14617@
MAX14617ETA+T

LUSB/RUSB/S&C
Custom 1.0
VCUAA
5 4 3 2 1
A B C D E
35mA for 3.3V level

close to pin 25 close to pin 38
UA1 +3VS 1 @ 2 0.1U_0402_16V4Z +DVDD_IO +AVDD 0.1U_0402_10V7K 0.1U_0402_10V7K 1 @ 2 +5VS
RA28 0_0603_5% 2 1 2 1 1 RA18 0_0603_5%
MIC1_R_R 4.7U_0402_6.3V6M 1 2 CA58 MIC1_R_C_R 22 1 +DVDD_IO 1
MIC1_R DVDD
1
MIC1_R_L 4.7U_0402_6.3V6M 1 2 CA57 MIC1_R_C_L 21 9 +3VS_DVDD CA4 CA42 CA47 CA37 CA50 CA39
MIC1_L DVDD_IO CA3 @ 10U_0603_6.3V6M
+AVDD 10U_0805_6.3V6M 1 2 1 2 2
17 25
2
MIC2_R AVDD1 +AVDD 2 10U_0603_6.3V6M 10U_0603_6.3V6M
16 MIC2_L AVDD2 38
650mA
+MIC1_VREFO_L 31 39 +PVDD 0.1U_0402_16V4Z
MIC1_VREFO_L PVDD1 +PVDD @ +3VS_DVDD LA11
+MIC1_VREFO_R 30 MIC1_VREFO_R PVDD2 46 +3VS 1 2
29 RA17 0_0603_5% 1 +PVDD 1 2 0.1U_0402_10V7K +5VS
MIC2_VREFO
1
1 1
1 2 PBY160808T-601Y-N_2P 1
1
15 45 SPKR+ CA46 CA45 CA33 0.1U_0402_10V7K
LINE2_R SPK_OUT_R+ SPKR- 10U_0805_6.3V6M CA48 CA44 CA36
14 44
2
LINE2_L SPK_OUT_R- 2 10U_0805_6.3V6M
close to pin39
2
2 1 2
20 40 SPKL+ 10U_0603_6.3V6M
MONO_OUT SPK_OUT_L+ SPKL-
SPK_OUT_L- 41
1 2 MONO_IN 12 place close to chip
CA59 100P_0402_50V8J PCBEEP 75_0402_1% 1
0.01U_0402_25V7K 10 33 RA19 HP_R <39> CA32 0.1U_0402_10V7K
<24> AZ_SYNC_HD SYNC HPOUT_R
@ CA65 1 2 32 RA20
HPOUT_L 75_0402_1% HP_L <39>
<24> AZ_RST_HD# 11 RESET# 2
close to pin19 SDATA_OUT 5 AZ_SDOUT_HD <24>
close to pin 28 8 AZ_SDIN0_HD_R 2 1
SDATA_IN AZ_SDIN0_HD <24>
2 RA30 1AC_JDREF 19 JDREF
RA23 33_0402_5%
10U_0603_6.3V6M 1 2CA60 20K_0402_1% 28 6 AZ_BITCLK_HD
LDO_CAP BCLK AZ_BITCLK_HD <24>
27 VREF
AC_VREF 1 2 CPVEE 34 CPVEE
CA54 2.2U_0402_6.3V6M 35 23 @ CA51 For EMI
CBN NC AZ_BITCLK_HD 2
1 1 1 2 36 24 1 1 2 @
CA55 CA56 CA53 2.2U_0402_6.3V6M CBP NC
48 10_0402_5% RA29 please place near codec
2.2U_0402_6.3V6M NC 10P_0402_50V8J
@ 2
2 2 <22> INT_MIC_DATA GPIO0/DMIC_DATA
INT_MIC_CLK_R 3 26
0.1U_0402_10V7K GPIO1/DMIC_CLK AVSS1
AVSS2 37
PVSS1 42
SENSE_A 13 43
SENSE_A PVSS2
2 @ 1 SENSE_B 18 SENSE_B DVSS 7
RA34 20K_0402_1%
47
AGND
2 <40> EC_MUTE# 4
EAPD
PD# Thermal Pad 49 Beep sound 2
ALC259-VC2-CG_MQFN48_6X6
For EMI PCI Beep RA52

CA70
1 2 1 2 MONO_IN
<24> PCH_SPKR
RA42
INT_MIC_CLK_R DGND 47K_0402_5%
0.1U_0402_10V7K
<22> INT_MIC_CLK
FBMA-10-100505-301T
CAM@ EC_MUTE# Internal AMP
1 Hight Enable
LOW Disable
2
CA52 CAM@
220P_0402_50V7K RA49 CA69
2 100P_0402_50V8J
4.7K_0402_5%
change to SM010027780
1
EC_MUTE#
2
2W 4ohm =40mil placement near Audio Codec
1W 8ohm =20mil RA50
LA7 4.7K_0402_5%
SPKL+ 2 1 SPK_L1
SPK_L1 <39>
0_0603_5% 2 To solve noise issue
1
CA71
2
1000P_0603_50V7K CA74
1 1U_0402_6.3V4Z
2 @
CA72 1
LA8 1000P_0603_50V7K
3 SPKL- 1 SPK_L2 3
2 1
0_0603_5%
LA9
SPK_L2 <39>
Ext.MIC/LINE IN JACK
SPKR+ 2 1 SPK_R1
SPK_R1 <39>
0_0603_5% 2
CA76
RA47 2 1 +MIC1_VREFO_R
1000P_0603_50V7K 2 1K_0402_5% RA48 2.2K_0402_5%
1 CA73 MIC1_R_R 2 1 MIC1_R <39>
2 1U_0402_6.3V4Z
CA75 @
1 MIC1_R_L 2 1 MIC1_L <39>
LA10 1000P_0603_50V7K 1K_0402_5%
SPKR- 1 SPK_R2 RA45
2 1 SPK_R2 <39> 2 1 +MIC1_VREFO_L
0_0603_5% RA46 2.2K_0402_5%
EMI request
Sense Pin Impedance Codec Signals Function place close to chip

CA63 1 2 0.1U_0603_50V7K
39.2K PORT-I (PIN 32, 33) Headphone out <39> MIC_SENSE 2 1 SENSE_A
RA32 20K_0402_1% CA61 1 2 0.1U_0603_50V7K
20K PORT-B (PIN 21, 22) Ext. MIC CA66 1 2 0.1U_0603_50V7K

SENSE A CA62 1 2 0.1U_0603_50V7K
4
10K PORT-C (PIN 23, 24) <39> NBA_PLUG
RA33 39.2K_0402_1% 4
1 2
5.1K (PIN 48) RA31 0_0603_5%
39.2K PORT-E (PIN 14, 15)
SENSE B 20K PORT-F (PIN 16, 17)

10K PORT-H (PIN 20) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDA-ALC259-VC
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
A B C D E
HeadPhone/LINE OUT JACK
JLINE @
8
7
3
1
4
2
LA121 2 HP_L_L
<38> HP_L
CHILISIN PBY100505T-121Y-N 0402 5
6
LA6 1 2 HP_R_L SINGA_2SJ2285-001191

<38> HP_R
CHILISIN PBY100505T-121Y-N 0402
<38> NBA_PLUG
1
3
1 CA38 CA40 CA34 @
2 100P_0402_50V8J 100P_0402_50V8J
2
DA3 @ 0.1U_0402_10V7K
PJDLC05_SOT23-3
For EMI
EXT.MIC/LINE IN JACK
JEXMIC @
8
7
3
1
4
2
LA141 2 MIC1_L_L
<38> MIC1_L
CHILISIN PBY100505T-121Y-N 0402 5
6
LA131 2 MIC1_L_R SINGA_2SJ2285-001191

<38> MIC1_R
CHILISIN PBY100505T-121Y-N 0402
<38> MIC_SENSE
3 1
1
2 CA35 CA41 CA43 @
100P_0402_50V8J 100P_0402_50V8J
DA4 @ 2
PJDLC05_SOT23-3 0.1U_0402_10V7K
For EMI
SPK CONN.
@
DA5 PJDLC05_SOT23-3
3
1 JSPK @
2 6 GND2
5 GND1
<38> SPK_L1 4 4
<38> SPK_L2 3 3
<38> SPK_R1 2 2
<38> SPK_R2 1 1
PJDLC05_SOT23-3 E-T_3806K-F04N-03R
3
1
2
DA6
@

AUDIO CONN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
A B C D E
+3VL +3VL
0.1U_0402_10V7K 0.1U_0402_10V7K 1000P_0402_50V7K CB3

1 1 1 1 1 1 0.1U_0402_10V7K 1 @ 2 H_PROCHOT# <5>
<49> VR_HOT#
CB1 CB2 CB5 CB7 1 2 RB1 0_0402_5%
1
0.1U_0402_10V7K D
For EMI CB4 CB6 QB1 1
2 2 2 2 2 2 H_PROCHOT#_EC 2 CB8
111
125
0.1U_0402_10V7K 1000P_0402_50V7K G 47P_0402_50V8J
22
33
96
67
9
CLK_PCI_EC UB1
SSM3K7002F_SC59-3 S 2
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
EC_VDD0
1
3
RB3
10_0402_5%
@ GATEA20 1 21 WL_BT_LED#
1 <29> GATEA20 GATEA20/GPIO00 GPIO0F WL_BT_LED# <41> 1
KB_RST# 2 23 BATT_TEMPA 1 2
<29> KB_RST#
2
SERIRQ KBRST#/GPIO01 BEEP#/GPIO10 FANPWM CB9 100P_0402_50V8J
1 <24> SERIRQ 3 SERIRQ GPIO12 26 FANPWM <5>
CB11 LPC_FRAME# 4 27
<24,41> LPC_FRAME# LPC_FRAME# ACOFF/GPIO13
22P_0402_50V8J LPC_AD3 5 ACIN_D 1 2
<24,41> LPC_AD3 LPC_AD3
@ LPC_AD2 7 PWM Output CB10 100P_0402_50V8J
2 <24,41> LPC_AD2 LPC_AD2
LPC_AD1 8 63 BATT_TEMPA
<24,41> LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMPA <43>
LPC_AD0 10 LPC & MISC 64
<24,41> LPC_AD0 LPC_AD0 GPIO39
65 ADP_I
ADP_I/GPIO3A ADP_I <43,44>
CLK_PCI_EC 12 AD Input 66 ADP_V
<28> CLK_PCI_EC CLK_PCI_EC GPIO3B ADP_V <44> +3VS
PLT_RST# 13 75 MOS_TEMP
<28,34,35,41,5> PLT_RST# PCIRST#/GPIO05 GPIO42 MOS_TEMP <51>
EC_RST# 37 76 EC_ENBKL
+3VL EC_RST# IMON/GPIO43 EC_ENBKL <27>
RB2 EC_SCI# 20
<29> EC_SCI# EC_SCII#/GPIO0E
47K_0402_5% 38 H_PROCHOT#_EC 1 @ 2
EC_RST# GPIO1D WOL_EN# RB6 10K_0402_5%
1 2 DAC_BRIG/GPIO3C 68 WOL_EN# <35>
70 3VALW_EN
EN_DFAN1/GPIO3D 3VALW_EN <45>
1 2 DA Output 71 PCH_SUSPWRDN# PCH_SUSPWRDN# <26>
CB12 0.1U_0402_10V7K KSI0 IREF/GPIO3E SUSACK#
55 KSI0/GPIO30 CHGVADJ/GPIO3F 72 SUSACK# <26>
KSI1 56
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
Reserve this signal to EC by SW demand
KSI3 58 83 EC_MUTE#
KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# <38> 2011/10/18a
KSI4 59 84 USB_EN#0
KSI4/GPIO34 USB_EN#/GPIO4B USB_EN#0 <37>
KSI5 60 85
KSI6 KSI5/GPIO35 CAP_INT#/GPIO4C
61 KSI6/GPIO36 PS2 Interface EAPD/GPIO4D 86
KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK <41> +3VL
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <41>
KSO1 40
KSO2 KSO1/GPIO21
41 KSO2/GPIO22
KSO3 42 97 VGATE
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 VGATE <26,49>
KSO4 43 98 EC_DRAMRST_CNTRL_PCH
KSO4/GPIO24 WOL_EN/GPXIOA01 EC_DRAMRST_CNTRL_PCH <7>
KSO5 PWRME_CTRL LID_SW#
KSO6
44 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 99
VCIN0_PH
PWRME_CTRL <24> 1
RB35
2
47K_0402_5%
45 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 109 VCIN0_PH <43>
KSO7 46 SPI Device Interface VCIN0_PH connect to
2 KSO8 KSO7/GPIO27 +3VS 2
47 KSO8/GPIO28 power portion (9012 only)
KSO9 48 119
KSI[0..7] KSO10 KSO9/GPIO29 SPIDI/GPIO5B EC_BT_ON# TP_CLK
<41> KSI[0..7] 49 KSO10/GPIO2A SPIDO/GPIO5C 120 EC_BT_ON# <34> 1 2
KSO11 50 SPI Flash ROM 126 GPS_DOWN# RB8 4.7K_0402_5%
KSO[0..15] KSO11/GPIO2B SPICLK/GPIO58 GPS_DOWN# <13>
KSO12 51 128
<41> KSO[0..15] KSO12/GPIO2C SPICS#/GPIO5A
KSO13 52 TP_DATA 1 2
KSO14 KSO13/GPIO2D RB9 4.7K_0402_5%
53 KSO14/GPIO2E
KSO15 54 73
RB12 2.2K_0402_5% KSO15/GPIO2F ENBKL/GPIO40
81 KSO16/GPIO48 PECI_KB930/GPIO41 74
+3VL 1 2 EC_SMB_CK1 82 KSO17/GPIO49 FSTCHG/GPIO50 89 SYSON 1 2
1 2 EC_SMB_DA1 BATT_CHG_LED#/GPIO52 90 BATT_FULL_LED#
BATT_FULL_LED# <41>
RB10 4.7K_0402_5%
RB13 2.2K_0402_5% 91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# <41>
EC_SMB_CK1 77 GPIO 92 PWR_SUSP_LED#
<43,44> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_SUSP_LED# <41>
RB15 2.2K_0402_5% EC_SMB_DA1 78 93 BATT_CHG_LOW_LED#
<43,44> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_CHG_LOW_LED# <41>
+3VS 1 2 EC_SMB_CK2 <13,25> EC_SMB_CK2
EC_SMB_CK2 79 SM
EC_SMB_CK2/GPIO46 Bus SYSON/GPIO56 95 SYSON
SYSON <46>
1 2 EC_SMB_DA2 <13,25> EC_SMB_DA2
EC_SMB_DA2 80 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 121 VR_ON
VR_ON <49>
RB16 2.2K_0402_5% 127 USB_OC#0
PM_SLP_S4#/GPIO59 USB_OC#0 <28,37>
PM_SLP_S3# 6 100 PCH_RSMRST#

<26> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 PCH_RSMRST# <26>
SLP_S5# 14 101 EC_LID_OUT#
PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# <29>
EC_SMI# 15 102 PROCHOT_IN VCOUT0_PH_L 1 @ 2
<29> EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 PROCHOT_IN <43> VS_ON <45>
USB_OC#2 16 103 H_PROCHOT#_EC PROCHOT_IN connect RB34 0_0402_5%
<28,37> USB_OC#2 GPIO0A H_PROCHOT#_EC/GPXIOA06
<26,5> PM_PWROK 1 @ 2 PM_PWROK_EC <28,37> USB_OC#1
USB_OC#1 17 GPIO0B VCOUT0_PH/GPXIOA07 104 VCOUT0_PH_L to power portion (9012 only) VCOUT0_PH connect to power portion (9012 only)
RB32 0_0402_5% USB_CHG_EN# 18 GPO 105 BKOFF#
<37> USB_CHG_EN# GPIO0C BKOFF#/GPXIOA08 BKOFF# <22>
USB_EN#2 19 GPIO 106 PBTN_OUT# RB18
<37> USB_EN#2 GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# <26>
KB_LED 25 107 PCH_PWR_EN 330K_0402_5%
<41> KB_LED EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 PCH_PWR_EN <42>
FAN_SPEED1 28 108 SA_PGOOD 2 1 +3VL
<5> FAN_SPEED1 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 SA_PGOOD <48>
WL_OFF# 29
<34> WL_OFF# EC_PME#/GPIO15
E51_TXD 30
<34> E51_TXD EC_TX/GPIO16
E51_RXD 31 110 ACIN_D ACIN_D 2 1
<34> E51_RXD EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN <26,44>
PM_PWROK_EC 32 112 EC_ON_R RB751V40_SC76-2 DB1
3 PWR_ON_LED# PCH_PWROK/GPIO18 EC_ON/GPXIOD02 ON/OFFBTN# 3
Close to EC <41> PWR_ON_LED# 34 SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 114 ON/OFFBTN# <41>
36 GPI 115 LID_SW#
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# <41>
@ 116 SUSP#
SUSP#/GPXIOD05 SUSP# <42,47,48>
1 2 SUSP# 117
CB14 180P_0402_50V8J GPXIOD06 EC_PECI H_PECI
PECI_KB9012/GPXIOD07 118 1 2 H_PECI <5>
AGND/AGND
122 RB19 43_0402_1% SUSP# 1 2

CLK_EC XCLKI/GPIO5D +EC_V18R RB21 10K_0402_5%
GND/GND
GND/GND
GND/GND
GND/GND
<26> CLK_EC 123 XCLKO/GPIO5E V18R 124

1
GND0
VR_ON 1 2
CB15 RB23 10K_0402_5%
1
1 4.7U_0805_10V4Z
+3VALW CB17 RB22 CB16 KB9012QF-A3_LQFP128_14X14 2
11
24
35
94
113
69
0.1U_0402_10V7K 100K_0402_5% 20P_0402_50V8

1 2
2
2
5
UB2
1
P
<26> PM_SLP_S5# B
4 SLP_S5#
Y RB36
<26> PM_SLP_S4# 2 A
G
EC_ON_R 1 2 EC_ON <45>

TC7SH08FUF_SSOP5
3
2.2K_0402_5% 1
@ 1U_0402_6.3V6K
1 2 CB50
RB25 0_0402_5% 2
For KB9012 EC_ON low pulse work around

4 4
RB27 Voltage Comparator Pins FOR 9012 A3

100K_0402_5%
1 2 E51_TXD
VCIN0 pin109 >1.2V <1.2V
VCIN1 pin102
HIGH
VCOUT0 pin104 LOW Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title
(default)
LOW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LPC-EC-KB9012&930
VCOUT1 pin103 HIGH AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
(default) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
A B C D E
5 4 3 2 1
Power Button LPC Debug Port Place the PAD under DDR DIMM.
TJG-533-V-T/R_6P
3 1
Place on BOT 4 2 JDB @

+3VL 1 +3VS
Debug used SW2 @ 1
2
5
6
2
@ after PVT 3 3 PLT_RST# <28,34,35,40,5>
2
4 CLK_PCI_DDR
4 CLK_PCI_DDR <28>
R395 5
5 LPC_FRAME# <24,40>
6 6 LPC_AD3 <24,40>
100K_0402_5% 7
TJG-533-V-T/R_6P 7 LPC_AD2 <24,40>
8 LPC_AD1 <24,40>
1
D ON/OFFBTN# 8 D
3 1 ON/OFFBTN# <40> 9 9 LPC_AD0 <24,40>
10 10
Place on TOP 4 2 1 GND 11
C458 12
5
SW3 0.1U_0402_25V6 GND
6
@ E-T_3801K-F10N-01L
2
For EMI request

D2 C457 R393
2 1 2 1 2 CLK_PCI_DDR
1
3 22P_0402_50V8J 22_0402_5%
For ESD request @ @
close to SW3 L30ESD24VC3-2_SOT23-3
For EMI
LED/LID/TP SMALL BOARD Keyboard LED

Q38 KBL@
JBLG @
Screw Hole
1 1 +5VS_LED
+5VS AO3413_SOT23 2
2
5 G1 3 3
D
3 1 +5VS_LED 6 G2 4 4 CPU VGA
1
1
E-T_7182K-F04N-00R H12 H13 H14 H15 H16
R587 C836 H_4P3x3P8 H_3P8 H_4P3 H_3P0x3P7 H_3P0
G
2
Swap pin assign to avoid DDR interference 10K_0402_5% 0.1U_0402_10V7K @ @ @ @ @
KBL@ 2 KBL@
1
2
C C
JLED @
+3VL 14 14 GND2 16
1
13 15 D
+3VS 13 GND1
+5VALW 12 2 Q52
12 <40> KB_LED KSO0
<40> BATT_FULL_LED# 11 11 G 2N7002KW_SOT323-3 1 2
10 KBL@ C406 100P_0402_50V8J
<40> BATT_CHG_LOW_LED# 10
9 S KSO1 1 2
<40> PWR_ON_LED# 9
3
8 C405 100P_0402_50V8J PTH
<40> PWR_SUSP_LED# 8
7 KSO2 1 2 NPTH
<40> WL_BT_LED# 7
6 C404 100P_0402_50V8J H1 H2 H3 H5 H6
<40> LID_SW# 6
5 KSO3 1 2 H_2P8 H_3P0 H_3P0 H_3P0 H_3P0
5 C408 100P_0402_50V8J @ @ @ @ @ H17 H18
<40> TP_DATA 4 4
3 KSI0 1 2 H_3P2N H_3P2x3P7N
<40> TP_CLK
NEW KEYBOARD CONN.
1
3 C425 100P_0402_50V8J @ @
<11,12,25,34> PM_SMBDATA 2 2
1 KSO4 1 2
<11,12,25,34> PM_SMBCLK
1
1 C407 100P_0402_50V8J
HB_A021419-SAHR31 KSI[0..7] KSI1 1 2
KSI[0..7] <40>
C431 100P_0402_50V8J H7 H8 H9 H11 H10 H21 H19 H20
KSO[0..15] KSI2 1 2 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P2x3P7N H_3P3N
KSO[0..15] <40>
C422 100P_0402_50V8J @ @ @ @ @ @ @ @
KSI3 1 2
1
C423 100P_0402_50V8J
KSI4 1 2
C424 100P_0402_50V8J
KSO5 1 2
C409 100P_0402_50V8J
JKB @ KSI5 1 2
32 C427 100P_0402_50V8J
G2 KSO6
31 1 2
G1
30
29
30
29
KSO2
KSO1 KSI6
C411
1
100P_0402_50V8J
2
PCB Fedical Mark PAD
D89 28 KSO0 C429 100P_0402_50V8J
TP_DATA 28 KSO4 KSI7
2 27 27 1 2
1 26 KSO3 C421 100P_0402_50V8J FD1 FD2 FD3 FD4
TP_CLK 26 KSO5 KSO7
3 25 25 1 2
24 KSO14 C412 100P_0402_50V8J @ @ @ @
YSDA0502C_SOT23-3 24 KSO6 KSO8
23 1 2
1
@ 23 KSO7 C415 100P_0402_50V8J
B 22 22 B
21 KSO13 KSO9 1 2
21 KSO8 C416 100P_0402_50V8J
please place near JTP 20 20
19 KSO9 KSO10 1 2
19 KSO10 C417 100P_0402_50V8J
18 18
17 KSO11 KSO11 1 2
17 KSO12 C418 100P_0402_50V8J
16 16
15
14
13
15
14
13
KSO15
KSI7
KSI2
KSO12
KSO13
1
C419
1
C413
2
100P_0402_50V8J
2
100P_0402_50V8J
ISPD PCH CPU GPU
12 12
11 KSI3 KSO14 1 2
11 KSI4 C410 100P_0402_50V8J
10 10
9 KSI0 KSO15 1 2 ZZZ UH1 HM77R3@ (Default) UV4 N13PGSR1@
9 KSI5 C420 100P_0402_50V8J
8 8 CPU@ (Default)
7 KSI6 SA00004SX00 N13PGLR1@
7 KSI1 DAZ0T700100
6 SA00005AGP0 SA000051A00 SA000051880
6
5 5
4 JKB4 2 1 +3VS
4 CAPS_LED# R376 300_0402_5% CAPS_LED# PCB LA-9161P Panther Point 82HM77 C-1 HM77 N13P-GS-A2 FCBGA
3 3 CAPS_LED# <40> 1 2
2 C403 100P_0402_50V8J
2 UC1 CPUI5@ UC1 CPUI3@
1 1
CVILU_CF20302U0RG-NH For EMI

SA00005K690 SA00005L590 UV4 N13PGLR3@ UV4 N13PGSR3@
(Default)
Close to JKB HM77R1@
BD82HM77 SLJ8C C1 Ivy Bridge i5-3317U R1 Ivy Bridge i3-3217U R1 SA000051A60 SA0000518C0
SA00005AGH0
N13P-GL-A1 N13P-GS-A2
UH1 HM77@ UC1 CPUI5R3@ UC1 CPUI3R3@
SA00005AG30 SA00005K6G0 SA00005L5G0

PJP1 45@
A Panther Point 82HM77 C-1 HM77 Ivy Bridge i5-3317U R3 Ivy Bridge i3-3217U R3 A
PJP1

TP/ISPD/KB/Screw
1.0
VCUAA
5 4 3 2 1
A B C D E
+3VALW TO +3VS +5VALW TO +5VS

Vgs=10V,Id=9A,Rds=18.5mohm +1.8VS
+3VALW +3VS Vgs=10V,Id=9A,Rds=18.5mohm +5VALW +5VS
2
4.7U_0805_10V4Z +5VS +5VALW
1 1 1 1 R470
Q29 C459 C460 4.7U_0805_10V4Z Q30 C461 C462 470_0805_5%
2
470_0805_5%
470_0805_5%
8 D S 1 8 D S 1 For EMI
2
7 2 7 2 1U_0402_6.3V6K R5545
1
D S 2 2 R406 D S 2 2 R407
0.1U_0402_10V7K
0.1U_0402_10V7K
6 D S 3 6 D S 3 10K_0402_5%
5 D G 4 5 D G 4 2 2
1U_0402_6.3V6K C822 C821
1
D Q190
SI4800BDY_SO8 1 R409 2 +VSB SI4800BDY_SO8 1 R410 2 +VSB <30,31> PCH_PWR_EN# PCH_PWR_EN#
3 1
3 1
120K_0402_5% SUSP
0.01U_0402_25V7K
200K_0402_5% @ @
0.022U_0402_25V7K
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1 1 1 1 1 2 1
6
C466 1 1 2N7002KW_SOT323-3 G
C465 R412 Q10A Q10B C467 C468 R413 Q11A
1
820K_0402_5% 820K_0402_5% Q11B D S
3
2 2 SUSP 2 2 @ SUSP 2N7002KDWH_SOT363-6 Q5527
2 5 2 5 <40> PCH_PWR_EN 2
2N7002KDWH_SOT363-6 G
2
1
2N7002KDWH_SOT363-6 S SB570020110
3
2N7002KDWH_SOT363-6 2N7002E-T1-E3_SOT23-3
R5529
100K_0402_5%
change R409 to 120k 5%
2
+1.5V to +VRAM_1.5VS
+1.5V +VRAM_1.5VS
+5VALW +0.75VS +1.05VS_VCCP
Vgs=10V,Id=14.5A,Rds=6mohm
For S3 CPU Power Saving
2
1 1 <34,5,9> SUSP
Q46 OPT@ C479 C476 R422 R421 R468
8 OPT@ OPT@ 470_0805_5% 100K_0402_5% 22_0805_5% 470_0805_5%
D S 1 1
2
7 1U_0402_6.3V6K 4.7U_0805_10V4Z C44

D S 2 2 2 R429
6 S 3
1
D
220P_0402_50V6K
5 OPT@ SUSP
D G 4 OPT@ 2
6
FDS6676AS_SO8 VRAM_1.5VS_GATE 1 R432 2 1 2 0.75VR_EN
1
+VSB <47,48> VCCP_PWRGOOD 0.75VR_EN <46> D Q189 D
3 1
220K_0402_5% Q60
4.7U_0805_10V4Z
1 1 SUSP
1
2 2
0.1U_0402_25V6
R158 220K_0402_5% Q6A

G G
3
C473 C482 R430 Q13A 2 2N7002KDWH_SOT363-6
<40,47,48> SUSP#
OPT@ OPT@ 820K_0402_5% OPT@ Q13B
2 2 2 S 2N7002KW_SOT323-3 S 2
OPT@ 2 VGA_PWROK# 2N7002DW-T/R7_SOT363-6 Q6B
3
5
1
2N7002DW-T/R7_SOT363-6 OPT@ SUSP 2N7002KDWH_SOT363-6 2N7002KW_SOT323-3
5 ESD request 8/6
2
+5VALW
4
<34> VGA_PWROK# 1 OPT@ 2
100K_0402_5% R146
1
Q188 D
<29,51> VGA_PWROK 2
G 2N7002KW_SOT323-3
Reserve CAP to avoid Power Noise ESD Cap., please keep original location EMI request
OPT@
S
3
+5VALW +3VS +0.75VS +GFX_CORE
1 1 1 1 1 1 1 1 1 1 1
1
+5VALW +5VALW B+ +5VALW C32 C33 C28 C40 C20 C21 C36 C37 C38 C39 C30 C1
+1.05VS_VCCP to +1.05VS_DGPU
680P_0402_50V7K
0.1U_0402_6.3V6K
0.1U_0402_6.3V6K
0.1U_0402_6.3V6K
0.1U_0402_6.3V6K
0.1U_0402_6.3V6K
0.1U_0402_6.3V6K
0.1U_0402_6.3V6K
0.1U_0402_6.3V6K
0.1U_0402_6.3V6K
0.1U_0402_6.3V6K
0.1U_0402_6.3V6K
2
2 2 2 2 2 2 2 2 2 2 2
1 1 1 1 1 1 1 1
C22 C23 C24 C25 C26 C27 C42 C41
@ @ @ @ @ @ @
+5VALW
10U_0805_25V6K
+1.05VS_VCCP
10U_0603_6.3V6K
10U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_10V7K
0.1U_0402_6.3V6K
0.1U_0402_6.3V6K
0.1U_0402_6.3V6K
2 2 2 2 2 2 2 2
+1.05VS_DGPU
1
Vgs=4.5V,Id=3A,Rds<22mohm
R434
2
330K_0402_5%
Q56 OPT@ R460
1
D 22_0805_5%
3 3
2
2 OPT@
G +5VALW +0.75VS +VCCSA
1
S 1
3
AO3416_SOT23-3
0.1U_0402_25V6
OPT@ C493
OPT@ Q207A 1 1 1 1 1
2 Q207B C29 C43 C31 C34 C35
2 VGA_PWROK# 5 @ @ @ @
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
0.1U_0402_10V7K
10U_0603_6.3V6K
0.1U_0402_6.3V6K
0.1U_0402_6.3V6K
0.1U_0402_6.3V6K
+1.05VS_DGPU 2 2 2 2 2
OPT@ OPT@
1
1 1
C685 C686
4.7U_0402_6.3V6M 1U_0402_6.3V6K
@ OPT@
2 2
+3VS to +3VS_DGPU
+3VS
+3VALW +3VS_DGPU +VGA_CORE
2
2
2
2 Vgs=-4.5V,Id=3A,Rds<97mohm R458 R459

R433 C491 470_0805_5% 470_0805_5%
100K_0402_5% 0.1U_0402_10V7K OPT@ OPT@
OPT@ OPT@
3 1
1
1
S
R426 Q54
1
G Q55 D
DGPU_PWR_EN# 1 2 2
Q206B 2
4 +3VS_DGPU G 2N7002KW_SOT323-3 4
47K_0402_5% 2 AO3413_SOT23 D 2N7002DW-T/R7_SOT363-6 5 DGPU_PWR_EN#
1
6
OPT@ OPT@ OPT@

Q206A C492 S OPT@
3
4
OPT@ OPT@ 0.01U_0402_25V7K

1
<28,51> DGPU_PWR_EN 2 1
2N7002DW-T/R7_SOT363-6 1
C683 C684
1
4.7U_0805_10V4Z 1U_0402_6.3V6K
@ 2 OPT@
2 Security Classification Compal Secret Data Compal Electronics, Inc.
DC-DC INTERFACE
1.0
VCUAA
A B C D E
A B C D
PL1
HCB2012KF-121T50_0805 PH1 under CPU botten side :
1 2 VIN CPU thermal protection at 93 +-3 degree C Please locate these parts
PF1 PL2
Near EC chip
7A_32V_S1206-H-7.0A HCB2012KF-121T50_0805 Recovery at 56 +-3 degree C
DC_IN_S1 2 1 DC_IN_S2 1 2
@ PJP3
+3VL
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
+ 1
100P_0402_50V8J
1
1
2 <40,44> ADP_I
1
+ 1
PC1
PC2
PC3
PC4
12.1K_0402_1%
2
1
1K_0402_1%
3
2
-
PR4
PR1
- 4
ACES_50305-00441-001
2
PR2 PR5
0_0402_5% 0_0402_5%
100K_0402_1%_TSM0B104F4251RZ
<40> PROCHOT_IN 1 2 <40> VCIN0_PH 1 2
1
20K_0402_1%
PL3
1
HCB2012KF-121T50_0805 @PC11
@ PC11
PR3
PH1
1 2 0.1U_0402_10V7K
VMB
2
1
2
PL4
@PJP2
@ PJP2 PF2 HCB2012KF-121T50_0805
1 BATT_S1 2 1 1 2
1 BATT+
2 2
3 10A_125V_S6125-F-10.0A
3 BATT_P4
4 4
5 BATT_P5
5
1
6 EC_SMDA PC7
6 PC6
1
7 EC_SMCA @ PC5
7 PR16 .1U_0402_16V7K 1000P_0402_50V7K 0.01U_0402_25V7K
8
2
8 1K_0402_1%
9 9
GND 10
11
2
2 GND
+VSBP
2
12 3 1
GND
GND 13 B+
0.22U_0603_25V7K
0.1U_0603_25V7K
100K_0402_1%
SUYIN_200070GR009G106ZR
1
PD2
1
1
PR6
PC9
PJSOT24C_SOT23-3
PC8
2
PD1 1 VL @
2
PJSOT24C_SOT23-3 3 @ PQ1
2
PR10 PR7 TP0610K-T1-E3_SOT23-3
6.49K_0402_1% 22K_0402_1%
2
2 1 1 2 VSB_N_001
+3VL
1VSB_N_003
PR8
100K_0402_1%
1
PR11 PR9
1
0_0402_5% D
1K_0402_1%
<26,45> POK 1 2VSB_N_002 2 PQ2
G SSM3K7002FU_SC70-3
2
2
.1U_0402_16V7K
S
3
1
PC10
PR13 PR12 BATT_TEMPA <40>
100_0402_1% 100_0402_1%
2
@
1
EC_SMB_DA1 <40,44>
EC_SMB_CK1 <40,44>
3 3
@ PJ332
2 @ PJ152 @ PJ76
+3VALWP 2 1 1 +3VALW
2 1 1 2 1
JUMP_43X118 2
JUMP_43X118
+0.75VSP 2 1
JUMP_43X39
+0.75VS
RTC Battery
(7.5A,300mils ,Via NO.= 10)
OCP=10A @ PJ153 (0.5A,40mils ,Via NO.= 1)
@ PJ352 +1.5VP 2 2 1 1 +1.5V - PBJ1 + PR14
560_0603_5%
PR15
560_0603_5%
+5VALWP 2 1 +5VALW JUMP_43X118 2 1 1 2 1 2 +RTCBATT
2 1
(10A, 400mils ,Via NO.= 20)
JUMP_43X118
OCP=12.7A
(15A,600mils ,Via NO.= 30) @ MAXEL_ML1220T10
OCP=20A @ PJ462
+VCCSAP 2 2 1 1 +VCCSA
JUMP_43X118 SP093MX0000
@ PJ333
+3VLP 2 1 +3VL
(6A,240mils ,Via NO.= 12)
2 1
OCP=7.5A
JUMP_43X39
(100mA,40mils ,Via NO.= 2)
@ PJ3
+VSBP 2 2 1 1 +VSB
4 4
JUMP_43X39
(120mA,40mils ,Via NO.= 1)
@ PJ182
+1.8VSP 2 2 1 1 +1.8VS Security Classification Compal Secret Data Compal Electronics, Inc.
JUMP_43X118 Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title
(1.54A,60mils ,Via NO.= 3) PWR-DCIN / BATT CONN / OTP
Size
Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS VCUAA
A B C D
A B C D
for reverse input protection
1
D
2 PQ209
G SSM3K7002FU_SC70-3
S
3
PR225 PR226
1 2 1 2
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1
1M_0402_5% 3M_0402_5% 1
PC216
1
1
PC211
PC212
AON6504_POWERDFN56-8-5
VIN P1 PQ205 P2 B+ PQ207
2
PQ203 DMG4406LSS_SO8 PR211 PL201 @ @ DMG4406LSS_SO8
0.01_1206_1% 1UH_NRS4018T1R0NDGJ_3.2A_30%
1 1 8 1 4 1 2 8 1
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2 2 7 7 2
5 3 3 6 2 3 6 3
0.1U_0402_25V6
5 5
1
1
2200P_0402_50V7K
0_0402_5%
PC213
PC214
PC215
0.01U_0402_50V7K
@ PR231
1
VIN
0_0402_5%
PC231
@ PR232
4
PC234
2
2
1 2 @
PC230
2
1
2
3
2
PC236
<BOM Structure>
2
0.1U_0402_25V6 PD230
2
BQ24725_ACDRV_1 BAS40CW_SOT323-3
BQ24725_BATDRV 1 2BQ24725_BATDRV_1
0.1U_0402_25V6
0.1U_0603_25V7K
0.047U_0402_25V7K PR233
1 1
10_1206_1%
4.12K_0603_1%
PC237
1
PC238
PC235
PR228
1 2
5
2
1
2.2_0603_5%
PR229
PD231
BQ24725_VCC
2
RB751V-40_SOD323-2 PQ201
AON7408L
DH_CHG 4
BQ24725_BST 2
BQ24725_REGN2
4.12K_0603_1%
4.12K_0603_1%
2
PC239 2
BQ24725_LX
1
1 2 BATT+
PR234
PR235
DH_CHG
PL202
3
2
1
1U_0603_25V6K PC205 4.7UH_ETQP3W4R7WFN_5.5A_20% PR227
BQ24725_ACP
BQ24725_ACN
1 2 0.01_1206_1%
BQ24725_LX 1 2 CHG 1 4
2
1U_0603_25V6K
5
20
19
18
17
16
2 3
4.7_1206_5%
PU200
2200P_0402_50V7K
0.01U_0402_50V7K
CSON1
CSOP1
1
PR206
BTST
VCC
PHASE
HIDRV
REGN
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
21 PQ202
0.1U_0402_25V6
0.1U_0402_25V6
PAD
PC224
PC225
PC221
PC222
PC223
1
1
1 15 DL_CHG 4 AON7406L
ACN LODRV
PC240
PC241
2
2
680P_0603_50V8J
2 14 @
ACP GND PR236
3
2
1
2
1
BQ24725RGRR_VQFN20_3P5X3P5 10_0603_1%
PC206
BQ24725_CMSRC 3 13 SRP1 2 CSOP1
CMSRC SRP
1
PR237
2
6.8_0603_5%
BQ24725_ACDRV 4 12 SRN1 2 CSON1
2
ACDRV SRN
+3VALW 1 2 BQ24725_ACOK 5 ACOK BATDRV 11 BQ24725_BATDRV PC242

@PR238
@ PR238 10K_0402_1% 0.1U_0603_16V7K
ACDET
IOUT
SDA
ILIM
SCL
1 2 +3VALW
+3VL
6
10
PR239 10K_0402_1%
3 3
BQ24725_ILIM 1 2
0.01U_0402_25V7K
1 2 PR241
<26,40> ACIN VIN
100K_0402_1%
PR240 10K_0402_1% 357K_0402_1%
PC243
PR242
1
BQ24725_ACDET
VIN 1 2
1
154K_0402_1%
PR243
2
1
270K_0402_1%
PR244
PR247
309K_0402_1%
PR248
2
10K_0402_1%
2
1 2 ADP_V <40>
Vin Dectector
0.1U_0402_25V6
1
66.5K_0402_1%
EC_SMB_CK1 <40,43>
1
1
@PC247
@ PC247
Min. Typ Max. PR249
1
PR245
0.1U_0402_10V7K
PC244
47K_0402_1%
H-->L 17.23V
2
EC_SMB_DA1 <40,43>
2
2
L--> H 17.63V
2
PC245 PR246
ILIM and external DPM 2 1 2 1 ADP_I <40,43>
100P_0402_50V8J
3.97A 100_0402_5%
1
@ PC246
@PC246
0.1U_0402_10V7K
2
4 4
Please locate the RC

Near EC chip
2011-02-22

PWR-CHARGER
Size
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS VCUAA 1.0
A B C D
A B C D E
1 1
0_0402_5%
@ PQ3
3
S
PR335
SSM3K7002FU_SC70-3
<40> 3VALW_EN
G
2
D
1
PC345
100P_0402_25V8K PR350
1 2 30K_0402_1%
1 2
B+ PR330
3/5V_B+ 3/5V_B+
PL331 14K_0402_1%
HCB2012KF-121T50_0805 1 2
235K_0402_1%
156K_0402_1%
54.9K_0402_1%
2
2
1 2 PR331
PR337
PR342
PR357
20K_0402_1%
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
FB_3V PR351
4.7U_0805_25V6-K
1 2
10U_0805_25V6K
2200P_0402_50V7K
0.1U_0402_25V6
19.1K_0402_1%
1
PC358
1
680P_0603_50V7K
PC353
PC354
PC361
FB_5V 1 2
1
PC340
1
1
5
PC338
PC339
1
PC334
2
2
1U_0603_10V6K
2
2
5
AON7408L
2
1
PQ331
PC344
@
4
TON
FB2
ENTRIP2
ENTRIP1
FB1
<26,43> POK
21 PQ351
2
PAD
6 PGOOD
PC335 PR333 20 4 AON7518
0.1U_0402_10V7K 2.2_0402_1% BYP1 PR355 PC355
1
2
3
1 2 BST1_3V 1 2 BST_3V 7 BOOT2
2.2_0402_1% 0.1U_0402_10V7K
19 BST_5V 1 2 BST1_5V 1 2
BOOT1
3
2
1
2 UG_3V 2
8 UGATE2
PL332 18 UG_5V
4.7UH_ETQP3W4R7WFN_5.5A_20% UGATE1 PL352
2 1 LX_3V 9 S COIL 3.3UH +-20% KJ1040-3R3M 11A
+3VALWP PHASE2 LX_5V
PHASE1 17 1 2 +5VALWP
5
LG_3V 10 LGATE2
1
4.7_1206_5%
220U_6.3V_M
16 LG_5V
ENLDO
SECFB
LGATE1
4.7_1206_5%
PR336
LDO5
LDO3
1
VIN
PR356
150U_D2_6.3VY_R15M
PC331
+
1
4 PU330
1 SNUB_3V 2
11
12
13
14
15
+
PC351
RT8243AZQW_WQFN20_3X3
SNUB_5V 2
2
4
AON7406L PR334 +3VLP PQ352 2

1
2
3
680P_0603_50V8J
680P_0603_50V8J
PQ332 499K_0402_1% AON7212L_DFN8-5
1
1 2 PC341
3/5V_B+ VL
3
2
1
PC336
4.7U_0805_10V6K
1
100K_0402_1%
1U_0603_10V6K
PC356
0.1U_0603_25V7K
2
1
PC359
2
1
PC360
PR338
PC342
4.7U_0805_10V6K
2
3.3V
2
2
Peak Current 7.5A
OCP current 10A
PR340
Delta I=1.160A ,ripple=1.160 x17m=19.27mV 2.2K_0402_1%
5V
FSW=455kHz 1 2 Peak Current 15A
<40> EC_ON
3
DCR 35mohm +/-15% PR341 OCP current 18A 3
0_0402_5%
TYP MAX 1 2 FSW=400kHz
<40> VS_ON
4.7U_0805_25V6-K
0.1U_0402_25V6
Delta I=2.791A,ripple=2.791*15m=41.865mV
100K_0402_5%
H/S Rds(on) :27mohm , 34mohm
PC343
PR332
1
PC346
L/S Rds(on) :19mohm , 23.5mohm DCR 13.2mohm +/-5%
TYP MAX
2
2
@
1
H/S Rds(on) :11.2mohm , 14mohm
L/S Rds(on) :6.2mohm , 7.8mohm
4 4

PWR-3.3VALWP/5VALWP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VCUAA 1.0
A B C D E
A B C D
1 1
0.75Volt +/- 5%
Peak Current 1.5A

PL151
HCB1608KF-121T30_0603 OCP Current 1.5A
B+ 1 2 1.5V_B+ PR155
0_0603_5%
BST_1.5V-1 1 2 BST_1.5V +1.5V
PR154
2200P_0402_50V7K
10U_0805_25V6K
4.7U_0805_25V6-K
0_0603_5%
DH_1.5V-1 1 2 DH_1.5V +0.75VSP
1
0.1U_0603_25V7K
PC152
PC153
PC154
2
PC155
10U_0805_6.3V6K
10U_0805_6.3V6K
10U_0805_6.3V6K
SW_1.5V
2
1
PC159
PC160
PC161
@
1
5
DL_1.5V
16
17
18
19
20
PU150
2
PHASE
UGATE
BOOT
VLDOIN
VTT
AON7408L
21 @
PAD
PQ151
4 15 LGATE VTTGND 1
2 2
PR158 14 2
PL152 16.2K_0402_1% PGND VTTSNS
1
2
3
1UH_VMPI0703AR-1R0M-Z01_11A_20% 1 2CS_1.5V
2 1 13 3
+1.5VP PC162 CS RT8207MZQW_WQFN20_3X3 GND
5
1U_0603_10V6K
FDMC7692S_MLP8-5
1 2 12 4 VTTREF_1.5V
PR159 VDDP VTTREF
330U_D2_2.5VY_R9M
1 5.1_0603_5%
+1.5VP
PQ152
1 2 VDD_1.5V 11 5
VDD VDDQ
PC157
PGOOD
@PR156
@ PR156 4
1
4.7_1206_5%
TON
+5VALW PC163
FB
S5
S3
SNUB_+1.5VP 2
1
2 0.033U_0402_16V7K
2
PC164
1
2
3
10
6
1U_0603_10V6K
+5VALW
2
PR160
10.2K_0402_1%
FB_1.5V 2 1 +1.5VP
TON_1.5V
1
@ PC156
@PC156
680P_0402_50V7K
2
Mode Level +0.75VSP VTTREF_1.5V
2
PR161
S5 L off off
1
887K_0402_1% PR162 PC165
S3 L off on PR163 1.5V_B+ 1 2 10K_0402_1% .1U_0402_16V7K
S0 H on on 0_0402_5%
2
3 3
1 2 EN_1.5V
<40> SYSON
1
Note: S3 - sleep ; S5 - power off
EN_0.75VSP
1
@PC166
@ PC166 PR164
0.1U_0402_10V7K 0_0402_5%
2 1
2
<42> 0.75VR_EN
1.5V
1
Peak Current 10A
PC167
OCP current 12.7A 0.1U_0402_10V7K
2
FSW=500kHz
DCR 10mohm
TYP MAX
H/S Rds(on) :27mohm , 34mohm
L/S Rds(on) :9.6mohm , 13mohm
4 4

+1.5VP/+0.75VSP
Size
Document Number Rev
1.0
VCUAA
A B C D
5 4 3 2 1
D D
PR408
60.4K_0402_1% PL401
1 2 FBMA-L11-201209-121LMA50T_0805
<40,42,48> SUSP#
1.05_B+ 2 1
+3VS +5VALW
2
10K_0402_1%
.1U_0402_16V7K
1
@ PR409
2200P_0402_25V7K
100K_0402_1%
PC407
22U_0805_6.3VAM
22U_0805_6.3VAM
2
1
1
PR413
PC402
PC403
S TR AON7514 1N DFN
12K_0402_1%
PC411
PR405
5
2.2_0603_5%
2
PR412
PR403 1 2
0.1U_0603_25V7K
0_0402_5%
PQ401
<42,48> VCCP_PWRGOOD 1 2
PC405
4
C C
17
16
15
14
13
11K_0402_1% 9.76K_0402_1%
PU400
1
MODE
BST
PAD
PGOOD
EN
2
PR411
PL402
3
2
1
0.24UH_FDUE0630J-H-R24M-P3_22A_20%
+1.05VS_VCCP
0.1U_0402_25V6
1 12 LX_1.05VS_VCCP 1 2
VREF SW
1
2
PC408
S TR AON6508 1N DFN
4.7_0402_1%
PR406
2 11 DH_1.05VS_VCCP
2
REFIN DH
2
PQ402
PR410
PC413
0.01UF_0402_25V7K TPS51219RTER_QFN16_3X3
1
1SNUB_+1.05VSP 1
3 10 DL_1.05VS_VCCP 4
GSNS DL
<8> VCCIO_SENSE_VSS
1
4 9 +5VALW
3
2
1
VSNS V5
680P_0402_50V7K
COMP
PGND
TRIP
GND
PC406
1
PC410
5
8
1U_0603_10V6K
2
PR404 PR402 PC409
64.9K_0402_1%
10_0402_1% 10_0402_5% 0.01UF_0402_25V7K
1
<8> VCCIO_SENSE 1 2 1 2 1 2
PR407
2
B B
PC412
2
1000P_0402_50V7K
1
@ PR401
10_0402_1%
1 2
2
PC414
1000P_0402_50V7K
1
1.05V
Peak Current 14A
OCP current 15.08A
FSW=300kHz
Delta I=5.883A,Rippe=5.883x 4.5m=26.473Mv
DCR 3.7ohm +
TYP MAX
H/S Rds(on) :5.6mohm , 6.8mohm
A
L/S Rds(on) :3.7mohm , 5mohm A
Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2012/04/19 Deciphered Date 2015/04/19
PWR-V1.05SP/16V
Custom 1.0
VCUAA
5 4 3 2 1
5 4 3 2 1
VID [0] VID[1] VCCSA Vout

D
0 0 0.9V D
The 1k PD on the VCCSA VIDs are empty. 0 1 0.85V

These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability. 1 0 0.775V
1 1 0.750V
output voltage adjustable network
+3VS PR470
0_0402_5%
1 2
H_VCCSA_VID1 <9>
100K_0402_5%
1
PR469
PR471
0_0402_5%
1 2
VCCSA
H_VCCSA_VID0 <9>
TDC 4.2A
2
<40> SA_PGOOD 2 1 @ PC475 Peak Current 6.0A
0.033U_0402_16V7K
+VCCSA_PWRGD
PR472 1 2 OCP current 7.5A
0_0402_5%
Frequce = 700K
1U_0603_10V6K
+5VALW
PC472
PR473 PR468
10_0402_1% 0_0402_5%
1
2 1 +VCCSA_EN 1 2 VCCP_PWRGOOD <42,47>
PC473
C 2.2U_0603_10V7K C
1 2
18
17
16
15
14
13
PU460
PR474 PC474
V5DRV
V5FILT
PGOOD
VID1
VID0
EN
2.2_0603_1% 0.1U_0402_25V6
12 +VCCSA_BT 1 2+VCCSA_BT_1 1 2
BST PL462
19 PGND 0.47UH_VMPI0703AR-1R0M-Z01_11A_20%
SW 11 +VCCSA_PHASE 1 2 +VCCSAP
20 PGND
2200P_0402_25V7K
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
.1U_0402_16V7K
SW 10
21 PGND
2
PC461
PC462
PC477
PC463
PC478
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
PR466
0.1U_0402_25V6
PC476
TPS51463RGER_QFN24_4X4~D 9 4.7_1206_5%
SW
22
1
VIN
1
2
PC471
PC470
PC469
PC468
SW 8
1
23
2
PL461 VIN
PC466
HCB1608KF-121T30_0603 7 680P_0402_50V7K
SW
2
1 2 +VCCSA_PWR_SRC 24
+5VALW VIN
TP 25
COMP
MODE
SLEW
VOUT
VREF
1GND
6
2 1
PR475
100K_0402_5%
PR465
100_0402_5%
PC479 2 1
B B
2 1
0.22U_0402_16V7K~D
PR467
2 1 2 1 0_0402_5%
0.01U_0402_25V7K
2 1 +VCCSA_SENSE <9>
PC480 PR476
2
3300P_0402_50V7K 5.1K_0402_1%
PC481
PU180
PL181 SY8032ABC_SOT23-6 PL182
HCB1608KF-121T30_0603 1UH_NRS4018T1R0NDGJ_3.2A_30%
+5VALW 1 2 4 3 LX_1.8V 1 2 +1.8VSP
IN LX
68P_0402_50V8J
5 PG GND 2
1
4.7_0402_1%
1
1
PC187
PC184 6 FB EN 1
PR186
PR183
22U_0805_6.3VAM
20K_0402_1% VCCSA
22U_0805_6.3VAM
22U_0805_6.3VAM
2
2
2
PC183
PC182
1
FB_1.8V Peak Current 1.54A

2
2
680P_0603_50V7K
PR181 EN_1.8V OCP current 1.078A

<40,42,47> SUSP# 1 2
1
1
PC186
150K_0402_1%
A PR184 A
1
10K_0402_1%
1
@ PR182 PC185
2
499K_0402_1% @ 0.1U_0402_10V7K
2
2
DELL CONFIDENTIAL/PROPRIETARY
123
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR-VCCSAP/1.8VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VCUAA
5 4 3 2 1
A B C D E F G H
+CPU_CORE
1
@ PR501 PR502 @
100_0402_5% 100_0402_5%
2
@ PC501
2
0.1U_0402_25V6
1 2
+5VALW <8> VSSSENSE VCCSENSE <8>
1
PR503 PR504
1
1 0_0402_5% 0_0402_5% 1
PR515
2.2_0402_1%
2
VCC
10K_0402_1%_ERTJ0EG103FA
2
VCC RNTC1N
1
PR512 PR513 +CPU_5V PL501
1
@ PR507 PR508 PR509 @ PR511 PC502 PR542 49.9K_0402_1% 2.2_0402_1% HCB2012KF-121T50_0805
PH505
66.5K_0402_1%
22U_0805_6.3VAM
22U_0805_6.3VAM
680P_0603_50V8J
PR510 2.2U_0603_10V6K 3.3K_0402_1% 1 2 1 2 1 2 +5VALW
2
51K_0402_1%
10K_0402_1%
66.5K_0402_1%
0.1U_0402_25V6
1
2
PC503
PC510
PC504
PC508
10K_0402_1%
PC529
390P_0402_50V7K + PC500
2
1
RNTC1P PC507
2
SETINIA 0.1U_0402_25V6 2
5
SETINI
1
TEMPMAX S_A-P_CAP 220U 6.3V M 6.3X4.2 R17M VLPS
PQ503
ICCMAX PR514 PR505 PC505 PR522 S TR AON7514 1N DFN
3.3K_0402_1% 2.2_0603_5% 0.22U_0603_10V7K 0_0603_5%
ICCMAXA 1 2 1 2 1 2 4
2
+CPU_CORE
1
1
PR519 PR516 PR517 PR518 PR520 PL502
BOOT_CPU
10K_0402_1%
10K_0402_1%
33K_0402_1%
0.12UH FDUE0630-H-R12M=P3 32.5A
3
2
1
1
10K_0402_1%
10K_0402_1%
1 2
PR521
5
17.4K_0402_1%
4.7_0402_1%
2
2
PR524
PR506
1.58K_0402_1%
1
VCC PC509
390P_0402_50V7K 4 @ PR527
2 1
1
1.69K_0402_1%
2
PQ502 PC506
10K_0402_1%_ERTJ0EG103FA
10K_0402_1%_ERTJ0EG103FA
1 2
S TR AON6504 1N DFN 680P_0402_50V7K
PC511
2.55K_0402_1%
3
2
1
1
2
1
0.1U_0402_25V6
1 2
2
1
2.55K_0402_1%
PR547
PH502
PH501
FB_CPU
2 2
PR523
1 2 VCC
1
1
PR560 @
1
10K_0402_1%
1
PC512
2
10
PR528 0.1U_0402_25V6
1
PU500 10K_0402_1%
1
432_0402_1%
CPU_CORE
0.1U_0402_25V6
SETINIA
VCC
GFXPS2
RGND
FB
COMP
ISEN1N
ISEN1P
TONSET
BOOT1
2
2
PC513 PC514 PR530

1
TDC 16A
432_0402_1%
0.1U_0402_25V6
2
PR529
1
41 Peak Current 29A

2
GND
1
OCP current 48.5A
1
11 40 UG_CPU PC515
2
SETINI UGATE1 +5VALW
2.2U_0603_10V6K
12 39 PHASE_CPU
PR531 Load line -2.9mV/A
2
TMPMAX PHASE1
PR533 1 2 FSW=700kHz
PR532 OCSET 13 38 LG_CPU
13.3K_0402_1% ICCMAX LGATE1
VCC
0_0402_5%
0_0402_5% DCR 0.63mohm +/-7%
1 2 1 2 14 ICCMAXA PVCC 37
PVCC TYP MAX
15 36 LG_GFX
TSEN LGATEA
1

10K_0402_1%
PH503
1 2 16 RT8167BGQW WQFN 40P PWM 35 PHASE_GFX
PR534 OCSET PHASEA
VR_ON <40>
@ 10K_0402_1%_ERTJ0EG103FA 17 34 UG_GFX
TSENA UGATEA
2
18 33 BOOT_GFX
OCSETA BOOTA PR535
PR536 PR537 OCSETA 19 32 EN_GFX 1 2 PR538 PR539
IBIAS EN +CPU_5V
0_0402_5% 8.66K_0402_1% 57.6K_0402_1% 2.2_0402_1%
1
VCC 1 2 1 2 PR540 20 31 1 2 1 2 +GFX_5V

VRHOT TONSETA 0_0402_5%
53.6K_0402_1%
22U_0805_6.3VAM
22U_0805_6.3VAM
680P_0603_50V8J
1
0.1U_0402_25V6
10K_0402_1%
PH504
1
VRA_READY
PC517
PC518
1 2 PR541 PC516 PQ507
PC519
PC530
VR_READY
0.1U_0402_25V6 S TR AON7514 1N DFN

2
2
ISENAN
COMPA
ISENAP
@ 10K_0402_1%_ERTJ0EG103FA
RGNDA
PR525 PC525
ALERT
2
VCLK
2.2_0603_5% 0.22U_0603_10V7K
VDIO
2
FBA
1 2 1 2 4
1
PC521 PR544
PR543 75_0402_1% 2.2_0603_5%
AON7514
21
22
23
24
25
26
27
28
29
30
3 1 2 VR_HOT# 0.1U_0402_25V6 1 2 +GFX_CORE 3
+1.05VS_VCCP VR_HOT# <40>
2
SB00000VA00 PL503
3
2
1
PR545 10K_0402_1% 0.12UH FDUE0630-H-R12M=P3 32.5A
FB_GFX
+3VS 1 2 VGATE 1 2
5
VR_SVID_ALRT#
4.7_0402_1%
2
2
VR_SVID_DAT PQ506
PR526
VR_SVID_CLK S TR AON6504 1N DFN PR550
@ PR548 150_0402_1% 1.58K_0402_1%
+1.05VS_VCCP 1 2
4
2 1
1
PR549 130_0402_1% @ PR553
1 2 PC526 2K_0402_1%
1
680P_0402_50V7K 1 2
1
PR551
3
2
1
1
16.2K_0402_1%
1 2 PC522
330P_0402_50V7K
2
1
@ PC524 PR552 54.9_0402_1% PC520

2
0.1U_0402_25V6
0.1U_0402_25V6 1 2
2
<8> VR_SVID_ALRT#
1
1
3.3K_0402_1% 3.3K_0402_1%
PC527
<8> VR_SVID_DAT
PR554
0.1U_0402_25V6
2
10K_0402_1%_ERTJ0EG103FA
<8> VR_SVID_CLK
GFX_CORE
2
RNTCAP
<26,40> VGATE PC523
TDC 21.5A
1
220P_0402_50V8J
2
Peak Current 33A

PH506
PR555
OCP current 48.5A

Load line -3.9mV/A
2
RNTCAN
FSW=700kHz
DCR 0.63mohm +/-7%
1
4 4
PR556
0_0402_5%
PR557
0_0402_5%
TYP MAX
2
<9> VSS_AXG_SENSE 1 2 VCC_AXG_SENSE <9>

1
PC528 @
@ PR558 0.1U_0402_25V6
1
100_0402_5%
@ PR559
2
100_0402_5%
2

+GFX_CORE
PWR- CPU GFX CORE
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A2 LA-8551P 1.0
A B C D E F G H
5 4 3 2 1
+GFX_CORE
+CPU_CORE
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1
PC853
PC854
PC855
PC856
PC857
PC858
1
1
PC806 PC807 PC808 PC809 PC810 2 2 2 2 2 2
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
2
2
D D
+1.05VS_VCCP
1
1
PC811 PC812 PC813 PC814 PC815
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1
1
PC860
PC861
PC862
PC863
PC864
PC454
PC417
PC418
PC419
PC420
PC421
PC422
PC423
PC424
PC425
PC426
PC453
PC859
2
2
@
1
1
PC816 PC817 PC818 PC819 PC820 PC821
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
PC865
PC866
PC867
PC868
PC869
PC870
PC427
PC428
PC429
PC430
PC431
PC432
PC433
PC434
PC435
PC436
PC437
PC438
PC439
C C
2
+CPU_CORE
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1
1
PC872
PC873
PC874
PC876
PC875
PC440
PC441
PC442
PC443
PC444
PC445
PC446
PC447
PC448
PC449
PC450
PC451
PC452
PC834 PC835
22U_0805_6.3V6M 22U_0805_6.3V6M
2 2
2
470U_D2_2VM_R4.5M
1 1 1 1 1 1
PC822 PC823 PC824 PC825 PC826 PC827
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 1
2 2 2 2 2 2
+
PC852
1 1
330U_D2_2V_Y
330U_D2_2V_Y
2 + +
PC415
PC416
B
1 1 1 1 1 1 2 2 B
PC828 PC829 PC830 PC831 PC832 PC833 @
@
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2
+CPU_CORE Chief River ULV 330uF*9m 22uF 10uF 2.2uF 1uF
1 1
+ +
CPU 2 14 16
PC802 PC803
330U_D2_2V_Y 330U_D2_2V_Y
2 2
GFX_CORE 1 6 6 11
1.05V_VCCP 2 11 26
A A

PWR - PROCESSOR DECOUPLING
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS VCUAA 1.0
5 4 3 2 1
A B C D E F G H
VGA_Core
TDC 35A
Peak Current 42A
OCP current 65A
Load line -
FSW=300kHz
DCR 1.5~1.8mohm +/-5%
<28,42>
1 1
DGPU_PWR_EN
TYP MAX
<13>
<13>
<13>
<13>
<13>
<13>
VGA_VID_2
VGA_VID_3
VGA_VID_4
VGA_VID_5
VGA_VID_0
VGA_VID_1
H/S Rds(on) :11.2mohm , 14mohm
1K_0402_1% PR909 1 2 VGA_VID_0 2 1@ PR901 1K_0402_1%
L/S Rds(on) :3.7mohm , 5mohm
1K_0402_1% PR910 1 2 VGA_VID_1 2 1@ PR903 1K_0402_1%
1K_0402_1% PR911 @ 1 2 VGA_VID_2 2 1 PR904 1K_0402_1% Total capacitor

1K_0402_1% PR912 @ 1 2 VGA_VID_3 2 1 PR907 1K_0402_1% 1320u
ESR=2.25m ohm
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
1K_0402_1% PR942 1 2 VGA_VID_4 2 1@ PR902 1K_0402_1%
+5VS
1K_0402_1% PR946 @ 1 2 VGA_VID_5 2 1 PR940 1K_0402_1%
+VGA_B+
PR933
PR913
0.1U_0402_16V7K
2
330K_0402_1%
80.6K_0402_1%
+3VS PL901
2
PC904
HCB2012KF-121T50_0805
PR914
PR915
PR916
PR917
PR918
PR919
PR920
1 2 B+
PR936
1
10_0603_1%
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
1
220P_0402_25V8K
68P_0402_50V8J
0.1U_0402_25V6
1
PC901
PC902
1
1
PC917
PC918
PC919
PC903
32 VGA_EN
VID1
VID2
VID3
VID4
+3VS
2
1
VGA_VCC
5
PU900 PC916
1
1U_0603_10V6K
31
30
29
28
27
26
25
2
PR908
1K_0402_1% PQ901 PQ904
VID0
VID1
VID2
VID3
VID4
VID5
VID6
EN
24 PC909 4 AON75184 AON7518
2
VCC PR905 0.22U_0603_25V7K
<29,42> VGA_PWROK 1 PWRGD
PC908
BST 23 VGA_BOOST 1 2VGA_BOOST-1 1 2
1
1000P_0402_50V7K PR938 2 2.2_0603_5%

24.9K_0402_1% IMON VGA_DRVH PR937 PL902
22 2 1
3
2
1
3
2
1
PR923 DRVH 0.36UH_TMPC1203H-R36MG-D_30A_20%
2 1 2 3 0_0603_5% 2
2
0_0402_5% CLKEN# VGA_SW

21 1 2
<15> VGA_VSS_SENSE 2 1 4
SW +VGA_CORE
FBRTN PR939
4.7_1206_5%
ADP3211AMNR2G_QFN32_5X5 20 2 1 +5VS
S TR AON6508 1N DFN
S TR AON6508 1N DFN
PVCC
1
1 2 VGA_FB 5 0_0603_5%
FB
PQ902
PR906
VGA_DRVL
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
DRVL 19 2 1 1 1 1 1
1
PQ903
PC907 PC905 VGA_COMP 6
COMP + + + +
PC996
PC997
PC998
PC999
PR924 220P_0402_50V7K 47P_0402_50V8J 18 PC915
0_0402_5% VGA_VCC 7 PGND 2.2U_0603_10V6K 4 4
2
2
GPU
<15> VGA_VCC_SENSE 2 1 1 2 1 2VGA_COMP-1
1 2 AGND 17
VGA_ILIM 8 2 2 2 2
680P_0603_50V8J
CSCOMP
ILIM
1
PR921 PC906 PR922 33
CSREF
AGND
RAMP
LLINE
CSFB
PC910
1K_0402_1% 470P_0402_50V8J 20K_0402_1%
IREF
RPM
3
2
1
3
2
1
RT
2
9
10
11
12
13
14
15
16
2
PR925
6.81K_0402_1%
VGA_IREF
VGA_RAMP
VGA_CSFB
VGA_CSCOMP
VGA_RT
VGA_RPM
VGA_CSCOMP 1
2
237K_0402_1%
301K_0402_1%
PR929 422K_0402_1%
PR926
PR927
PR928
80.6K_0402_1%
1
1
1
1
PH901 @
1
PR934
@
2
PC913 PC914 220K_0402_1% 220K_0402_5%_TSM0B224J4702RE

Connect to input caps
2
2
1000P_0402_50V7K 560P_0402_50V7K
2
2
PR930 2 1
1K_0402_1%
3 3
+VGA_B+ 2 1 VGA_RAMP-1 PR935
200K_0603_1%
1
PC911 PC912
1000P_0402_50V7K 1000P_0402_50V7K
2
+VGA_CORE Under VGA Core +3VL

1 2
Near VGA Core PR931 PR932 LL
1
@ PR932
0_0402_5%
12.1K_0402_1%
1
+VGA_CORE
PR931
0_0402_5%
PR943
@ 0 X
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
2
1
1
PC929
PC941
PC930
PC925
PC933
PC924
PC943
PC940
0 @ V
2
VGA_CSCOMP PR945
0_0402_5%
2
47U_0805_4V6
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
100K_0402_1%_TSM0B104F4251RZ
1 1 1 1 <40> MOS_TEMP 1 2
1
@ PC952
@ PC953
PC948
PC950
PC944
2
2 2 2 @ 2
1
1
@ PC974
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
PH2
0.1U_0402_10V7K
1
1
PC921
PC935
PC936
PC922
PC937
PC942
PC931
2
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
2
2
1
PC945
PC949
PC947
PC946
PC951
4 4
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
PC932
PC939
PC938
PC928
@ PC927
@ PC934
@ PC923
@ PC926
2

+VGA_COREP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-8712P 1.0
A B C D E F G H
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase
DVT
1 HW command (Follow QFKAA) 45 change PR330 13K to 14K 2012/5/17
2
D D
HW command (Follow QFKAA) 45 change PR351 20K to 19.1K 2012/5/17 DVT
4 fine tune 1.5V ocp =12.6A 46 change PR158 13.3K to 16.2K 2012/5/17 DVT
5 fine the 1.05V vout volatge=1.059V 47 change PR411 10.5K to 9.76K 2012/5/17 DVT
6 fine tune the CPU load line =2.7mV 49 change PR521 14.3K to 17.4K 2012/5/17 DVT
7 fine tune the GFX load line =3.7mV 49 change PR551 10.5K to 16.2K 2012/5/21 DVT
8 fine tune the GFX load line =3.7mV 49 change PC522 560P to 330P 2012/5/21 DVT
9 fine tune the GFX OCP setting 49 change PR537 13.3K to 8.66K 2012/5/21 DVT
C C
10 purchaser command for cost down plane 48 change PU460 SY8037D to TPS51463 2012/5/22 DVT
11 for 1.05V high frequeence change to remote sense 47 add PR402 reserve PR401 2012/5/24 DVT
12 for 1.05V high frequeence 47 change PR412 100k to 12K 2012/5/24 DVT
change the same solution for 2nd sourcd 44

13 change PQ203 TPCA8057 to AON6504 2012/5/24 DVT
14 change the same solution for 2nd sourcd 44 change PR227 with the same PR211 2012/5/25 DVT
15 change the same solution for 2nd sourcd 46 change PC157 with the same PC996 2012/5/25 DVT
16 fine tune 1.05V vout volatge=1.059V 47 change PR410 12K to 11K 2012/5/25 DVT
17
fine tune the CPU DCR sense 49 change PR538 49.9K to 57.6K 2012/5/25 DVT
B B
18 fine tune the CPU DCR sense 49 change PR550 1.13K to 1.58K 2012/5/25 DVT
change PR357 120K to 133K

19 fine tune the 5V OCP=18A 45 2012/5/25 DVT
20 fine tune 3.3V OCP =10A 45 change PR337 120K to 200K 2012/5/25 DVT
21 for 1.05V high frequeence 47 change PL402 0.47u to 0.24u 2012/5/25 DVT
22 for 1.05V high frequeence 47 Reserve the PC415 and PC416 2012/5/25 DVT
23 change the 3v/5v IC version 45 change the PU330 RT8243B to RT8243A 2012/5/25 DVT
change 1.5V chokethe same part number with PL462 46 change the PL152 SH00000GJ00 to SH00000KS00 2012/5/25 DVT
24
25 change 1.05V high frequeence OCP=16.5A 47 change the PR407 75K to 64.9K 2012/5/25 DVT
A A
26 change charger current =3.46A 48 change the PR241 150 Kto 357K
27 change the PF2 for design change 43

change the PF2 8A to 10A

PIR (PWR)
Size Document Number
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VCUAA 1.0
5 4 3 2 1
A B C D E
HW PIR (Product Improve Record)

VCUAA LA-9161P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.3 TO 1.0
-----------------------------------------------------------------------------------------------------------------------------------
Item Page Date Request Solution
-----------------------------------------------------------------------------------------------------------------------------------
1) 24 2012/7/23A Change RTCBATT power rail from GCLK to original design DH1 mount always
2) 24 2012/7/23A remove BIOS socket UH3 mount always
1 1
3) 41 2012/7/23A remove debug SW Change SW2 to @
4) 38 2012/7/26A EMI request CA71,CA72,CA75,CA76 mount SE025102K80/1000pF
5) 41 2012/8/3A Update JBLG footprint Change JBLG footprint to E-T_7182K_F04N-00R_4P
6) 41 2012/8/3A Update H20 Change H20 from 3P8 to 3P3 size
7) 05 2012/8/6C remove JTAG for ESD request remove T5, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17
8) 42 2012/8/6D ESD request mount C20,C21,C28,C30,C32,C33,C36,C37,C38,C39,C40; add C44 on SUSP
9) 2012/8/6D Change footprint of 0ohm to Short_pad Change location: LL2, R1, R16, R17, R388, RA17, RA18, RA28, RB1,RB32, RB34, RC119, RC183, RC73, RC88,
RC92, RC94, RC95, RH128, RH208, RH213, RH214, RH221, RH242, RH244, RH246, RH247, RH249, RH25, RH286, RH311,
RH312, RH314, RL433, RV182, RV80, RV81
10) 41 2012/8/6D Change PCB PN Change to DAZ0T700100
11) 34 2012/8/6D EMI request Change CM18 from 47pF to 680pF
12) 42 2012/8/6D EMI request Add C1(680pF) on +GFX_CORE, place close to CPU
2 2
3 3
4 4

HW-PIR
A B C D E

63a4a Compal LA-9161P

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63a4a Compal LA-9161P

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A B C D E

LA-9161P REV 1.0 Schematic

Security Classification Compal Secret Data Compal Electronics, Inc.

1.5V DDRIII 1066/1333/1600 MT/s

Intel PCH USB20 2x CardReader RTS5137 Int. Camera

SATA Gen3 port 0 SATA HDD

SATA Gen3 port 1 SATA mSATA

3 LED+LID/B LPC BUS HD Audio 3

RTC CKT. SPI ROM

Touch Pad Int.KBD SPK Conn JPIO

Power On/Off CKT.

Security Classification Compal Secret Data Compal Electronics, Inc.

DESIGN CURRENT 0.1A +3VL

N-CHANNEL DESIGN CURRENT 4A +5VS

Ipeak=6A, Imax=4.A, Iocp min=8 DESIGN CURRENT 6A +VCCSA

Ipeak=5A, Imax=3.5A, Iocp min=6.2A DESIGN CURRENT 5A +3VALW

P-CHANNEL DESIGN CURRENT 330mA +3V_LAN

N-CHANNEL DESIGN CURRENT 4A +3VS

P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD

DESIGN CURRENT 2A +3V_WLAN

DESIGN CURRENT 94A +CPU_CORE

N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU

DESIGN CURRENT 2A +1.5VS

A DESIGN CURRENT 8.6A A

Ipeak=33.8A, Imax=23.4A, Iocp min=40A DESIGN CURRENT 20.5A +VGA_CORE

Security Classification Compal Secret Data Compal Electronics, Inc.

( O MEANS ON X MEANS OFF )

Full ON HIGH HIGH HIGH

S4 (Suspend to Disk) LOW LOW HIGH

G3 LOW LOW LOW

Security Classification Compal Secret Data Compal Electronics, Inc.

UC1B 100 MHz

T2 PAD H_CATERR# C49 @

H_PECI A48 AT30 H_DRAMRST#

RC45 2 1 10K_0402_5% H_PWRGOOD H_THERMTRIP# D45

L56 XDP_TCK T3 PAD @

JTAG & BPM

Buffered Rest to CPU XDP Connector FAN Control Circuit

IN 43_0402_1% 0.01U_0402_25V7K ACES_88266-05001

Security Classification Compal Secret Data Compal Electronics, Inc.

PEG_ICOMPI and RCOMPO signals should be

PCI EXPRESS -- GRAPHICS

G17 PCIE_CTX_GRX_P7 CC14 1 2 OPT@ 0.22U_0402_16V7K PCIE_CTX_C_GRX_P7

PEG DG suggest AC cap

SANDY Bridge Gen1/Gen2 180 nF~265 nF

NV N13X Gen1/2/3 Suggest 220 nF

Security Classification Compal Secret Data Compal Electronics, Inc.

DDR_A_D0 AG6 DDR_B_D0 AL4

DDR SYSTEM MEMORY B

IVY-BRIDGE_BGA1023 <BOM> IVY-BRIDGE_BGA1023 <BOM>

<5> H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2 SM_DRAMRST# <11,12>

<11,25> DRAMRST_CNTRL_PCH 1 @ 2 DRAMRST_CNTRL Request by ESD

+CPU_CORE UC1F POWER +1.05VS_VCCP

PEG IO AND DDR IO

N30 VCC[74] VCCPQE[1] AM25

C44 H_CPU_SVIDDAT RC88 1 @ 2 0_0402_5%

VCC_SENSE F43 VCCSENSE_R RC94 1 @ 2 0_0402_5% VCCSENSE <49>

VSS_SENSE G43 VSSSENSE_R 1 @ 2 VSSSENSE <49>

+1.05VS_VCCP Close to CPU

Close to CPU Ivy Bridge_POWER-1

+GFX_CORE UC1G POWER +V_SM_VREF should

29A have 20 mil trace width RC120 1K_0402_0.5%

+1.8VS 1 @ 2 +1.8VS_VCCPLL BB3