Académique Documents
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Contents :
1.ABSTRACT
2.INTRODUTION
3.MICROCONTROLLER
4.INTRODUCTION AND
DESCRIPTION OF DTMF
5.LCD INTERFACING
6.PROJECT CIRCUITARY
8.CONCLUTION
9.REFERENCES
1ABSTRACT
The objective of this project is to design an embedded system
Frequency).
Therefore, no two keys will have a same set of low & high
frequencies.
This system can selectively turn on or off multiple loads one at a time or switch
off all the loads simultaneously. It also provides you feedback when the circuit
is in energized state and also sends an acknowledgement indicating action with
respect to the switching on of each load and switching off of all loads
(together). This is a micro controller aided system where a ring detector, auto
lifter and DTMF decoder work together to place a call and a relay driver
connects the required load. This makes the task of the various operators easy as
they can sit anywhere and control the status of the various loads.
In the existing system if an operator in and industry has to control a certain
load there is no other method than being physically present at the site of the
load. If he has to switch off a system after a particular period he will have to
wait till the completion of the operation. But our project titled "Telephone
controlled switch" rectifies this disadvantage of conventional systems. This
system as its name suggests help the user to control the status of various loads
from any remote location through a telephone connection.
This project telephone controlled load activator has the following features.
APPLICATION
8051
MICROCONTROLLER
REGULATED
POWER
SUPPLY
CHAPTER II
INTRODUCTION TO EMBEDDED SYSTEM
AND MICROCONTROLLER
INTRODUCTION TO EMBEDDED SYSTEM
EMBEDDED SYSTEM
Communications applications
All the Port 3 pins are multifunctional. They are not only
port pins, but also serve the functions of various special
features as listed below:
Port Pin Alternate Function
P3.0 RxD (serial input port)
P3.1 TxD (serial output port)
MEMORY ORGANISATION
The alternate functions can only be activated if the
corresponding bit latch in the port SFR contains a 1. Otherwise
the port pin remains at 0.All 80C51 devices have separate
address spaces for program and data memory, as shown in
Figures 1 and 2. The logical separation of program and data
memory allows the data memory to be accessed by 8-bit
addresses, which can be quickly stored and manipulated by an
8-bit CPU. Nevertheless, 16-bit data memory addresses can
also be generated through the DPTR register.
The Data Pointer: The Data Pointer (DPTR) is the 8052ís only
user-accessible 16-bit (2-byte) register. The Accumulator, "R"
registers, and "B" register are all 1-byte values. The PC just
described is a 16-bit value but isn't directly user-accessible as
a working register.
The Stack Pointer: The Stack Pointer, like all registers except
DPTR and PC, may hold an 8-bit (1-byte) value. The Stack
Pointer is used to indicate where the next value to be removed
from the stack should be taken from.
When you push a value onto the stack, the 8052 first
increments the value of SP and then stores the value at the
resulting memory location. When you pop a value off the stack,
the 8052 returns the value from the memory location indicated
by SP and then decrements the value of SP.
ADDRESSING MODES
The addressing modes in the 80C51 instruction set are as
follows:
Immediate Constants
The value of a constant can follow the opcode in Program
Memory. For example,
MOV A, #100
loads the Accumulator with the decimal number 100. The same
number could be specified in hex digits as 64H.
Indexed Addressing
Only program Memory can be accessed with indexed
addressing, and it can only be read. This addressing mode is
intended for reading look-up tables in Program Memory A 16-
bit base register (either DPTR or the Program Counter) points
to the base of the table, and the Accumulator is set up with the
table entry number. The address of the table entry in Program
Memory is formed by adding the Accumulator data to the base
pointer. Another type of indexed addressing is used in the
“case jump” instruction. In this case the destination address of
a jump instruction is computed as the sum of the base pointer
and the Accumulator data.
TIMERS/COUNTERS
MICROPROCESSOR
A microprocessor as a term has come to be known is a
general-purpose digital computer central processing unit.
Although popularly known as a computer on a chip.
The microprocessor contains arithmetic and logic unit,
program counter, Stack pointer, some working registers, clock
timing circuit and interrupt circuits.
MICROCONTROLLER
FEATURES
• 80C51 Central Processing Unit.
• On-chip FLASH Program Memory
• Speed up to 33 MHz
• Fully static operation
• RAM expandable externally up to 64 Kbytes
• 4 interrupt priority levels
• 6 interrupt sources
• Four 8-bit I/O ports
• Full-duplex enhanced UART
Framing error detection
Automatic address recognition
• Three 16-bit timers/counters T0, T1 (standard 80C51) and
additional T2 (capture and compare)
• Power control modes
Clock can be stopped and resumed
Idle mode
Power down mode
• Programmable clock out
• Second DPTR register
• Asynchronous port reset
• Low EMI (inhibit ALE)
• Wake up from power down by an external interrupt
BLOCK DIAGRAM 1
BLOCK DIAGRAM 2
PIN CONFIGURATION
LOGIC SYMBOL
PIN DESCRIPTIONS
MNEM PIN TYP NAME AND FUNCTION
ONIC No. E
VSS 20 I Ground: 0 V reference.
VCC 40 I Power Supply: This is the power supply voltage
for normal, idle, and power-down operation.
P0.0– 39– I/O Port 0: Port 0 is an open-drain, bidirectional I/O
0.7 32 port. Port 0 pins that have 1s written to them
float and can be used as high-impedance
inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to
external program and data memory. In this
application, it uses strong internal pull-ups
when emitting 1s.
P1.0– 1–8 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port
P1.7 with internal pull-ups. Port 1 pins that have 1s
written to them are pulled high by the internal
pull-ups and can be used as inputs. As inputs,
port 1 pins that are externally pulled low will
source current because of the internal pull-
1 I/O ups. Alternate function for Port 1:
T2 (P1.0): Timer/Counter2 external count
0 I input/clockout (see Programmable Clock-
Out).
T2EX (P1.1): Timer/Counter2
reload/capture/direction control.
P2.0– 21– Port 2: Port 2 is an 8-bit bidirectional I/O port
P2.7 28 with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal
pull-ups and can be used as inputs. As inputs,
port 2 pins that are externally being pulled low
will source current because of the internal pull-
ups. (See DC Electrical Characteristics: IIL).
Port 2 emits the high-order address byte
during fetches from external program memory
and during accesses to external data memory
that uses 16-bit addresses (MOVX @DPTR). In
this application, it uses strong internal pull-ups
when emitting 1s. During accesses to external
data memory that uses 8-bit addresses (MOV
@Ri); port 2 emits the contents of the P2
special function register.
P3.0– 10– I/O Port 3: Port 3 is an 8-bit bidirectional I/O port
P3.7 17 with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal
pull-ups and can be used as inputs. As inputs,
port 3 pins that are externally being pulled low
will source current because of the pull-ups.
(See DC Electrical Characteristics: IIL). Port 3
I also serves the special features of the
10 O 89C51/89C52/89C54/89C58, as listed below:
11 I RxD (P3.0): Serial input port
12 I TxD (P3.1): Serial output port
13 I INT0 (P3.2): External interrupt
14 I INT1 (P3.3): External interrupt
15 O T0 (P3.4): Timer 0 external input
16 O T1 (P3.5): Timer 1 external input
17 WR (P3.6): External data memory write
strobe
RD (P3.7): External data memory read
strobe
RST 9 I Reset: A high on this pin for two machine
cycles while the oscillator is running, resets
the device. An internal diffused resistor to VSS
permits a power-on reset using only an
external capacitor to VCC.
ALE 30 O Address Latch Enable: Output pulse for
latching the low byte of the address during an
access to external memory. In normal
operation, ALE is emitted at a constant rate of
1/6 the oscillator frequency, and can be used
for external timing or clocking. Note that one
ALE pulse is skipped during each access to
external data memory. ALE can be disabled by
setting SFR auxiliary.0. With this bit set, ALE
will be active only during a MOVX instruction.
PSEN 29 O Program Store Enable: The read strobe to
external program memory. When executing
code from the external program memory,
PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped
during each access to external data memory.
PSEN is not activated during fetches from
internal program memory.
EA/VPP 31 I External Access Enable/Programming Supply
Voltage: EA must be externally held low to
enable the device to fetch code from external
program memory locations 0000H to the
maximum internal memory boundary. If EA is
held high, the device executes from internal
program memory unless the program counter
contains an address greater than 0FFFH for 4 k
devices, 1FFFH for 8 k devices, 3FFFH for 16 k
devices, and 7FFFH for 32 k devices.
The value on the EA pin is latched when RST is
released and any subsequent changes have no
effect. This pin also receives the 5V/12V
(±10%) programming supply voltage (VPP)
during FLASH programming.
XTAL1 19 I Crystal 1: Input to the inverting oscillator
amplifier and input to the internal clock
generator circuits.
XTAL2 18 O Crystal 2: Output from the inverting oscillator
amplifier.
Features
• FLASH EPROM internal program memory with Chip Erase.
• Up to 64 k byte external program memory if the internal
program memory is disabled (EA = 0).
• Programmable security bits.
• 10,000 minimum erase/program cycles for each byte.
• 10 year minimum data retention.
• Programming support available from many popular
vendors.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an
on-chip oscillator. To drive the device from an external clock
source, XTAL1 should be driven while XTAL2 is left
unconnected. There are no requirements on the duty cycle of
the external clock signal, because the input to the internal
clock circuitry is through a divide-by-two flip-flop. However,
minimum and maximum high and low times specified in the
data sheet must be observed.
RESET
A reset is accomplished by holding the RST pin high for at least
two machine cycles (24 oscillator periods), while the oscillator
is running. To insure a good power-on reset, the RST pin must
be high long enough to allow the oscillator time to start up
(normally a few milliseconds) plus two machine cycles. At
power-on, the voltage on VCC and RST must come up at the
same time for a proper start-up. Ports 1, 2, and 3 will
asynchronously be driven to their reset condition when a
voltage above VIH1 (min.) is applied to RST. The value on the
EA pin is latched when RST is deasserted and has no further
effect.
Idle Mode
In the idle mode (see Table 2), the CPU puts itself to sleep
while all of the on-chip peripherals stay active. The instruction
to invoke the idle mode is the last instruction executed in the
normal operating mode before the idle mode is activated. The
CPU contents, the on-chip RAM, and all of the special function
registers remain intact during this mode. The idle mode can be
terminated either by any enabled interrupt (at which time the
process is picked up at the interrupt service routine and
continued), or by a hardware reset which starts the processor
in the same manner as a power-on reset.
Power-Down Mode
To save even more power, a Power Down mode (see Table 2)
can be invoked by software. In this mode, the oscillator is
stopped and the instruction that invoked Power Down is the
last instruction executed. The on-chip RAM and Special
Function Registers retain their values down to 2.0 V and care
must be taken to return VCC to the minimum specified
operating voltages before the Power Down Mode is terminated.
Either a hardware reset or external interrupt can be used to
exit from Power Down. Reset redefines all the SFRs but does
not change the on-chip RAM. An external interrupt allows both
the SFRs and the on-chip RAM to retain their values. To
properly terminate Power Down the reset or external interrupt
should not be executed before VCC is restored to its normal
operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10ms).
With an external interrupt, INT0 and INT1 must be enabled and
configured as level-sensitive. Holding the pin low restarts the
oscillator but bringing the pin back high completes the exit.
Once the interrupt is serviced, the next instruction to be
executed after RETI will be the one following the instruction
that put the device into Power Down.
Design Consideration
When the idle mode is terminated by a hardware reset, the
device normally resumes program execution, from where it left
off, up to two machine cycles before the internal reset
algorithm takes control. On-chip hardware inhibits access to
internal RAM in this event, but access to the port pins is not
inhibited. To eliminate the possibility of an unexpected write
when Idle is terminated by reset, the instruction following the
one that invokes Idle should not be one that writes to a port
pin or to external memory.
ONCETM Mode
The ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems without the device having to be
removed from the circuit. The ONCE Mode is invoked by:
1. Pull ALE low while the device is in reset and PSEN is high;
2. Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a
float state, and the other port pins and ALE and PSEN are
weakly pulled high. The oscillator circuit remains active. While
the device is in this mode, an emulator or test CPU can be
used to drive the circuit.
Normal operation is restored when a normal reset is applied.
Programmable Clock-Out
A 50% duty cycle clock can be programmed to come out on
P1.0. This pin, besides being a regular I/O pin, has two
alternate functions. It can be programmed:
1. to input the external clock for Timer/Counter 2, or
2. to output a 50% duty cycle clock ranging from 61Hz to
4MHz at a 16MHz operating frequency.
To configure the Timer/Counter 2 as a clock generator, bit C/T2
(in T2CON) must be cleared and bit T20E in T2MOD must be
set. Bit TR2 (T2CON.2) also must be set to start the timer. The
Clock-Out frequency depends on the oscillator frequency and
the reload value of Timer 2 capture registers (RCAP2H,
RCAP2L) as shown in this equation:
Oscillator Frequency
UART The UART in the AT89S52 operates the same way as the
UART in the AT89C51 and AT89C52.
Enhanced UART operation
In addition to the standard operation modes, the UART can
perform framing error detect by looking for missing stop bits,
and automatic address recognition. The UART also fully
supports multiprocessor communication. When used for
framing error detect the UART looks for missing stop bits in the
communication. A missing bit will set the FE bit in the SCON
register. The FE bit shares the SCON.7 bit with SM0 and the
function of SCON.7 is determined by PCON.6 (SMOD0). If
SMOD0 is set then SCON.7 functions as FE. SCON.7 functions
as SM0 when SMOD0 is cleared. When used as FE SCON.7 can
only be cleared by software.
Idle Mode In idle mode, the CPU puts itself to sleep while all
the on-chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and the entire
special functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset. Note that when idle mode is
terminated by a hardware reset, the device normally resumes
program execution from where it left off, up to two machine
cycles before the internal reset algorithm takes control. On-
chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write to a port pin when idle mode
is terminated by a reset, the instruction following the one that
invokes idle mode should not write to a port pin or to external
memory.
INTRODUCTION TO DTMF
DESCRIPTION OF DTMF RECEIVER
INTRODUCTION
Keypad
The DTMF keypad is laid out in a 4×4 matrix, with each row
representing a low frequency, and each column representing a
high frequency. Pressing a single key (such as ‘1’) will send a
sinusoidal tone of the two frequencies (697 and 1209 hertz
(Hz)). The original keypads had levers inside, so each button
activated two contacts. The multiple tones are the reason for
calling the system multi-frequency. These tones are then
decoded by the switching center to determine which key was
pressed.
Low High
Event
frequency frequency
Busy signal 480 Hz 620 Hz
Dial tone 350 Hz 440 Hz
Ringback
440 Hz 480 Hz
tone
Features
• Operating voltage: 2.5V~5.5V
• Minimal external components
• No external filter is required
• Low standby current (on power down mode)
• Excellent performance
• Tristate data output for MCU interface
• 3.58MHz crystal or ceramic resonator
• 1633Hz can be inhibited by the INH pin
DESCRIPTION
The HT9170B/D are Dual Tone Multi Frequency (DTMF)
receivers integrated with digital decoder and band split filter
functions as well as power-down mode and inhibit mode
operations. Such devices use digital counting techniques to
detect and decode all the 16 DTMF tone pairs into a 4-bit code
output. Highly accurate switched capacitor filters are
implemented to divide tone signals into low and high group
signals. A built-in dial tone rejection circuit is provided to
eliminate the need for pre-filtering.
tACC=tDP+tGTP
tIR=tDA+tGTA
where tACC: Tone duration acceptable time
tDP: EST output delay time (“L” → “H”)
tGTP: Tone present time
tIR: Inter-digit pause rejection time
tDA: EST output delay time (“H” → “L”)
tGTA: Tone absent time
CHAPTER V
LCD INTERFACING
Introduction
The most commonly used Character based LCDs are based on
Hitachi's HD44780 controller or other which are compatible
with HD44580. In this tutorial, we will discuss about character
based LCDs, their interfacing with various microcontrollers,
various interfaces (8-bit/4-bit), programming, special stuff and
tricks you can do with these simple looking LCDs which can
give a new look to your application.
Pin Description
The most commonly used LCD’s found in the market today are
1 Line, 2 Line or 4 Line LCDs which have only 1 controller and
support at most of 80 characters, whereas LCDs supporting
more than 80 characters make use of 2 HD44780 controllers.
As you can see in both the code maps, the character code from
0x00 to 0x07 is occupied by the CGRAM characters or the user
defined characters. If user wants to display the fourth custom
character then the code to display it is 0x03 i.e. when user
sends 0x03 code to the LCD DDRAM then the fourth user
created character or pattern will be displayed on the LCD.
CGRAM - Character Generator RAM
As clear from the name, CGRAM area is used to create custom
characters in LCD. In the character generator RAM, the user
can rewrite character patterns by program. For 5 x 8 dots,
eight character patterns can be written, and for 5 x 10 dots,
four character patterns can be written.
BF - Busy Flag
Busy Flag is a status indicator flag for LCD. When we send a
command or data to the LCD for processing, this flag is set (i.e.
BF =1) and as soon as the instruction is executed successfully
this flag is cleared (BF = 0). This is helpful in producing and
exact amount of delay for the LCD processing.
The busy flag will only be valid after the above reset sequence.
Usually we do not use busy flag in 4-bit mode as we have to
write code for reading two nibbles from the LCD. Instead we
simply put a certain amount of delay usually 300 to 600uS.
This delay might vary depending on the LCD you are using, as
you might have a different crystal frequency on which LCD
controller is running. So it actually depends on the LCD module
you are using.
CIRCUIT FEATURES
BLOCK DIAGRAM
EXAMPLE CIRCUIT DIAGRAM:
CHAPTER 6
PROJECT CIRCUITRY
The schematic is divided into four sections microcontroller
section, DTMF receiver module, controlling section and power
supply section
FEATURES
SDCC also comes with the source level debugger SDCDB, using
the current version of Daniel's s51 simulator.
SUPPORT OF SDCC
SDCC Basics
#include <stdio.h>
Flash Magic can erase devices, program them, read data and
read and set various configuration information. Rather than
providing the basic features of ISP, Flash Magic adds additional
features and intelligence, allowing complex operations to be
performed. For example, erasing can be any collection of
pages, blocks, the hex file to be programmed or the entire
device. Some devices store the ISP boot loader in flash
memory, so Flash magic implements methods to protect this
code from being erased.
Flash Magic has been available for free for over six years and
supports all current 8-bit (8051), 16-bit (XA) and 32-bit (ARM)
flash microcontrollers from NXP.
Possible Uses
Features
Source code
Conclusion