TEST PAPER Computer Organization

1. The output of the following circuit is

(a) S=A+B (b) S=A-B (c) S=A+B+1 (d)S=A-B-1

2. Consider IEEE 754 representation of floating point numbers. The largest normalized
32-bits number that can be represented is

(1  223 )  2127 (b) (1  224 )  2127

(c) (2  2 23 )  2127 (d) (2  2 24 )  2127

3. A three level memory system has a cache, a main memory. The hit ratio of SRAM
cache is 97% and hit ratio of DRAM is main memory is 98%. It takes 2 cycles to
access SRAM, 50 cycles to fetch from DRAM and 100000 cycles to access the virtual
memory. The average memory access time is
(a) 63.5 cycles (b) 3.25 cycles (c) 16 cycles (d) 32 cycles
4. Consider a 16 bit processor with variable length instructions. The opcode field is 16
bit and memory address is 16 bits. The following program is to be executed

ADD R1, A,B ; R1  M[A] + M[B]

ADD R2, C,D; R2  M[C]+M[D]

MUL D, R1, R2; M[X]  R1 + R2

Total number of memory access to execute the program is

(a) 06 (b) 11 (c) 12 (d) 13

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5. A 16 bit CPU adds two signal integers A1F2 and 3A1F. The PSW of the CPU
consists of ov = overflow, C=carry, P =Even parity, Z = zero and S= Sign bits. The
status of these flags, (ov, s, p, z,s) after the addition will be
(a) 11011 (b) 10011 (c) 00011 (d) 00100
6. The expression for difference of a fill subs tractor with input a, b, c is given by

(a) abc (b) a b c

(c) (a  b).c (d) (a b).c

7. A 32 bit CPU has the following instruction mix

Operation Frequency Cycles
ALU 40% 1
Load 20% 5
Store 20% 5
Branch 20% 2

The CPI of load and store instruction is improved to 3 and it result in ALU instruction
CPI increasing to 2. This result in performance by a factor of
(a) 1 (b) 1.16 (b) 1.6 (d) 2

8. A computer system uses expanding opcode. It has 16 bit instructions and 6 bit
addresses. It supports one address and two address instructions. There are 15 two
address instructions. Then the maximum number of one address instructions possible
are
(a) 128 (b) 64 (c) 256 (d) 512
9. An instruction takes m bits and it supports p zero address instructions, q one address
instructions and r two address instructions. Address takes n bits. Then which of the
following is true

(a) p+q+r = m (b) np + 2nq + 4nr = 2m

(c)p+q*r+2n = m (d) p+q*2n +r*22n = 2m

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10. Consider the following block that converts the input signed data(4 bit) to equivalent
negative (twos complement form) the expression for M0 is

(a) m0  A0 (b) m0  A0

(c) m0  A3  A2  A1  A0 (d) m0  A2  A1  A0

11. A computer system uses Booths algorithm for multiplication. Which of the
following data sets give worst performance.
(a)1AF1 and 2882 (b) FF02 and3FF1
(c) AA55 (d) 2F22 and 301A

12. A mode 12 adder uses binary adder and adds 04 to the result by generating a
signal x=1 when the result after addition of A and B is greater than 12.
The expression for x can be written as

(a) X = D3  D2  D1 (b) D3  D2  D1  D0

(c) X= D3 D2 (d) X  A3 B3

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13. The magnitude of minimum renormalized number in IEEE 754 format will have a
value

(a) 2127 (b) 222 (c) 2148 (d) 2149

14. Consider a 3 bit adder that adds bits a2 a1a0 with b2b1b0 the carry out from most
significant position can be denoted as
(a) a2 b2  b2b1a1  a0b0 b1b2  a0 a1b0b2  b0 a2a1a0  b1b0 a2 a0  b1a2 a1
(b) a2b2  b1a1  b0 a0
(c) a2 b2 b1  a1b2b1  b2 a2b1  b2 a1b1  b2 a1a0  b2 a1b0  b
(d) None of these

15. Four 4 bit carry look ahead adder blocks are cascaded to get a 16 bit parallel
adder. If the gate level delay is td then the final result is available after time equal
to
(a) 10td (b) 12td (c) 13td (d) 16td
16. The number of multiplexers required to construct a 4 bit adder is
(a) 4 (b) 7 (c) 8 (d) 16
17. Overflow flag is set after an addition operation it means
(a) Range of result exceeded the allotted range if the operands are unsigned
numbers
(b)Range of result exceeded the allotted range if the operands are signed
numbers.
(c) Range of result exceeded whether the operands are signed or unsigned
numbers
(d)Cannot say anything about range of result without knowing the contents of
carry flag also

18. Which of the following addressing mode result in smallest size instructions
(a) Direct Addressing mode (b) Indirect addressing mode

(c) Implied addressing (d) Auto index addressing

19. Which of the following is not the characteristics of CISC processor
(a) Large number of instructions
(b) Less number of addressing mode
(c) Large number of memory based instruction
(d) Slow speed

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20. Which of the following addressing modes result in large instruction execution time
(a) Direct addressing (b) Indirect addressing
(c) Register indirect addressing (d) Auto decrement addressing
21. Consider the following control unit architectures. Which of them is slowest
(a) Hard wired control unit
(b) Vertical format micro control
(c) Horizontal format micro control
(d) Nano programmed micro control

22. CPU suspends the execution of instruction after the current machine cycle when
(a) General interrupt occurs
(b) None maskable interrupt occurs
(c) DMA occurs
(d) All the above

23. A CPU uses 8 bit signal relative address for short jumps. The current PC contents is
1000h. If the jump instruction in the memory pointed by PC is JMP 82h. Then the
branch address will be
(a) 1082h (b) 0F82 (c) F082 (d) 2082

24. A computer can read or write 8 bit, 16 bit or 32 bit in a memory cycle. The system
need 32 MB memory. It is implemented using a number of memory chips. The
number of address lines connected commonly to all memory chips are
(a) 25 (b) 24 (c) 23 (d) 20
25. The number of 8M x 2 chips required to implement 32MB storage is
(a) 24 (b) 32 (c) 16 (d) 20

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