TECHNOLOGICAL UNIVERSITY OF THE PHILIPPINES

Lopez Extension Campus

College of Industrial Technology
Brgy. Villa Hermosa, Lopez, Quezon

HARDWARE DESCRIPTIVE LANGUAGE

HOMEWORK NO.1

INFELIZ, KIMBERLY ANN D.

BACHELOR OF ENGINEERING TECHNOLOGY

Major in Computer Engineering Technology

September 3, 2019
What is Hardware Descriptive Language and it's History? 5pts.

Hadware Descriptive Language (HDL) is a specific scripting language used to depict the structure and conduct of
electronic circuits, and most ordinarily, advanced rationale circuits.l
Hardware Descriptive Language empowers an exact, formal depiction of an electronic circuit that takes into account the
robotized examination and reproduction of an electronic circuit. It additionally takes into consideration the blend of a
HDL portrayal into a netlist (a determination of physical electronic parts and how they are associated together), which
would then be able to be put and steered to deliver the arrangement of covers used to make an incorporated circuit.
Hardware Descriptive Language looks much like a programming language, for example, C; it is a literary depiction
comprising of articulations, proclamations and control structures. One significant contrast between most programming
dialects and HDLs is that HDLs expressly incorporate the idea of time. HDLs structure an essential piece of electronic plan
robotization (EDA) frameworks, particularly for complex circuits, for example, application-explicit incorporated circuits,
microchips, and programmable rationale gadgets.

Brief History

Verilog HDL was invented by Phil Moorby and Prabhu Goel around 1984. It filled in as an exclusive equipment
demonstrating language owned by Gateway Design Automation Inc. At that time, the language was not standarized. It
modified itself in almost all the revisions that turned out between 1984 to 1990.

In 1990, Gateway Design Automation Inc was acquired by Cadence Design System, which is now the biggest provider of
electronic design technologies and engineering services in the electronic design automazation (EDA) industry. Cadence
recognized the value of Verilog, and realized that if Verilog reamined as a closed language, the pressure of
standarization the people would eventually drive to VHDL. So in 1991 the Open Verilog International (OVI) (presently
known as Accellera) was organized by Candence and the documentation of Verilog was moved to public domain under
the name of OVI. It was later submitted to IEEE and later become IEEE standard 1364-1995, usually called as Verilog-95.

In 2001, extensions to Verilog-95 were submitted back to IEEE and became IEEE standard 1364-2001, known as Verilog-
2001. The extensions covered some deficiencies that users had found in the Verilog-95. One of the most significant
upgrades was that signed variables (in 2.s complement) became supported. Verilog-2001 is now the dominant edition of
Verilog supported by most design tools.

In 2005, Verilog-2005 (IEEE Standard 1364-2005) was published with minor corrections and modifications. Also in 2005
System Verilog, a superset of Verilog-2005, with many new features and capabilities to aid design verification, was
published. As of 2009, SystemVerilog and Verilog language standards were merged into SystemVerilog 2009 (IEEE
Standard 1800-2009), which is one of the most popular languages for IC design and verification today. Xilinx® Vivado
Design Suite, released in 2013, can support SystemVerilog for FPGA design and verification.

Convert the following decimal numbers to binary. Create a table.

Decimal Binary
 66 1000010
49 110001
513 1000000001
864 1101100000
1897 11101101001
2004 11111010100

Convert the following unsigned binary numbers to decimal, hexadecimal, and octal:

Binary Decimal Hexadecimal Octal

100100011 291 123 443
1011011 91 5B 133
1101101110 878 36E 1556
101111010100 3028 BD4 5724