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SW_AXS = RW;
// 0 : 5 BITS\
// 1 : 6 BITS\
// 2 : 7 BITS\
// 3 : 8 BITS”;
SW_AXS = RW;
CLEARING_MODE = DC;
ENUM
FIVE_BIT = 0;
SIX_BIT = 1;
SEVEN_BIT = 2;
EIGHT_BIT = 3;
SW_AXS = RW;
CLEARING_MODE = DC;
ENUM {
SHORT_STOP_BIT = 0;
LONG_STOP_BIT = 1;
SW_AXS = RW;
CLEARING_MODE = DC;
SW_AXS = RW;
CLEARING_MODE = DC;
ENUM {
EVEN_PARITY = 1;
ODD_PARITY = 0;
FIELD SP <5:5> {
SW_AXS = RW;
CLEARING_MODE = DC;
ENUM {
DISABLE_STICKY_PAR = 0;
ENABLE_STICKY_PAR = 1;
FIELD SB <6:6> {
SW_AXS = RW;
CLEARING_MODE = DC;
SW_AXS = RW;
CLEARING_MODE = DC;
CONTROL_REGISTERS
SW_AXS = WO;
SW_AXS = WO;
CLEARING_MODE = DC;
SW_AXS = WO;
CLEARING_MODE = DC;
SW_AXS = WO;
CLEARING_MODE = DC;
RESERVED<3:5> = 0;
SW_AXS = WO;
CLEARING_MODE = DC;
DATA_REGISTERS
SW_AXS = RO;
SW_AXS = RO;
CLEARING_MODE = DC;
VALUE_ON_RESET=0;
DATA_REGISTERS
SW_AXS = WO;
SW_AXS = WO;
CLEARING_MODE = DC;
VALUE_ON_RESET=0;
GENERAL_PURPOSE_REGISTERS
SW_AXS = RW;
//DESCRIPTION = "DEVICE LATCH LEAST SIGNIFICANT BYTE";
SW_AXS = RW;
CLEARING_MODE= DC;
VALUE_ON_RESET= 0X01;
SW_AXS=RW;
SW_AXS = RW;
CLEARING_MODE = DC;
VALUE_ON_RESET = 0X00;
STATUS_REGISTERS
SW_AXS = RO;
FIELD DR <0:0>
{
SW_AXS = RO;
VALUE_ON_RESET = 0X60;
FIELD OE <1:1>
SW_AXS = RO;
VALUE_ON_RESET = 0X60;
FIELD PE <2:2>
SW_AXS = RO;
VALUE_ON_RESET = 0X60;
ENUM
ENABLED = 0X1;
DISABLED = 0X0;
}
}
FIELD FE <3:3>
SW_AXS = RO;
VALUE_ON_RESET = 0X60;
FIELD BI <4:4>
SW_AXS = RO;
VALUE_ON_RESET = 0X60;
SW_AXS = RO;
VALUE_ON_RESET = 0X60;
}
FIELD TEMT <6:6>
SW_AXS = RO;
CLEARING_MODE = DC;
VALUE_ON_RESET = 0X60;
SW_AXS = RO;
VALUE_ON_RESET = 0X60;