Vous êtes sur la page 1sur 9

CONTROL_REGISTERS

LCR [8] @ 0X8 {

// DESCRIPTION = “LINE CONTROL REGISTER”;

SW_AXS = RW;

FIELD WLS <0:1> {

// DESCRIPTION = “WORD LENGTH SELECT\

// 0 : 5 BITS\

// 1 : 6 BITS\

// 2 : 7 BITS\

// 3 : 8 BITS”;

SW_AXS = RW;

CLEARING_MODE = DC;

ENUM

FIVE_BIT = 0;

SIX_BIT = 1;

SEVEN_BIT = 2;

EIGHT_BIT = 3;

FIELD STB <2:2> {

//DESCRIPTION = “NUMBER OF STOP BITS”;

SW_AXS = RW;

CLEARING_MODE = DC;

ENUM {

SHORT_STOP_BIT = 0;
LONG_STOP_BIT = 1;

FIELD PEN <3:3> {

//DESCRIPTION = “PARITY ENABLE”;

SW_AXS = RW;

CLEARING_MODE = DC;

FIELD EPS <4:4> {

//DESCRIPTION = “EVEN PARITY SELECT”;

SW_AXS = RW;

CLEARING_MODE = DC;

ENUM {

EVEN_PARITY = 1;

ODD_PARITY = 0;

FIELD SP <5:5> {

//DESCRIPTION = “STICK PARITY”;

SW_AXS = RW;

CLEARING_MODE = DC;

ENUM {

DISABLE_STICKY_PAR = 0;

ENABLE_STICKY_PAR = 1;

FIELD SB <6:6> {

//DESCRIPTION = “SET BREAK”;

SW_AXS = RW;
CLEARING_MODE = DC;

FIELD DLAB <7: 7> {

//DESCRIPTION = “DIVISOR LATCH ACCESS BIT”;

SW_AXS = RW;

CLEARING_MODE = DC;

CONTROL_REGISTERS

FCR [8] @ 0X8 {

//DESCRIPTION = “FIFO CONTROL REGISTER”;

SW_AXS = WO;

FIELD FIFO_ENABLE <0:0> {

//DESCRIPTION =“FIFO ENABLE”;

SW_AXS = WO;

CLEARING_MODE = DC;

FIELD RX_FIFO_RST <1:1> {

//DESCRIPTION = “RECIEVER FIFO RESET”;

SW_AXS = WO;

CLEARING_MODE = DC;

FIELD TX_FIFO_RST <2:2> {


//DESCRIPTION = “TRANSMITTER FIFO RESET”;

SW_AXS = WO;

CLEARING_MODE = DC;

RESERVED<3:5> = 0;

FIELD RX_TRIGGER <6:7> {

//DESCRIPTION = “RECEIVER TRIGGER BIT ”;

SW_AXS = WO;

CLEARING_MODE = DC;

DATA_REGISTERS

RBR [8] @ 0X0{

//DESCRIPTION = “RECEIVER BUFFER REGISTER”;

SW_AXS = RO;

FIELD RBR <0:7>{

//DESCRIPTION = “THIS REGISTER HOLDS RECEIVED DATA”;

SW_AXS = RO;
CLEARING_MODE = DC;

VALUE_ON_RESET=0;

DATA_REGISTERS

THR [8] @ 0X0{

//DESCRIPTION = “TRANSMIT HOLDING REGISTER”;

SW_AXS = WO;

FIELD THR <0:7>{

//DESCRIPTION = “ THIS REGISTER HOLDS THE DATA TO BE TRANSMITED”;

SW_AXS = WO;

CLEARING_MODE = DC;

VALUE_ON_RESET=0;

GENERAL_PURPOSE_REGISTERS

DLL [8] @ 0X0

SW_AXS = RW;
//DESCRIPTION = "DEVICE LATCH LEAST SIGNIFICANT BYTE";

FIELD DLL <0:7> {

SW_AXS = RW;

CLEARING_MODE= DC;

VALUE_ON_RESET= 0X01;

DLM [8] @ 0X4 {

SW_AXS=RW;

//DESCRIPTION = "DEVICE LATCH MOST SIGNIFICANT BYTE";

FIELD DLM <0:7> {

SW_AXS = RW;

CLEARING_MODE = DC;

VALUE_ON_RESET = 0X00;

STATUS_REGISTERS

LSR [8] @ 0X4{

SW_AXS = RO;

//DESCRIPTION = " LINE STATUS REGISTERS";

FIELD DR <0:0>
{

SW_AXS = RO;

//DESCRIPTION = "DATE READY INDICATOR";

CLEARING_MODE = COR RBR;

VALUE_ON_RESET = 0X60;

FIELD OE <1:1>

SW_AXS = RO;

DESCRIPTION = "OVER RUN ERROR RECEIVED";

CLEARING_MODE = COR LSR;

VALUE_ON_RESET = 0X60;

FIELD PE <2:2>

SW_AXS = RO;

//DESCRIPTION = "PARITY ERROR RECEIVED";

CLEARING_MODE = COR LSR;

VALUE_ON_RESET = 0X60;

ENUM

ENABLED = 0X1;

DISABLED = 0X0;

}
}

FIELD FE <3:3>

SW_AXS = RO;

//DESCRIPTION = "FRAMING ERROR RECEIVED";

CLEARING_MODE = COR LSR;

VALUE_ON_RESET = 0X60;

FIELD BI <4:4>

SW_AXS = RO;

//DESCRIPTION = "BREAK INTERRUPT RECEIVED";

CLEARING_MODE = COR LSR;

VALUE_ON_RESET = 0X60;

FIELD THRE <5:5>

SW_AXS = RO;

//DESCRIPTION = "TRANSMITTER HOLDING REGISTER EMPTY";


CLEARING_MODE = DC;

VALUE_ON_RESET = 0X60;

}
FIELD TEMT <6:6>

SW_AXS = RO;

//DESCRIPTION = "TRANSMITTER HOLDING AND SHIFT REGISTER EMPTY";

CLEARING_MODE = DC;

VALUE_ON_RESET = 0X60;

FIELD ERXFIFO <7:7>

SW_AXS = RO;

// DESCRIPTION = "ERROR IN RECEIVER FIFO";

CLEARING_MODE = COR LSR;

VALUE_ON_RESET = 0X60;

Vous aimerez peut-être aussi