NEC – V850 Risc

Microcontroller
CS433
Processor Presentation Series
Prof. Luddy Harrison

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 1

Note on this presentation series

z These slide presentations were prepared by

students of CS433 at the University of Illinois at
Urbana-Champaign
z All the drawings and figures in these slides were
drawn by the students. Some drawings are based
on figures in the manufacturer’s documentation for
the processor, but none are electronic copies of
such drawings
z You are free to use these slides provided that you
leave the credits and copyright notices intact

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 2

Table of Content
z Product Overview
z Specifications
z Core Architecture
z Memory MAP
z Memory Organization
z Pipeline
z Register Set
z Instruction Set
z Applications
z Packaging
z PinOut Description
z Development Environment
CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 3
Product Overview

z Range of
Performance Products
Data
Processing
V850E2
(under dev.)

z 20-100 MHz and beyond compatible with

popular machine
>= 100MHZ

Competitors class
32 bit
V850E1
3-4 times the performance of the
microprocessors 50MHZ
z
same frequency when compared to
16-bit Microprocessors compatible with high
end machine class V850 33MHZ
Competitors
z Up to 168K high-speed instruction 16 bit
microprocessors
RAM, as well as 8 KB instruction
cache memory and 8 KB of data V850ES
V850
20MHZ

cache memory.

z Built-in peripheral devices such as

USB, Timer, Serial I/F, A/D
Converter

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 4

Applications

z Range of Applications:
z Digital consumer applications
z Inverters
z Industrial equipment
z Printers
z fax machines
z Etc… V850E/Mxx
Car
High End Lineup
More powerful, high performance memory
interface
QA

V850E/xxx
V850E1 Core
V850ES/xxx Industry

V850ES Core Specialized internal hardware

V850/xxx
ASSP Lineup Communic
V850 Core ation

Lowe power, low noise internal memory Informatio

V850ES/xxx
extensions n
application
V850/xxx
Low end lineup Quality of
life

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 5

Product Overview

z V850 Product Varieties

V850ES/FE2 V850ES/FF2 V850ES/FG2 V850ES/FJ2

V850ES/SG2 V850ES/SJ2
CAN
V850E/RS1 V850E/CA2

V850E/CG2

CAN &
V850ES/DG2 V850ES/DJ2
Motor
Control V850E/IA1

Motor V850ES/lk1 V850ES/IA3 V850E/IA2 V850E/MA3

Control
V850E/IA4

General V850ES/KE1 V850ES/KF1 V850ES/KG1 V850ES/KJ1

Purpose V850ES/KE1+ V850ES/KF1+ V850ES/KG1+ V850ES/KJ1+ V850E/ME2

V850E/MA2 V850E/MA1 V850E2/ME3

Low Power
V850/SA1

V850ES/SA2

64 80 100 144 176 pins

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 6

Product Overview
Operating Conditions Peripherals
z Example: V850/ME2 Voltage
Dhrys tone Mips
3-3.6V
129
I/O Ports
LCD
77
No
Max. clock (MHz) 150 FIP No
Min. Ins tr. Tim e (ns ) 6.6 ADC 8X10bit
Sub. Clock No DMA Channels 4
z High Speed Tm in[c] -40 CAN NO
Tm ax[c] 85 UART 2
z Single Power Supply CSI 2
z Memory interface I2C No
Memory Tim er 6
z Instruction RAM 128KB, ROM[KBytes ] No Watchdog No

z Data RAM 16KB, Type Rom les s PWM 2X16bit

RAM[KBytes ] 144
z Instruction Cache 8KB EEPROM[Bytes ] No
Ins tr. Cache [KBytes ] 8
z USB1.1 Data Cache [KBytes ] No

Core Package
CPU V850E1 Package Code GM-UEU
Instructions 83 Type LQFP
Internal Bus [bits] 32 Pins 176
External Bus [bits] 16-A ug Pin Pitch[m m ] 0.5
Size 24x24

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 7

 Specifications
z Performance & Features z Peripherals
z Real-time performance of 130 MIPS z Memory access controller DRAM controller (compatible with
z Number of instructions: 83 SDRAM)
z Operation at over 150 MHz z DMA controller: 4 channels
z Minimum instruction execution time: 10 ns/7.5 ns/6.7 ns (at internal z I/O ports: 77
100 MHz/133 MHz/150 MHz operation) z Real-time pulse unit: 16-bit timer/event counter: 6 channels (no
z General-purpose registers: 32 bits × 32 capture operation for 2 channels)
z Instruction set: V850E1 CPU z 16-bit timers: 6
z 128-bit instruction fetch bus z 16-bit capture/compare registers: 12
z Signed multiplication (16 bits × 16 bits → 32 bits or 32 bits × 32 bits z 16-bit interval timer: 4 channels
→64 bits): 1 to 2 clocks z 16-bit up/down counter/timer for 2-phase encoder input: 2 channels
z 32-bit shift instructions: 1 clock z 16-bit capture/compare registers: 4
z Bit manipulation instructions z 16-bit compare registers: 4
z Programmable wait function z Serial interfaces (SIO): Asynchronous serial interface B (UARTB)
z Interrupts/exceptions: External interrupts: 40 (including NMI) z Clocked serial interface 3 (CSI3)
z Eight levels of priorities can be set. z CSI3/UARTB: 1 channel
z Internal interrupts: 59 sources z UARTB: 1 channel
z Exceptions: 2 sources z CSI3: 1 channel
z Endian control function z USB function controller (USBF): 1 channel
z A/D converter: 10-bit resolution A/D converter: 8 channels
z PWM (Pulse Width Modulation): 16-bit resolution PWM: 2 channels
z Memory z Clock generator: ×8 function using SSCG
z Memory space: 256 MB linear address space (common z Power-save function: HALT/IDLE/software STOP mode
program/data use)
z External bus interface: 32-bit data bus (address/data separated)
z 32-/16-/8-bit bus sizing function z Packaging
z Internal memory Instruction RAM: 128 KB z Package: 176-pin plastic LQFP (fine pitch) (24 × 24)
z Instruction cache 8 KB 2-way set associative z 240-pin plastic FBGA (16 × 16)
z Data RAM: 16 KB z CMOS technology: All static circuit
z Operating voltage: IVDD = 1.4-1.65 V
(core), EVDD = 3.0-3.6 V (I/O)

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 8

Core Architecture
z Harvard Architecture
z Two independent internal buses – for the simultaneous transfer of instructions and data

CPU
Instruction
PC ASTB
R Prefetch
Queue
O (2 words)
OSTB
M 32 bit R/W
Barrel
Shifter Multiplier UBEN
16X16 -> 32
32X32 -> 64 LBEN
System
Registers
WAIT
Bus control
General Unit Add. Bus
R
ALU
Registers MUX ACK
A (32bitsx32)
data bus
M
HLDRQ
HLDAK

Internal Peripheral
Bus

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 9

Microprocessor Architecture
z Block Diagram

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 10

 On Chip Units
z (1) CPU
The CPU uses five-stage pipeline control to enable
single-clock execution of address calculations,
arithmetic logic operations, data transfers, and almost
all other instruction processing.
z (2) Bus control unit (BCU)
The BCU starts the required external bus cycle based
on the physical address obtained by the CPU.
The BCU controls a DRAM controller (DRAMC), page
ROM controller (ROMC), and DMA controller (DMAC)
and performs external memory access and DMA
transfer.
¾ (a) SDRAM controller
The SDRAM controller generates the SDRAS,
SDCAS, UUDQM, ULDQM, LUDQM, and LLDQM
signals
and performs access control for SDRAM.
¾ (b) Page ROM controller (ROMC)
This controller supports accessing ROM that includes
the page access function.
¾ (c) DMA controller (DMAC)
This controller controls data transfer between memory
and I/O instead of the CPU.
There are three bus modes: single transfer, single
step transfer, and block transfer.
z (3) RAM
Instruction RAM (128 KB) and data RAM (16 KB) are
provided.
The instruction RAM can be accessed in one clock
from the CPU when an instruction is fetched.
z (4) Cache
A 2-way set associative instruction cache (8 KB) is
provided.
CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois
z (5) Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI,
INTPn) from on-chip peripheral I/O and external hardware.
Eight levels of interrupt priorities can be specified for these
interrupt requests.
z (6) Clock generator (CG)
This clock generator supplies frequencies which are 8 times
the input clock (FX) (using an on-chip PLL) as the internal
system clock (fCLK).
z (7) Real-time pulse unit (RPU)
This unit incorporates a 6-channel 16-bit timer/event counter,
4-channel 16-bit interval timer, and 2-channel
16-bit up/down counter/timer for 2-phase encoder input and
can measure pulse widths or frequency and
output a programmable pulse.
z (8) Serial interfaces (SIO)
The serial interfaces consist of 3 channels divided between an
asynchronous serial interface B (UARTB) and clocked serial
interface 3 (CSI3). Of these 3 channels, one is alternative with
UARTB and CSI3, one is fixed to CSI3, and one is fixed to
UARTB.
In addition, a USB function controller (USBF) is also provided.
z (9) A/D converter (ADC)
This high-speed, high-resolution 10-bit A/D converter includes
8 analog input pins. Conversion is performed
using the successive approximation method.
z (10) PWM
Two channels for PWM signal output of 16-bit resolution have
been provided.
11
Memory MAP FFFFFFFFH
Pheripheral I/O

FFFFEFFFH

Internal RAM
z Linear address up to 4 GB
total

z Up to 16MB for instructions

4 GB Linear
Internal ROM/PROM/
Flash Memory
00000000H

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 12

Memory Organization
z Internal Memory:
¾ Instruction and Data RAM
Instruction RAM (128 KB) and data RAM (16 KB) are provided.
The instruction RAM can be accessed in one clock from the CPU when an instruction is fetched.
¾ Instruction Cache
A 2-way set associative instruction cache (8 KB) is provided.

z External Memory:
The BCU controls a DRAM controller (DRAMC), page ROM controller (ROMC), and DMA controller
(DMAC) and performs external memory access and DMA transfer.
¾ SDRAM controller
¾ SRAM Controller
¾ Page ROM controller (ROMC)
This controller supports accessing ROM that includes the page access function (i.e. Flash)
¾ DMA controller (DMAC)
This controller controls data transfer between memory and I/O instead of the CPU. There are three
bus modes: single transfer, single step transfer, and block transfer.

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 13

Pipeline
IF : Instruction fetch

z 5-stage pipeline ID : Instruction decode

z Uses Forwarding EX : Instruction execution

MEM: Memory Access

WB : Writing execution result to register

Time Flow
(State)
System Clock

Instr. 1 IF ID EX MEM WB
Instr. 2 IF ID EX MEM WB
Instr. 3 IF ID EX MEM WB
Instr. 4 IF ID EX MEM WB
Instr. 5 IF ID EX MEM WB
Instr. 6 IF ID EX MEM WB
Instr. 7 IF ID EX MEM WB
Instr. 8 IF ID EX MEM WB

Executing instruction every 1 cycle

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 14

Data Types & Representation
z Data Types:
¾ Byte (8bit)
¾ Half-Word (16bit)
¾ Word (32 bit)
¾ Bit (1 bit)

z Data Representation:
¾ Integer
¾ Unsigned Integer
¾ Bit

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 15

Address Space
z Up to 4-GB linear address space

z Memory and I/O are mapped to this address space

z The maximum address is 232-1

z Byte ordering is little endian

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 16

Addressing Modes
z Instruction address
¾ Relative address (PC relative, i.e. Bcond)
¾ Register addressing (register indirect, i.e. JMP)

z Operand address
¾ Register addressing (Register is accessed as operand)
¾ Immediate addressing (Contained directly in instruction)
¾ Based addressing
¾ Bit addressing (accessing 1 bit directly)

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 17

 Instruction Set
Mnemonic Function Mnemonic Function Mnemonic Function

Load/Store instructions Logical operation instructions Arithmetic instructions

SLD.B Load Byte TST Test MOV Move

SLD.H Load Half-Word OR Or MOVHI Move High Half-Word

SLD.W Load Word ORI Or Immediate MOVEA Move Effective Address

LD.B Load Byte AND And ADD Add

LD.H Load Half-Word ANDI And Immediate ADDI Add Immediate

LD.W Load Word XOR Exclusive-Or SUB Subtract

SST.B Store Byte XORI Exclusive-Or Immediate SUBR Subtract Reverse

SST.H Store Half-Word NOT Not MULH Multiply Half-Word

SST.W Store Word SHL Shift Logical Left MULHI Multiply Half-Word Immediate

ST.B Store Byte SHR Shift Logical Right DIVH Divide Half-Word

ST.H Store Half-Word SAR Shift Arithmetic Right CMP Compare

ST.W Store Word Branch instructions SETF Set Flag Condition

Saturate instructions JMP Jump Special instructions

SATADD Saturated Add JR Jump Relative LDSR Load System Register

SATSUB Saturated Subtract JARL Jump and Register Link STSR Store System Register

SATSUBI Saturated Subtract Immediate Bcond Branch on Condition Code TRAP Trap

SATSUBR Saturated Subtract Reverse Bit manipulation instructions RETI Return from Trap or Interrupt

SET1 Set Bit HALT Halt

CLR1 Clear Bit DI Disable Interrupt

NOT1 Not Bit EI Enable Interrupt

TST1 Test Bit NOP No Operation

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 18

Applications

z Range of Applications:
z Digital consumer applications
z Inverters
z Industrial equipment
z Printers
z fax machines
z Etc… V850E/Mxx
Car
High End Lineup
More powerful, high performance memory
interface
QA

V850E/xxx
V850E1 Core
V850ES/xxx Industry

V850ES Core Specialized internal hardware

V850/xxx
ASSP Lineup Communic
V850 Core ation

Lowe power, low noise internal memory Informatio

V850ES/xxx
extensions n
application
V850/xxx
Low end lineup Quality of
life

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 19

Role in Applications
z Graphics Usage
¾ High performance, Interface to SDRAM, DMA controller

z DSP Usage
¾ Barrel shifter, Multiplier Unit, 5 stage pipeline, DMA controller

z Consumer Products Usage

¾ High Performance, Huge memory, USB, PWM, ADC, SDRAM

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 20

V850 & IAR O.S.
z FOR DSP and fast processing: The operating system uses the barrel shifter on the
V850 as following:
On array access, the BREL_BASE symbol is used.

C-Code:
int main( void )
{
int *p = array_1;
int *q = array_2;
*(p+10)= *(q +0) + *(q +1) + *(q +2) + *(q +3) + *(q +4) + *(q +5) + *(q+6) + *(q +7) + *(p +0) +
*(p +1) + *(p +2) + *(p +3) + *(p +4) + *(p +5) + *(p+6) + *(p +7);
return *(p+11);
}

ASM-Code:
-------------------------
MOVHI hi1(array_2+0-?BREL_BASE-0x8000),gp,r1
MOVEA lw1(array_2+0-?BREL_BASE-0x8000),r1,r1
MOVHI hi1(array_1+0-?BREL_BASE-0x8000),gp,r5
MOVEA lw1(array_1+0-?BREL_BASE-0x8000),r5,r5
LD.W (+0)[r1],r6
LD.W (+4)[r1],r7
CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 21
V850 & IAR O.S.
z Size optimized FIR Filter
- Loops n times through the mac-code.
- Designed for V850,
- Strategy imposes an instruction time penalty of
- One clock for the compare with n instruction and two (V850) clocks for the discarded pipeline when the branch is taken (n-1 times).
- Implementing a pointer to the sample and another one to the coefficients

.macro firsz filter,sample,size,scale

-- size optimized version
mov filter,r7 -- get address of FILTER struct
mov size-1,r11 -- get filter order - 1
ld.w filter_coeff[r7],r8 -- get address of coefficients to r8
ld.w filter_data[r7],r7 -- get address of data to r7
addi 2*(size-2),r8,r8 -- we start from the end
st.h sample,0[r7] -- store new sample
addi 2*(size-2),r7,r7 -- we start from the end
ld.h 2[r8],r10 -- coefficient
ld.h 2[r7],r9 -- data
ld.h 0[r7],r6 -- data
mulh r9,r10 -- multiply
.align 4
1:
ld.h 0[r8],r9 -- coefficient
st.h r6,2[r7] -- upshift
mulh r6,r9 -- multiply
add -2,r7 -- next data (go down)
add -2,r8 -- next coefficient (go down)
add r9,r10 -- accumulate result
add -1,r11 -- loop counter
ld.h 0[r7],r6 -- data
bne 1b -- branch back while not finished
satsubi -(1<<(scale-1)),r10,r10-- for proper rounding
sar scale,r10 -- scale the result
.endm

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 22

Packaging

z 176-Pin PlasticLQFP
z 0.5 mm pitch
z 24x24 mm
z 1.4 mm thick

z 240-Pin FBGA
z 0.8 mm pitch
z 16x16 mm
z 1.48 mm thick

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 23

 Pin Descriptions
Pin Name I/O Function Alternate Function
P10 Port 1 INTP10/UCLK
P11 4-bit I/O port INTP11/SCK0
P12 Input/output can be specified in 1-bit units. SI0/RXD0 – Serial I/O
P13 I/O SO0/TXD0 – serial I/O

P20 Input Port 2 NMI -- Interrupts

P20 is an input port dedicated to checking the NMI
P21 input INTP21/RXD1
P22 status. INTP22/TXD1
P23 If a valid edge is input, it operates as an NMI input. INTP23/SCK1
P24 P21 to P25 are a 5-bit I/O port. INTP24/SI1
P25 I/O Input/output can be specified in 1-bit units. INTP25/SO1

P50 Port 5 INTP50/DMARQ0

P51 6-bit I/O port INTP51/DMAAK0
P52 Input/output can be specified in 1-bit units. INTP52/TC0
P53 INTPC00/TIC0/DMARQ1
P54 INTPC01/DMAAK1
P55 I/O TOC0/TC1

P65 Port 6 INTPC20/TIC2/DMARQ2

P66 3-bit I/O port INTPC21/DMAAK2
P67 I/O Input/output can be specified in 1-bit units. TOC2/TC2 -- timers

P72 Port 7 INTPC31/DMAAK3

P73 6-bit I/O port TOC3/TC3 -- timers
P74 Input/output can be specified in 1-bit units.
P75
P76
P77 I/O

PAH0 to PAH9 I/O Port AH A16 to A25

8-/10-bit I/O port
Input/output can be specified in 1-bit units.

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 24

 Pin Descriptions
Pin Name I/O Function Alternate Function

PAL0 I/O Port AL INTPL0/A0

PAL1 2-bit I/O port INTPL1/A1
Input/output can be specified in 1-bit units.

PDH0 I/O Port DH D16/INTPD0

PDH1 8-/16-bit I/O port D17/INTPD1
PDH2 Input/output can be specified in 1-bit units. D18/INTPD2/TOC4
PDH3 D19/INTPD3
PDH4 D20/INTPD4
PDH5 D21/INTPD5/TOC5
PDH6 D22/INTPD6/INTP100/TCUD10
PDH7 D23/INTPD7/INTP101/TCLR10
PDH8 D24/INTPD8/TO10
PDH9 D25/INTPD9/TIUD10
PDH10 D26/INTPD10/INTP110/TCUD11
PDH11 D27/INTPD11/INTP111/TCLR11
PDH12 D28/INTPD12/TO11
PDH13 D29/INTPD13/TIUD11
PDH14 D30/INTPD14/PWM0
PDH15 D31/INTPD15/PWM1

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 25

 Pin Descriptions
Pin Name I/O Function Alternate Function
PCD0 I/O Port CD SDCKE
PCD1 4-bit I/O port BUSCLK
PCD2 Input/output can be specified in 1-bit units. SDCAS
PCD3 SDRAS
PCM0 Port CM WAIT
PCM1 6-bit I/O port HLDAK
PCM2 Input/output can be specified in 1-bit units. HLDRQ
PCM3 REFRQ
PCM4 ADTRG/SELFREF
PCM5 I/O CS0

PCS0 Port CS CS1

PCS1 8-bit I/O port CS2/IOWR
PCS2 Input/output can be specified in 1-bit units. CS3
PCS3 CS4
PCS4 CS5/IORD
PCS5 CS6
PCS6 CS7
PCS7 I/O

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 26

 Pin Descriptions

Pin Name I/O Function Alternate Function

PCT0 Port CT LLWR/LLBE/LLDQM

PCT1 7-bit I/O port LUWR/LUBE/LUDQM

PCT2 Input/output can be specified in 1-bit units. ULWR/ULBE/ULDQM

PCT3 UUWR/UUBE/UUDQM

PCT4 RD

PCT5 WE/WR

PCT7 BCYST

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 27

 Pins By Function
Pin Name I/O Function Alternate Function
Output 26-bit address bus for external memory PAL0/INTPL0
A0 PAL1/INTPL1
A1
A2 to A9
A10 to A15
A16 to A25 PAH0 to PAH9
ADTRG input A/D converter external trigger input PCM5/SELFREF
ANI0 to ANI7 input Analog inputs to A/D converter
AVDD 3.3 V positive power supply for A/D converter
AVREFM input Reference voltage applied to A/D converter
AVREFP
AVSS Ground potential for A/D converter
BCYST Output Strobe signal output that shows the start of the bus cycle PCT7
BUSCLK Output Clock output for SDRAM PCD1
CS0 Output Chip select signal output PCS0
CS1 PCS1
CS2 PCS2/IOWR
CS3 PCS3
CS4 PCS4
CS5 PCS5/IORD
CS6 PCS6
CS7 PCS7
D0 to D15 I/O 32-bit data bus for external memory
D16 PDH0/INTPD0
D17 PDH1/INTPD1
D18 PDH2/INTPD2/TOC4
D19 PDH3/INTPD3
D20 PDH4/INTPD4
D21 PDH5/INTPD5/TOC5
D22 PDH6/INTPD6/INTP100/TCUD10
D23 PDH7/INTPD7/INTP101/TCLR10
D24 PDH8/INTPD8/TO10
D25 PDH9/INTPD9/TIUD10
D26 PDH10/INTPD10/INTP110/TCUD11
D27 PDH11/INTPD11/INTP111/TCLR11
D28 PDH12/INTPD12/TO11
D29 PDH13/INTPD13/TIUD11
D30 PDH14/INTPD14/PWM0
D31 PDH15/INTPD15/PWM1
CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 28
 Pins by Function
Pin Name I/O Function Alternate Function
DCK I/O Debug clock input −
DDI Input Debug data input −
DDO Input Debug data output −
DMAAK0 Output P51/INTP51
DMAAK1 P54/INTPC01
DMAAK2 P73/INTPC21
DMAAK3 Output P76/INTPC31 P76/INTPC31
DMARQ0 P50/INTP50
DMARQ1 P53/INTPC00/TIC0
DMARQ2 P72/INTPC20/TIC2
DMARQ3 Input DMA request signal input P75/INTPC30/TIC3
DMS Input Debug mode select −
DRST Input Reset input for debug −
EVDD 3.3 V positive power supply for external pin −
EVSS Ground potential for external pin −
HLDAK Output Bus hold acknowledge output PCM2
HLDRQ Input Bus hold request input PCM3
INTP10 P10/UCLK
INTP11 P11/SCK0
INTP21 P21/RXD1
INTP22 P22/TXD1
INTP23 P23/SCK1
INTP24 P24/SI1
INTP25 P25/SO1
INTP50 P50/DMARQ0
INTP51 P51/DMAAK0
INTP52 P52/TC0
INTP65 P65/TIC1/INTPC10
INTP66 P66/INTPC11
INTP67 P67/TOC1
INTPD0 PDH0/D16
INTPD1 PDH1/D17
INTPD2 PDH2/TOC4/D18
INTPD3 PDH3/D19
INTPD4 PDH4/D20
INTPD5 PDH5/TOC5/D21
INTPD6 PDH6/INTP100/TCUD10/D22
INTPD7 PDH7/INTP101/TCLR10/D23
INTPD8 PDH8/TO10/D24
INTPD9 PDH9/TIUD10/D25
INTPD10 Input External maskable interrupt request input PDH10/INTP110/TCUD11/D26

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 29

 Pins by Function
Pin Name I/O Function
INTPD11 Input External maskable interrupt request input
INTPD12
INTPD13
INTPD14
INTPD15
INTPL0
INTPL1
INTP100 Input Timer ENC10 external capture trigger input
INTP101
INTP110 Input Timer ENC11 external capture trigger input
INTP111
INTPC00 Input External maskable interrupt request input/timer C0
INTPC01 external capture trigger input
INTPC10 External maskable interrupt request input/timer C1
INTPC11 external capture trigger input
INTPC20 External maskable interrupt request input/timer C2
INTPC21 external capture trigger input
INTPC30 External maskable interrupt request input/timer C3
INTPC31 external capture trigger input
IORD Output DMA read strobe signal output
IOWR Output DMA write strobe signal output
IVDD 1.5 V positive power supply for internal unit
IVSS Ground potential for internal unit
JIT0 Input Specifying SSCG operating mode
JIT1
LLBE Output External data bus byte enable signal output (lowest byte((D0 to D7))
LLDQM Output Output disable/write mask signal output for SDRAM (lowest byte (D0 to D7))
LLWR Output External data bus write strobe signal output (lowest byte(D0 to D7))
LUBE Output External data bus byte enable signal output (third byte (D8to D15))
LUDQM Output Output disable/write mask signal output for SDRAM (thirdbyte (D8 to D15))
LUWR Output External data bus write strobe signal output (third byte (D8to D15))
MODE0 Input Specifying V850E/ME2 operating mode
MODE1
NMI Input Non-maskable interrupt request signal input
OSCVDD 3.3 V positive power supply for oscillator
OSCVSS Ground potential for oscillator
PLLSEL Input Input specifying PLL operating mode

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 Pins By Function
Pin Name I/O Function
PLLVDD 1.5 V positive power supply for PLL synthesizer
PLLVSS Ground potential for PLL synthesizer
PWM0 Output PWM pulse signal output
PWM1
RD Output External data bus read strobe signal output
REFRQ Output Refresh request signal output for SDRAM
RESET Input System reset input
RXD0 Input UARTB0 and UARTB1 serial receive data input
RXD1
SCK0 I/O CSI30 and CSI31 serial clock I/O (3-wire)
SCK1
SDCAS Output Column address strobe signal output for SDRAM
SDCKE Output SDRAM clock enable signal output
SDRAS Output Row address strobe signal output for SDRAM
SELFREF Input Self-refresh request input for SDRAM
SI0 Input CSI30 and CSI31 serial receive data input (3-wire)
SI1
SO0 Output CSI30 and CSI31 serial transmit data output (3-wire)
SO1
SSEL0 Input Specifying the clock generator’s operating mode
SSEL1
TC0 Output DMA transfer end (terminal count) signal output
TC1
TC2
TC3
TCLR10 Input Clear signal input to timer ENC10 and ENC11
TCLR11
TCUD10 Input Count operation switching signal input to timer ENC10 and ENC11
TCUD11
TIC0 Input External count clock input of timer C0 to C3
TIC1
TIC2
TIC3
TIUD10 Input External count clock input to timer ENC10 and ENC11
TIUD11
TO10 Output Pulse signal output of timer ENC10 and ENC11
TO11

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 31

 Pins By Function
Pin I/O Function
TOC0 Output Pulse signal output of timer C0 to C5
TOC1
TOC2
TOC3
TOC4
TOC5
TRCCLK Output Trace clock output
TRCDATA0 Output Trace data output (D0 to D3)
TRCDATA1
TRCDATA2
TRCDATA3
TRCEND Output Trace end status output
TXD0 Output UARTB0 and UARTB1 serial transmit data output
TXD1
UCLK Input USB clock signal input
UDM I/O USB data I/O (−)
UDP I/O USB data I/O (+)
ULBE Output External data bus byte enable signal output (second byte (D16 to D23))

ULDQM Output Output disable/write mask signal output for SDRAM(second byte (D16 to D23))

ULWR Output External data bus write strobe signal output (second byte(D16 to D23))

UUBE Output External data bus byte enable signal output (highest byte(D24 to D31))

UUDQM Output Output disable/write mask signal output for SDRAM(highest byte (D24 to D31))

UUWR Output External data bus write strobe signal output (highest byte(D24 to D31))

UVDD 3.3 V positive power supply for USB

WAIT Input Control signal input that inserts a wait in the bus cycle

WE Output Write enable signal output for SDRAM

WR Output Write strobe signal output for SDRAM
X1 Input Connects the crystal resonator for system clock oscillation.
X2

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 32

Development Environment

z Evaluation Board (starter kit)

z Enables RISC chip performance sampling with only a serial connection to a PC
z Low-cost GUN Compiler exeCC assessment-version package featuring
assessment board and PARTNER monitor-debugger
z Includes connector for writing to CPU's internal flash memory

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 33

Development Environment

z In-circuit emulator
z IE-V850E1-CD-NW
z Compact PC card-type emulator
z Supports flash programmer functions

z IE-V850ESK1-ET, IECUBE
series
z Integrate emulation board into emulator body
z USB I/F for PC (Hi-Speed USB I/F, USB1.1)
z Real-time RAM monitor, time measurement
function, USB_IF

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 34

 References
¾NEC User Manuals
‰User’s Manual
V850 FAMILY 32-bit Single-Chip Microcontroller Architecture
Document No. U10243EJ7V0UM00 (7th edition), Date Published March 2001 J CP(K)

‰V850 Series Development Environment.

Document No. U15763EJ3V0PF00_E2, Date Feb. 2004

‰V850E/ME2 User’s Manual

32-Bit Single-Chip Microcontroller , Hardware µPD703111A
Document No. U16031EJ3V0UD00 (3rd edition), Date Published June 2004 N CP(K)
‰Application Notes
Digital Signal Processing with V850 and V850E Devices
Document No. U17285EE1V0AN00
Date Published August 2004, NEC Corporation 2004, Printed in Germany

¾http://www.necel.com/micro/english/v850/product/cpucore.html

CS433 Prof. Luddy Harrison Copyright 2005 University of Illinois 35