OPA615

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Wide-Bandwidth, DC Restoration Circuit

Check for Samples: OPA615

1FEATURES DESCRIPTION
•
2 PROPAGATION DELAY: 1.9ns The OPA615 is a complete subsystem for very fast
• BANDWIDTH: and precise DC restoration, offset clamping, and
OTA: 710MHz low-frequency hum suppression of wideband
Comparator: 730MHz amplifiers or buffers. Although it is designed to
stabilize the performance of video signals, the circuit
• LOW INPUT BIAS CURRENT: ±1μA can also be used as a sample-and-hold amplifier,
• SAMPLE-AND-HOLD SWITCHING high-speed integrator, or peak detector for
TRANSIENTS: ±5mV nanosecond pulses. The device features a wideband
• SAMPLE-AND-HOLD FEEDTHROUGH Operational Transconductance Amplifier (OTA) with a
REJECTION: 100dB high-impedance cascode current source output and
fast and precise sampling comparator that together
• CHARGE INJECTION: 40fC set a new standard for high-speed applications. Both
• HOLD COMMAND DELAY TIME: 2.5ns the OTA and the sampling comparator can be used
• TTL/CMOS HOLD CONTROL as stand-alone circuits or combined to form a more
complex signal processing stage. The self-biased,
bipolar OTA can be viewed as an ideal
APPLICATIONS voltage-controlled current source and is optimized for
• BROADCAST/HDTV EQUIPMENT low input bias current. The sampling comparator has
• TELECOMMUNICATIONS EQUIPMENT two identical high-impedance inputs and a current
• HIGH-SPEED DATA ACQUISITION source output optimized for low output bias current
• CAD MONITORS/CCD IMAGE PROCESSING and offset voltage; it can be controlled by a
TTL-compatible switching stage within a few
• NANOSECOND PULSE INTEGRATOR/PEAK nanoseconds. The transconductance of the OTA and
DETECTOR sampling comparator can be adjusted by an external
• PULSE CODE MODULATOR/DEMODULATOR resistor, allowing bandwidth, quiescent current, and
• COMPLETE VIDEO DC LEVEL RESTORATION gain trade-offs to be optimized.
• SAMPLE-AND-HOLD AMPLIFIER The OPA615 is available in both an SO-14
• SHC615 UPGRADE surface-mount and an MSOP-10 package.
Ground CHOLD Base

9 4 3

2
Emitter
Hold 7 Switching
Control Stage
OTA
Sampling
12 Collector
Comparator (SC)
(IOUT)
S/H 10
In+ 1
SOTA ∞ Biasing IQ Adjust
S/H 11
In−
OPA615

13 5

+VCC −VCC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
OPA615

SBOS299E – FEBRUARY 2004 – REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

Table 1. ORDERING INFORMATION (1)

SPECIFIED
PACKAGE TEMPERATURE PACKAGE TRANSPORT MEDIA,
PRODUCT PACKAGE DESIGNATOR RANGE MARKING ORDERING NUMBER QUANTITY
OPA615ID Rails, 50
OPA615 SO-14 D –40°C to +85°C OPA615ID
OPA615IDR Tape and Reel, 2500
OPA615IDGST Tape and Reel, 250
OPA615 MSOP-10 DGS –40°C to +85°C BJT
OPA615IDGSR Tape and Reel, 2500

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.

ABSOLUTE MAXIMUM RATINGS (1)

Supply Voltage ±6.5V
Differential Input Voltage ±VS
Common-Mode Input Voltage Range ±VS
Hold Control Pin Voltage –VS to +VS
Storage Temperature Range –65°C to +125°C
Junction Temperature (TJ) +150°C
ESD Ratings:
Human Body Model (HBM) (2) 1000V
Charge Device Model (CDM) 1000V
Machine Model (MM) 150V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Pin 2 for the SO-14 package and pin 1 for the MSOP-10 package > 500V HBM.

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BLOCK DIAGRAMS

SO−14 MSOP−10
Ground CHO LD Base Ground CHO LD Base

9 4 3 6 3 2

2 1
Emitter Emitter
Hold 7 Switching Hold 5 Switching
Control Stage Control Stage

Sampling Sampling
12 Collector 9 Collector
Comparator (SC) OTA Comparator (SC) OTA
(IO UT ) (IO U T )
S/H 10 S/H 7
In+ 1 In+
SOTA ∞ Biasing IQ Adjust SOTA ∞ Biasing
S/H 11 S/H 8
In− In−
OPA615 OPA615

13 5 10 4

+VCC −VC C +VCC −VC C

PIN CONFIGURATIONS

Top View

IQ Adjust 1 14 NC(1) Emitter, E 1 10 +VCC

Emitter, E 2 13 +VCC Base, B 2 9 IOUT, Collector, C

Base, B 3 12 IOUT, Collector, C CHOLD 3 BJT 8 S/H In−

CHOLD 4 OPA615 11 S/H In− −VCC 4 7 S/H In+

−VCC 5 10 S/H In+ Hold Control 5 6 Ground

NC(1) 6 9 Ground
MSOP−10
Hold Control 7 8 NC(1)

SO−14

NOTE: (1) No Connection.

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ELECTRICAL CHARACTERISTICS: VS = ±5V

RL = 100Ω, RQ = 300Ω, and RIN = 50Ω, unless otherwise noted.
OPA615ID, OPA615IDGS
TYP MIN/MAX OVER TEMPERATURE
0°C to –40°C to MIN/ TEST
(2)
PARAMETER CONDITIONS +25°C +25°C 70°C (3) +85°C (3) UNIT MAX LEVEL (1)
AC PERFORMANCE (OTA) See Figure 36b
Small-Signal Bandwidth (B to E) VO = 200mVPP, RL = 500Ω 710 MHz min C
VO = 1.4VPP, RL = 500Ω 770 MHz min C
VO = 2.8VPP, RL = 500Ω 230 MHz min C
Large-Signal Bandwidth (B to E) VO = 5VPP, RL = 500Ω 200 MHz min C
Small-Signal Bandwidth (B to C) G = +1, VO = 200mVPP, RL = 100Ω 440 MHz min C
G = +1, VO = 1.4VPP, RL = 100Ω 475 MHz min C
G = +1, VO = 2.8VPP, RL = 100Ω 230 MHz min C
Large-Signal Bandwidth (B to C) G = +1, VO = 5VPP, RL = 100Ω 230 MHz min C
Rise-and-Fall Time (B to E) VO = 2VPP, RL = 500Ω 2 ns max C
Rise-and-Fall Time (B to C) G = +1, VO = 2VPP, RL = 100Ω 2 ns max C
Harmonic Distortion (B to E) RE = 100Ω
2nd-Harmonic VO = 1.4VPP, f = 30MHz –62 –50 –48 –47 dBc min B
3rd-Harmonic VO = 1.4VPP, f = 30MHz –47 –40 –35 –33 dBc min B
Input Voltage Noise Base Input, f > 100kHz 4.6 6.2 6.9 7.4 nV/√Hz max B
Input Current Noise Base Input, f > 100kHz 2.5 3.1 3.6 3.9 pA/√Hz max B
Input Current Noise Emitter Input, f > 100kHz 21 23 25 27 pA/√Hz max B
DC PERFORMANCE (OTA) See Figure 37b
Transconductance (V-base to I-collector) VB = ±5mVPP, RC = 0Ω, RE = 0Ω 72 65 63 58 mA/V min A
B-Input Offset Voltage VB = 0V, RC = 0V, RE = 100Ω ±4 ±40 ±47 ±50 mV max A
B-Input Offset Voltage Drift VB = 0V, RC = 0V, RE = 100Ω ±160 ±160 μV/°C max B
B-Input Bias Current VB = 0V, RC = 0V, RE = 100Ω ±0.5 ±0.9 ±1.5 ±1.7 μA max A
B-Input Bias Current Drift VB = 0V, RC = 0V, RE = 100Ω ±12 ±12 nA/°C max B
E-Input Bias Current VB = 0V, VC = 0V ±35 ±110 ±120 ±135 μA min A
E-Input Bias Current Drift VB = 0V, VC = 0V ±200 ±250 nA/°C max B
C-Output Bias Current VB = 0V, VC = 0V ±35 ±100 ±110 ±125 μA max A
C-Output Bias Current VB = 0V, VC = 0V ±200 ±250 nA/°C max B
INPUT (OTA Base) See Figure 37b
Input Voltage Range RE = 100Ω ±3.4 ±3.2 ±3.1 ±3.0 V min B
Input Impedance B-Input 7 || 1.5 MΩ || pF typ C
OTA Power-Supply Rejection Ratio
±VS to VIO at E-Input 54 49 47 46 dB min A
(–PSRR)
OUTPUT (OTA Collector) See Figure 37b
Output Voltage Compliance IE = 2mA ±3.5 ±3.4 ±3.4 ±3.4 V min A
Output Current VC = 0V ±20 ±18 ±17 ±17 mA min A
Output Impedance VC = 0V 1.2 || 2 MΩ || pF typ C
COMPARATOR PERFORMANCE
AC Performance
Output Current Bandwidth IO < 4mAPP 730 520 480 400 MHz min B
Output Current Rise and Fall Time IIO = ±2mAPP, RL = 50Ω at CHOLD 1.4 1.5 1.7 2 ns max B
Control Propagation Delay Time Hold ≥ Track and Track ≥ Hold 2.5 ns typ C
Signal Propagation Delay Time S/H In+ – S/H In– to CHOLD Current 1.9 ns typ C
Input Differential Voltage Noise S/H In+ – S/H In– 6 7.5 8 9 nV/√Hz max B
Charge Injection Track-to-Hold 40 fC typ C
Feedthrough Rejection Hold Mode, VIN = 1VPP, f < 20MHz 100 dB typ C

(1) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
(2) Junction temperature = ambient for +25°C tested specifications.
(3) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over
temperature specifications.

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ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)

RL = 100Ω, RQ = 300Ω, and RIN = 50Ω, unless otherwise noted.
OPA615ID, OPA615IDGS
TYP MIN/MAX OVER TEMPERATURE
0°C to –40°C to MIN/ TEST
(2)
PARAMETER CONDITIONS +25°C +25°C 70°C (3) +85°C (3) UNIT MAX LEVEL (1)
DC Performance
Input Bias Current S/H In+ = S/H In– = 0V ±1 ±3 ±3.5 ±4.0 μA max A
Output Offset Current S/H In+ = S/H In– = 0V, Track Mode ±10 ±50 ±70 ±80 μA max A
Input Impedance S/H In+ and S/H In– 200 || 1.2 kΩ || pF typ C
Input Differential Voltage Range S/H In+ – S/H In– ±3.0 V typ C
Input Common-Mode Voltage Range S/H In+ and S/H In– ±3.2 V typ C
Common-Mode Rejection Ratio (CMRR) ±2 ±50 ±55 ±60 μA/V max A
Output Voltage Compliance CHOLD Pin ±3.5 V typ C
Output Current CHOLD Pin ±5 ±3 ±2.5 ±2.0 mA min A
Output Impedance CHOLD Pin 0.5 || 1.2 MΩ || pF typ C
Transconductance S/H In+ – S/H In– to CHOLD Current 35 21 20 19 mA/V min A
VIN = 300mVPP
Minimum Hold Logic High Voltage Tracking High 2 2 2 V max A
Maximum Hold Logic Low Voltage Holding Low 0.8 0.8 0.8 V min A
Logic High Input Current VHOLD = +5V ±0.5 ±1 ±1 ±1.2 μA max A
Logic Low Input Current VHOLD = 0V 140 200 220 230 μA max A
Comparator Power-Supply Rejection S/H In+ = S/H In– = 0V, Track Mode
±2 ±50 ±55 ±60 μA/V max A
Ratio (PSRR)
POWER SUPPLY
Specified Operating Voltage ±5 V typ C
Minimum Operating Voltage ±4 ±4 ±4 V min B
Maximum Operating Voltage ±6.2 ±6.2 ±6.2 V max A
Maximum Quiescent Current RQ = 300Ω (4) 13 14 16 17 mA max A
Minimum Quiescent Current RQ = 300Ω (4) 13 12 11 9 mA min A
THERMAL CHARACTERISTICS
Specified Operating Range D Package –40 to +85 °C typ C
Thermal Resistance θ JA Junction-to-Ambient
DGS MSOP-10 125 °C/W typ C
D SO-14 100 °C/W typ C

(4) SO-14 package only.

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TYPICAL CHARACTERISTICS
TA = +25°C and IQ = 13mA, unless otherwise noted.

OTA
OTA TRANSCONDUCTANCE vs FREQUENCY OTA TRANSCONDUCTANCE vs QUIESCENT CURRENT
120 IOUT
120
VIN = 10mVPP VIN = 100mVPP
VIN
50Ω
100 IQ = 14.3mA (89mA/V), RQ = 0Ω 50Ω 100
Transconductance (mA/V)

Transconductance (mA/V)
80 IQ = 13mA (72mA/V), RQ = 300Ω 80

60 60 IOUT

40 40 VIN
IQ = 9.6mA (28mA/V), RQ = 2kΩ 50Ω
50Ω
20 30

0 0
10k 1M 10M 100M 1G 8 9 10 11 12 13 14 15
Frequency (Hz) Quiescent Current (mA)

Figure 1. Figure 2.

OTA TRANSCONDUCTANCE vs INPUT VOLTAGE OTA TRANSFER CHARACTERISTICS

100 20
I O UT
90 15
IQ = 14.3mA VIN
Transconductance (mA/V)

OTA Output Current (mA)

50Ω
80 10
50Ω
70 5
IQ = 13mA
60 0
IQ = 13mA IQ = 9.6mA
50 −5
I Q = 9.6mA
40 −10
IQ = 14.3mA
30 −15
Small−Signal Around Input Voltage
20 −20
−50 −40 −30 −20 −10 0 10 20 30 40 50 −200 −150 −100 −50 0 50 100 150 200
Input Voltage (mV) OTA Input Voltage (mV)

Figure 3. Figure 4.

OTA-C SMALL SIGNAL PULSE RESPONSE OTA-C LARGE SIGNAL PULSE RESPONSE
0.15 3
fIN = 10MHz fIN = 10MHz
G = +1V/V G = +1V/V
0.10 2
VIN = 0.2VPP VIN = 4VPP
Output Voltage (V)

Output Voltage (V)

0.05 1

0 0

−0.05 −1

−0.10 −2

−0.15 −3
Time (10ns/div) Time (10ns/div)

Figure 5. Figure 6.

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TYPICAL CHARACTERISTICS (continued)

TA = +25°C and IQ = 13mA, unless otherwise noted.
OTA B-INPUT RESISTANCE vs QUIESCENT CURRENT OTA C-OUTPUT RESISTANCE vs QUIESCENT CURRENT
140 18
16

OTA C−Output Resistance (MΩ )

OTA B−Input Resistance (MΩ )

120
14
100
12
80 10

60 8

6
40
4
20
2
0 0
8 9 10 11 12 13 14 15 8 9 10 11 12 13 14 15
Quiescent Current (mA) Quiescent Current (mA)

Figure 7. Figure 8.

OTA E-OUTPUT RESISTANCE vs QUIESCENT CURRENT OTA INPUT VOLTAGE AND CURRENT NOISE DENSITY
180 100

160
Voltage Noise Density (nV/√Hz)
Current Noise Density (pA/√Hz)
OTA E−Output Resistance (Ω)

140
E−Input Current Noise (21.0pA/√Hz)
120
100
10
80
B−Input Voltage Noise (4.6nV/√Hz)
60
B−Input Current Noise (2.5pA/√Hz)
40

20
0 1
8 9 10 11 12 13 14 15 100 1k 10k 100k 1M 10M
Quiescent Current (mA) Frequency (Hz)

Figure 9. Figure 10.

OTA B-INPUT OFFSET VOLTAGE AND BIAS CURRENT

vs TEMPERATURE OTA TRANSFER CHARACTERISTICS vs INPUT VOLTAGE
2.0 0.10 35
Degenerated E−Input IQ = 14.3mA
30 RE = RL = 100Ω
1.5 25
B−Input Offset Voltage (mV)

OTA−C Output Current (mA)

IO UT
B−Input Bias Current (µV)

20
1.0 0.05
15 VIN 100Ω
B−Input Bias Current 10 IQ = 9.6mA
0.5
100Ω
5
0 0 0 IQ = 13mA
−5
−0.5
−10
−1.0 −0.05 −15
B−Input Offset Voltage
−20
−1.5 −25
−30
−2.0 −0.10 −35
−40 −20 0 20 40 60 80 100 120
−3.5 −3 −2.5 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5
Ambient Temperature (_ C)
OTA−B Input Voltage (mV)

Figure 11. Figure 12.

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TYPICAL CHARACTERISTICS (continued)

TA = +25°C and IQ = 13mA, unless otherwise noted.
OTA-E OUTPUT FREQUENCY RESPONSE OTA-E OUTPUT PULSE RESPONSE
3 200 2.0
VO = 0.6VPP 160 1.6
0 120 1.2

Output Voltage (mV)

VO = 1.4VPP

Output Voltage (V)

80 0.8
−3
40 Large−Signal 0.4
Gain (dB)

VO = 5VPP ±1.6V
−6 0 Small−Signal 0
Right Scale
±80mV
−40 −0.4
VO = 2.8VPP Left Scale 100Ω
−9 100Ω
−80 VIN −0.8
V IN
VO = 0.2VPP −120
50Ω VO
−1.2
50Ω VO
−12 500Ω
500Ω −160 −1.6
−200 −2.0
−15
1M 10M 100M 1G Time (20ns/div)

Frequency (Hz)

Figure 13. Figure 14.

OTA-C OUTPUT FREQUENCY RESPONSE OTA-E OUTPUT HARMONIC DISTORTION vs FREQUENCY

3 −40
VOUT = 1.4VPP
0 −45
Harmonic Distortion (dBc)

VO = 0.6VPP
−3 −50
3rd−Harmonic
Gain (dB)

VO = 1.4VPP
−6 −55
VO VO = 0.2VPP 2nd−Harmonic
−9 V IN
100Ω −60
50Ω VO = 2.8VPP V IN

−12 100Ω −65 50Ω V OUT

10 0Ω
VO = 5VPP
−15 −70
1M 10M 100M 1G 1 10 100
Frequency (Hz) Frequency (MHz)

Figure 15. Figure 16.

OTA-C OUTPUT HARMONIC DISTORTION vs FREQUENCY OTA QUIESCENT CURRENT vs RQ

−20 16
VO U T V OUT = 1.4VPP
−25 VIN
100Ω 15
Harmonic Distortion (dBc)

50Ω
Quiescent Current (mA)

−30 100Ω 14

−35 13

−40 12
+IQ
−45 11

−50 3rd−Harmonic
10
−IQ
−55 9
2nd−Harmonic
−60 8
1 10 100 0.1 1 10 100 1k 10k 100k
Frequency (MHz) R Q (Ω)

Figure 17. Figure 18.

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TYPICAL CHARACTERISTICS (continued)

TA = +25°C and IQ = 13mA, unless otherwise noted.
SOTA (Sampling Operational Transconductance Amplifier)
SOTA TRANSCONDUCTANCE vs FREQUENCY SOTA TRANSCONDUCTANCE vs QUIESCENT CURRENT
40 40
VIN = 10mVPP

Transconductance (mA/V)
Transconductance (mA/V)

30 30

20 20

VIN IO UT
10 SOTA ∞
10
50Ω
50Ω
+5V RQ Adjusted
Hold Control
0 0
1M 10M 100M 1G 8 9 10 11 12 13 14 15
Frequency (Hz) Quiescent Current (mA)

Figure 19. Figure 20.

SOTA TRANSCONDUCTANCE vs INPUT VOLTAGE SOTA TRANSFER CHARACTERISTICS

45 8

40 6
SOTA Output Current (mA)
Transconductance (mA/V)

35 4
30
2
25
0
20
−2
15
−4
10

5 −6
Small−Signal Around Input Voltage
0 −8
−100 −80 −60 −40 −20 0 20 40 60 80 100 −200 −150 −100 −50 0 50 100 150 200
Input Voltage (mV) SOTA Input Voltage (mV)

Figure 21. Figure 22.

SOTA PULSE RESPONSE SOTA PULSE RESPONSE

150 150
fIN = 20MHz fIN = 20MHz
RL = 50Ω RL = 50Ω
100 IOUT = 4mAPP 100
IOUT = 4mAPP
tRISE = 2ns
Output Voltage (mV)

tRISE = 10ns
Output Voltage (mV)

50 50

0 0

−50 −50

−100 −100
Hold Control = +5V Hold Control = +5V
−150 −150
Time (10ns/div) Time (10ns/div)

Figure 23. Figure 24.

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TYPICAL CHARACTERISTICS (continued)

TA = +25°C and IQ = 13mA, unless otherwise noted.
SOTA PROPAGATION DELAY vs OVERDRIVE SOTA PROPAGATION DELAY vs TEMPERATURE
1.3 2.0
Negative 1.8
1.2 1.6 Falling Edge
Propagation Delay (ns)

Propagation Delay (ns)

1.4
Rising Edge
1.1 Positive 1.2
1.0
1.0 0.8
100W
VOD VOD 0.6
SOTA
GND
0.9 VOD 0.4
100W
0.2
0.8 0
0 200 400 600 800 1000 1200 −40 −20 0 20 40 60 80 100 120
Input Voltage (mV) Temperature (_ C)

Figure 25. Figure 26.

SOTA PROPAGATION DELAY vs SLEW RATE SOTA SWITCHING TRANSIENTS

1.4 10
100Ω
VOUT

1.3 ON −OFF
Switching Transient (mV)

50Ω
Propagation Delay (ns)

5 100Ω
TTL
1.2

Negative OFF −ON

1.1 0

1.0
VIN = 1.2Vpp
−5
+0.6V Positive
0.9 0V
−0.6V
0.8 −10
0 1 2 3 4 5 6 7 8 9 10 Time (10ns/div)
Rise Time (ns)

Figure 27. Figure 28.

SOTA HOLD COMMAND DELAY TIME SOTA BANDWIDTH vs OUTPUT CURRENT SWING
Hold Command (V)

2.5 6
2.0 IOUT = 0.5mAPP
3
1.5
1.0 0
0.5 IOUT = 4mAPP
Gain (dB)

0 −3
150 −50
Output Voltage (mV)

100 −6
IOUT = 2mAPP
50
−9
0
−50 −12
−100
−150 −15
Time (10ns/div) 1M 10M 100M 1G 2G
Frequency (Hz)

Figure 29. Figure 30.

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TYPICAL CHARACTERISTICS (continued)

TA = +25°C and IQ = 13mA, unless otherwise noted.
SOTA FEEDTHROUGH REJECTION vs FREQUENCY SOTA COMMON-MODE REJECTION vs FREQUENCY
0 0
Hold Control = 0V Hold Control = 5V
(Off−Isolation) V+ = V−

Common−Mode Rejection (dB)

−20 −20
Feedthrough Rejection (dB)

−40 −40

−60 −60

−80 −80

−100 −100

−120 −120
1M 10M 100M 1G 100k 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)

Figure 31. Figure 32.

SOTA INPUT BIAS CURRENT vs TEMPERATURE SOTA OUTPUT BIAS CURRENT vs TEMPERATURE
0.40 50
Hold Control = 5V
40
0.35 V+ = V− = 0V
30
Output Bias Current (µA)
Input Bias Current (µA)

0.30 Positive Input

20
0.25 Negative Input
10
0.20 0
−10
0.15
−20
0.10
−30
0.05 −40
0 −50
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
Temperature (_C) Temperature (_ C)

Figure 33. Figure 34.

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DISCUSSION OF PERFORMANCE

The OPA615, which contains a wideband Operational

Transconductance Amplifier (OTA) and a fast OPERATIONAL TRANSCONDUCTANCE
sampling comparator (SOTA), represents a complete AMPLIFIER (OTA) SECTION
subsystem for very fast and precise DC restoration,
OVERVIEW
offset clamping and correction to GND or to an
adjustable reference voltage, and low frequency hum The symbol for the OTA section is similar to that of a
suppression of wideband operational or buffer bipolar transistor, and the self-biased OTA can be
amplifiers. viewed as either a quasi-ideal transistor or as a
voltage-controlled current source. Application circuits
Although the IC was designed to improve or stabilize
for the OTA look and operate much like transistor
the performance of complex, wideband video signals,
circuits—the bipolar transistor is also a
it can also be used as a sample-and-hold amplifier,
voltage-controlled current source. Like a transistor, it
high-speed integrator, peak detector for nanosecond
has three terminals: a high-impedance input (base)
pulses, or as part of a correlated double sampling
optimized for a low input bias current of 0.3μA, a
system. A wideband Operational Transconductance
low-impedance input/output (emitter), and the
Amplifier (OTA) with a high-impedance cascode
high-impedance current output (collector).
current source output and a fast and precise
sampling comparator sets a new standard for The OTA consists of a complementary buffer
high-speed sampling applications. amplifier and a subsequent complementary current
mirror. The buffer amplifier features a Darlington
Both the OTA and the sampling comparator can be
output stage and the current mirror has a cascoded
used as stand-alone circuits or combined to create
output. The addition of this cascode circuitry
more complex signal processing stages such as
increases the current source output resistance to
sample-and-hold amplifiers. The OPA615 simplifies
1.2MΩ. This feature improves the OTA linearity and
the design of input amplifiers with high hum
drive capabilities. Any bipolar input voltage at the
suppression; clamping or DC-restoration stages in
high impedance base has the same polarity and
professional broadcast equipment, high-resolution
signal level at the low impedance buffer or emitter
CAD monitors and information terminals; and signal
output. For the open-loop diagrams, the emitter is
processing stages for the energy and peak value of
connected to GND; the collector current is then
nanoseconds pulses. This device also eases the
determined by the voltage between base and emitter
design of high-speed data acquisition systems behind
times the transconductance. In application circuits
a CCD sensor or in front of an analog-to-digital
(Figure 36b), a resistor RE between the emitter and
converter (ADC).
GND is used to set the OTA transfer characteristics.
An external resistor on the SO-14 package, RQ,
The following formulas describe the most important
allows the user to set the quiescent current. RQ is
relationships. re is the output impedance of the buffer
connected from Pin 1 (IQ adjust) to –VCC. It
amplifier (emitter) or the reciprocal of the OTA
determines the operating currents of the OTA section
transconductance. Above ±5mA, the collector current,
and controls the bandwidth and AC behavior as well
IC, will be slightly less than indicated by the formula.
as the transconductance of the OTA.
V IN V IN
Besides the quiescent current setting feature, a IC + or RE + * rE
r E ) RE IC (1)
Proportional-to-Absolute-Temperature (PTAT) supply
current control will increase the quiescent current The RE resistor may be bypassed by a relatively large
versus temperature. This variation holds the capacitor to maintain high AC gain. The parallel
transconductance (gm) of the OTA and comparator combination of RE and this large capacitor form a
relatively constant versus temperature. The circuit high-pass filter, enhancing the high frequency gain.
parameters listed in the specification table are Other cases may require an RC compensation
measured with RQ set to 300Ω, giving a nominal network in parallel to RE to optimize the
quiescent current at 13mA. While not always shown high-frequency response. The large-signal bandwidth
in the application circuits, this RQ = 300Ω is required (VO = 1.4VPP) measured at the emitter achieves
to get the 13mA quiescent operating current. 770MHz. The frequency response of the collector is
directly related to the resistor value between the
collector and GND; it decreases with increasing
resistor values, because of the low-pass filter formed
with the OTA C-output capacitance.

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Figure 35 shows a simplified block diagram of the While the OTA function and labeling appear similar to
OPA615 OTA. Both the emitter and the collector those of a transistor, it offers essential distinctive
outputs offer a drive capability of ±20mA for driving differences and improvements: 1) The collector
low impedance loads. The emitter output is not current flows out of the C terminal for a positive
current-limited or protected. Momentary shorts to B-to-E input voltage and into it for negative voltages;
GND should be avoided, but are unlikely to cause 2) A common emitter amplifier operates in
permanent damage. non-inverting mode while the common base operates
in inverting mode; 3) The OTA is far more linear than
a bipolar transistor; 4) The transconductance can be
+VCC adjusted with an external resistor; 5) As a result of
(13) the PTAT biasing characteristic, the quiescent current
increases as shown in the typical performance curve
vs temperature and keeps the AC performance
constant; 6) The OTA is self-biased and bipolar; and
7) The output current is approximately zero for zero
differential input voltages. AC inputs centered on zero
produce an output current centered on zero.

B E C
BASIC APPLICATION CIRCUITS
+1
(3) (2) (12) Most application circuits for the OTA section consist
of a few basic types which are best understood by
analogy to discrete transistor circuits. Just as the
transistor has three basic operating modes—common
emitter, common base, and common collector—the
OTA has three equivalent operating modes;
common-E, common-B, and common-C (see
Figure 36, Figure 37 and Figure 38). Figure 36 shows
+VCC the OTA connected as a Common-E amplifier, which
(5)
is equivalent to a common emitter transistor amplifier.
Input and output can be ground-referenced without
Figure 35. Simplified OTA Block Diagram any biasing. The amplifier is noninverting because a
current flowing out of the emitter will also flow out of
the collector as a result of the current mirror shown in
Figure 35.

V+

RB RL
12 VO
VO C
100Ω NoninvertingGain
VI 3 B OTA
Inverting Gain RL VOS ≈ 0
VI
VOS ≈ several volts E
2
RE
RB RE

V−
Single Transistor
(a) Common Emitter Amplifier (b) Common−E Amplifier for OTA
Transconductance varies over temperature. Transconductance remains constant over temperature.

Figure 36. a) Common Emitter Amplifier Using a Discrete Transistor; b) Common-E Amplifier Using the
OTA Portion of the OPA615

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Figure 37 shows the Common-C amplifier. It Figure 38 shows the Common-B amplifier. This
constitutes an open-loop buffer with low offset configuration produces an inverting gain, and the
voltage. Its gain is approximately 1 and will vary with input is low-impedance. When a high impedance
the load. input is needed, it can be created by inserting a
buffer amplifier (such as the BUF602) in series.

V+ 12
C V+
100Ω
3 B G≈1 RL RL
VI OTA G=− ≈ −
VOS ≈ 0 1 RE
RL RE +
E gm
VI
2
VO
VO
VO RE Noninverting Gain
G≈1 VOS ≈ several volts
(b) Common−C Amplifier for OTA 12 VO
RE VOS ≈ 0.7V
(Buffer) C Inverting Gain
100Ω
RE 3 B OTA VOS ≈ 0
1 ≈ 1 RL
G=
V− 1 E
1+ VI
Single Transistor gm x RE 2
(a) Common Collector Amplifier 1 Single Transistor
RO = RE
(Emitter Follower) gm (a) Common−Base
Amplifier
VI

(b) Common−B Amplifier for OTA

Figure 37. a) Common Collector Amplifier Using
a Discrete Transistor; b) Common-C Amplifier
Using the OTA Portion of the OPA615 Figure 38. a) Common Base Amplifier Using a
Discrete Transistor; b) Common-B Amplifier
Using the OTA Portion of the OPA615

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SAMPLING COMPARATOR The additional offset voltage or switching transient

induced on a capacitor at the current source output
The OPA615 sampling comparator features a very by the switching charge can be determined by the
short switching (2.5ns) propagation delay and utilizes following formula:
a new switching circuit architecture to achieve
excellent speed and precision. Charge (pC)
Offset (V) +
CHTotal (pF) (2)
It provides high impedance inverting and noninverting
analog inputs, a high-impedance current source The switching stage input is insensitive to the low
output and a TTL-CMOS-compatible Hold Control slew rate performance of the hold control command
Input. and compatible with TTL/CMOS logic levels. With
TTL logic high, the comparator is active, comparing
The sampling comparator consists of an operational the two input voltages and varying the output current
transconductance amplifier (OTA), a buffer amplifier, accordingly. With TTL logic low, the comparator
and a subsequent switching circuit. This combination output is switched off, showing a very high
is subsequently referred to as the Sampling impedance to the hold capacitor.
Operational Transconductance Amplifier (SOTA). The
OTA and buffer amplifier are directly tied together at
the buffer outputs to provide the two identical DESIGN-IN TOOLS
high-impedance inputs and high open-loop
Demonstration Fixture
transconductance. Even a small differential input
voltage multiplied with the high transconductance Two printed circuit boards (PCBs) are available to
results in an output current—positive or assist in the initial evaluation of circuit performance
negative—depending upon the input polarity. This using the OPA615. The demonstration fixture is
characteristic is similar to the low or high status of a offered free of charge as an unpopulated PCB,
conventional comparator. The current source output delivered with a user's guide. The summary
features high output impedance, output bias current information for this fixture is shown in Table 2.
compensation, and is optimized for charging a
capacitor in DC restoration, nanosecond integrators, Table 2. OPA615 Demonstration Fixtures
peak detectors and S/H circuits. The typical
comparator output current is ±5mA and the output ORDERING LITERATURE
bias current is minimized to typically ±10μA in the PRODUCT PACKAGE NUMBER NUMBER

sampling mode. OPA615ID SO-14 DEM-OPA-SO-1C SBOU039

OPA615IDGS MSOP-10 DEM-OPA-MSOP-1A SBOU042
This innovative circuit achieves the high slew rate
representative of an open-loop design. In addition, The demonstration fixture can be requested at the
the acquisition slew current for a hold or storage Texas Instruments web site (www.ti.com) through the
capacitor is higher than standard diode bridge and OPA615 product folder.
switch configurations, removing a main contributor to
the limits of maximum sampling rate and input Macromodel and Applications Support
frequency.
Computer simulation of circuit performance using
The switching circuits in the OPA615 use current SPICE is often a quick way to analyze the
steering (versus voltage switching) to provide performance of analog circuits and systems. This is
improved isolation between the switch and analog particularly true for video and RF amplifier circuits
sections. This design results in low aperture time where parasitic capacitance and inductance can have
sensitivity to the analog input signal, reduced power a major effect on circuit performance. A SPICE model
supply and analog switching noise. Sample-to-hold for the OPA615 is available through the TI web page
peak switching charge injection is 40fC. (www.ti.com). This model predicts typical small-signal
AC, transient steps, DC performance, and noise
under a wide variety of operating conditions. The
model includes the noise terms found in the electrical
specifications of the data sheet. However, the model
does not attempt to distinguish between package
types in their small-signal AC performance. The
applications department is also available for design
assistance.

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APPLICATION INFORMATION
The OPA615 operates from ±5V power supplies Power-supply bypass capacitors should be located as
(±6.2V maximum). Absolute maximum is ±6.5V. Do close as possible to the device pins. Solid tantalum
not attempt to operate with larger power supply capacitors are generally best. See Board Layout at
voltages or permanent damage may occur. the end of the applications discussion for further
suggestions on layout.
BASIC CONNECTIONS
Figure 39 shows the basic connections required for
operation. These connections are not shown in
subsequent circuit diagrams.

RB
(25Ω to 200Ω)
CHOLD

9 GND 4 3 Base

2
Emitter

Switching Stage OTA

(20Ω Hold 7
Control 12
to Collector
200Ω) Sampling Comparator
(SC)
S/H In+
10 IQ Adjust
SOTA ∞ Biasing 1
S/H In−
11
RQ = 300Ω sets approximately
RQ I Q = 13mA
13 5
+VCC −VCC
+5V −5V

+
2.2µF 10nF 470pF 470pF 10nF 2.2µF
+
Solid Tantalum

Figure 39. Basic Connections

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DC-RESTORE SYSTEM
Figure 40 and Figure 41 offer two possible HCL
DC-restore systems using the OPA615. Figure 41
implements a DC-restore function as a unity-gain
amplifier. As can be expected from its name, this 10
100Ω
7
DC-restore circuit does not provide any amplification.
SOTA
4 11
In applications where some amplification is needed,
consider using the circuit design shown in Figure 40.
12
CHOLD OPA615 100Ω
100Ω
OTA
3
HCL
VOUT
VIN 2
100Ω
7 10
4
SOTA
11
OPA615

CHOLD
12
100Ω Figure 41. DC Restoration of a Buffer Amplifier
100Ω
3 OTA
For either of these circuits to operate properly, the
2 VOUT source impedance needs to be low, such as the one
VIN R2
= VIN x
R1
provided by the output of a closed-loop amplifier or
R1 R2
buffer. Consider the video input signal shown in
Figure 42, and the complete DC restoration system
shown in Figure 40. This signal is amplified by the
OTA section of the OPA615 by a gain of:
Figure 40. Complete DC Restoration System R2
G+)
R1

100 89 70 59 41 30 11 0

W Y CY GRN MAG R BLU BLK

100

80
IRE UNITS

60

40
1VPP

20
10
40 IRE

7.5
0

−20
BACK PORCH
−40
BLANKING LUMINANCE + CHROMINANCE

FRONT PORCH
SYNC TIP
BREEZEWAY
COLOR BURST

Figure 42. NTSC Horizontal Scan Line

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The DC restoration is done by the SOTA section by When the SOTA is sampling, it is charging or
sampling the output signal at an appropriate time. discharging the CHOLD capacitor depending on the
The sampled section of the signal is then compared level of the output signal sampled. The detail of an
to a reference voltage that appears on the appropriate timing is illustrated in Figure 43.
non-inverting input of the SOTA (pin 10), or ground in
Figure 40.

100

80
IRE UNITS

60
Input Voltage

0V 40

20
10
7.5 0

−20

−40

Sample
HCL

Hold

100

80
IRE UNITS
Output Voltage

60

40

20
10
7.5 0
0V

−20

−40

Figure 43. DC-Restore Timing

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CLAMPED VIDEO/RF AMPLIFIER The external capacitor (CHOLD) allows for a wide
range of flexibility. By choosing small values, the
Another circuit example for the preamplifier and the
circuit can be optimized for a short clamping period or
clamp circuit is shown in Figure 44. The preamplifier
with high values for a low droop rate. Another
uses the wideband, low noise OPA656, again
advantage of this circuit is that small clamp peaks at
configured in a gain of +2V/V. Here, the OPA656 has
the output of the switching comparator are integrated
a typical bandwidth of 200MHz with a settling time of
and do not cause glitches in the signal path.
about 21ns (0.02%) and offers a low bias current
JFET input stage.
SAMPLE-AND-HOLD AMPLIFIER
With a control propagation delay of 2.5ns and
CHOLD
730MHz bandwidth, the OPA615 can be used
HCL advantageously in a high-speed sample-and-hold
100Ω
RE
7
amplifier. Figure 45 illustrates this configuration.
2 100Ω
11
VREF Hold /Track
4
OTA SOTA
3 10
OPA615
12 100Ω
R1 R2 150Ω OPA615 12
10 7
100Ω VIN 100Ω
300Ω 300Ω 4
SOTA OTA
50Ω 11 3
CHOLD
22pF 2 50Ω
CB OPA656 VOUT VOUT
300Ω
• Current Control
VIN RB • Non−Inverting 300Ω

Figure 44. Clamped Video/RF Amplifier Figure 45. Sample-and-Hold Amplifier

The video signal passes through the capacitor CB, To illustrate how the digitization is realized in the
blocking the DC component. To restore the DC level Figure 45 circuit, Figure 46 shows a 100kHz
to the desired baseline, the OPA615 is used. The sinewave being sampled at a rate of 1MHz. The
inverting input (pin 11) is connected to a reference output signal used here is the IOUT output driving a
voltage. During the high time of the clamp pulse, the 50Ω load.
switching comparator (SOTA) will compare the output
of the op amp to the reference level. Any voltage
1MHz SAMPLE−AND−HOLD OF A 100kHz SINEWAVE
difference between those pins will result in an output 5
current that either charges or discharges the hold 4
capacitor, CHOLD. This charge creates a voltage Hold−and−Track Signal (V)
3
across the capacitor, which is buffered by the OTA.
Output Voltage (V)

2
Multiplied by the transconductance, the voltage will
1
cause a current flow in the collector, C, terminal of
+2.5 0
the OTA. This current will level-shift the OPA656 up
+1.5
to the point where its output voltage is equal to the
+0.5
reference voltage. This level-shift also closes the
−0.5
control loop. Because of the buffer, the voltage
−1.5
across the CHOLD stays constant and maintains the
−2.5
baseline correction during the off-time of the clamp Time (1µs/div)
pulse.

Figure 46. 1MHz Sample-and-Hold of a 100kHz

Sine Wave

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Integrator for ns-Pulses Phase Detector for Fast PLL Systems

The integrator for ns-pulses using the OPA615 Figure 49 shows the circuit for a phase detector for
(shown in Figure 47) makes use of the fast fast PLL systems. Given a reference pulse train fREF
comparator and its current-mode output. Placing the and a pulse train input signal fIN out of phase, the
hold-control high, a narrow pulse charges the SOTA of the OPA615 acts in this circuit as a
capacitor, increasing the average output voltage. To comparator, either charging or discharging the
minimize ripples at the inverting input and maximize capacitor. This voltage is then buffered by the OTA
the capacitor charge, a T-network is used in the and fed to the VCO.
feedback path.

Hold Control

OPA615 12
150Ω 11
10 7 12 fR EF 100Ω
VIN 100Ω OTA
4 SOTA
SOTA OTA 10 4 3
11 3 f IN
50Ω 27pF 7 75Ω
C IN T 2
2 50Ω VO UT
VOUT 75Ω 75Ω
+5V
620Ω 820Ω

1µF
f IN
√N
fO UT
fR EF
Figure 47. Integrator for ns-Pulses fIN
VCO

VOU T
Fast Pulse Peak Detector I OU T
Phase

A circuit similar to that shown in Figure 47 (the

fR EF
integrator for ns-pulses) can be devised to detect and VOU T
isolate positive pulses from negative pulses. This
fO UT = f RE F x N
circuit, shown in Figure 48, uses the OPA615 as well
as the BUF602. This circuit makes use of diodes to
isolate the positive-going pulses from the
negative-going pulses and charge-different
capacitors.
Figure 49. Phase Detector For Fast PLL-Systems

Hold Control 100Ω 50Ω

+1 −VOUT
4 8

27pF BUF602
100Ω

150Ω 12
10 7
VIN 100Ω
4
SOTA OTA
50Ω 11 3

27pF 2 50Ω
OPA615 +VOUT

300Ω

Figure 48. Fast Bipolar Peak Detector

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CORRELATED DOUBLE SAMPLER The signal coming from the CCD is applied to the two
sample-and-hold amplifiers, with their outputs
Noise is the limiting factor for the resolution in a CCD connected to the difference amplifier. The timing
system, where the kT/C noise is dominant (see diagram clarifies the operation (see Figure 52). At
Figure 51). To reduce this noise, imaging systems time t1, the sample and hold (S/H1) goes into the hold
use a circuit called a Correlated Double Sampler mode, taking a sample of the reset level including the
(CDS). The name comes from the double sampling noise. This voltage (VRESET) is applied to the
technique of the CCD charge signal. A CDS using noninverting input of the difference amplifier. At time
two OPA615s and one OPA694 is shown in t2, the sample-and-hold (S/H2) will take a sample of
Figure 50. The first sample (S1) is taken at the end of the video level, which is VRESET – VVIDEO. The output
the reset period. When the reset switch opens again, voltage of the difference amplifier is defined by the
the effective noise bandwidth changes because of the equation VOUT = VIN+ – VIN–. The sample of the reset
large difference in the switch RON and ROFF voltage contains the kT/C noise, which is eliminated
resistance. This difference causes the dominating by the subtraction of the difference amplifier.
kT/C noise essentially to freeze in its last point.
The double sampling technique also reduces the
The other sample (S2) is taken during the video white noise. The white noise is part of the reset
portion of the signal. Ideally, the two samples differ voltage (VRESET) as well as of the video amplitude
only by a voltage corresponding to the transferred (VRESET – VVIDEO). With the assumption that the noise
charge signal. This is the video level minus the noise of the noise of the second sample was unchanged
(ΔV). from the instant of the first sample, the noise
The CDS function will eliminate the kT/C noise as amplitudes are the same and are correlated in time.
well as much of the 1/f and white noise. Therefore, the noise can be reduced by the CDS
function.
Figure 52 is a block diagram of a CDS circuit. Two
sample-and-hold amplifiers and one difference
amplifier constitute the correlated double sampler.

VHOLD1

100Ω 12
10 7
VIN1 100Ω 402Ω
3
SOTA OTA
50Ω 11 4
27pF
402Ω
2
300Ω
402Ω OPA694 VOUT

300Ω
402Ω
VHOLD2

100Ω 12
10 7
VIN2 100Ω
3
SOTA OTA
50Ω 11 4
27pF
2
300Ω

300Ω

Figure 50. Correlated Double Sampler

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Simplified CCD Output Signal

S1

kT/C −Noise PP

Reset Level ∆V

S2

Video Level

NOTE: Signals are out of scale.

Figure 51. Improving SNR with Correlated Double Sampling

VRESET
S/H1

VIN VOUT = VIN+ − VIN−

S/H2 Difference
VRESET − VVIDEO Amplifier
t2 t1
Video Hold Reset Hold

VIN
S1

t1
S2
t2

0V
Video Out

Figure 52. CDS: Circuit Concept

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BOARD LAYOUT GUIDELINES d) Connections to other wideband devices on the

board may be made with short direct traces or
Achieving optimum performance with a high- through onboard transmission lines. For short
frequency amplifier such as the OPA615 requires connections, consider the trace and the input to the
careful attention to printed circuit board (PCB) layout next device as a lumped capacitive load. Relatively
parasitics and external component types. wide traces (50mils to 100mils) should be used,
Recommendations that will optimize performance preferably with ground and power planes opened up
include: around them.
a) Minimize parasitic capacitance to any AC e) Socketing a high-speed part such as the
ground for all of the signal I/O pins. Parasitic OPA615 is not recommended. The additional lead
capacitance on the output and inverting input pins length and pin-to-pin capacitance introduced by the
can cause instability; on the non-inverting input, it can socket can create an extremely troublesome parasitic
react with the source impedance to cause network which can make it almost impossible to
unintentional bandlimiting. To reduce unwanted achieve a smooth, stable frequency response. Best
capacitance, a window around the signal I/O pins results are obtained by soldering the OPA615 directly
should be opened in all of the ground and power onto the PCB.
planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on the
board. INPUT AND ESD PROTECTION
The OPA615 is built using a very high-speed,
b) Minimize the distance (< 0.25") from the power
complementary bipolar process. The internal junction
supply pins to high frequency 0.1μF decoupling
breakdown voltages are relatively low for these very
capacitors. At the device pins, the ground and power
small geometry devices. These breakdowns are
plane layout should not be in close proximity to the
reflected in the Absolute Maximum Ratings table
signal I/O pins. Avoid narrow power and ground
where an absolute maximum ±6.5V supply is
traces to minimize inductance between the pins and
reported. All device pins have limited ESD protection
the decoupling capacitors. The power-supply
using internal diodes to the power supplies, as shown
connections should always be decoupled with these
in Figure 53.
capacitors. An optional supply-decoupling capacitor
across the two power supplies (for bipolar operation)
will improve 2nd-harmonic distortion performance. +VCC
Larger (2.2μF to 6.8μF) decoupling capacitors,
effective at a lower frequency, should also be used
on the main supply pins. These may be placed External Internal
somewhat farther from the device and may be shared Pin Circuitry
among several devices in the same area of the PCB.
c) Careful selection and placement of external −VCC
components will preserve the high frequency
performance of the OPA615. Resistors should be a
very low reactance type. Surface-mount resistors Figure 53. Internal ESD Protection
work best and allow a tighter overall layout. Metal-film
and carbon composition, axially-leaded resistors can These diodes also provide moderate protection to
also provide good high frequency performance. input overdrive voltages above the supplies. The
Again, keep these leads and PCB trace length as protection diodes can typically support 30mA
short as possible. Never use wirewound-type continuous current. Where higher currents are
resistors in a high frequency application. Other possible (for example, in systems with ±15V supply
network components, such as noninverting input parts driving into the OPA615), current-limiting series
termination resistors, should also be placed close to resistors should be added into the two inputs. Keep
the package. these resistor values as low as possible since high
values degrade both noise performance and
frequency response.

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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (August 2008) to Revision E ................................................................................................ Page

• Corrected y-axis title of Figure 25 ....................................................................................................................................... 10

Changes from Revision C (October 2006) to Revision D ............................................................................................... Page

• Changed rating for storage temperature range in Absolute Maximum Ratings table from –40°C to +125°C to –65°C
to +125°C .............................................................................................................................................................................. 2
• Clarified hold control pin voltage rating in Absolute Maximum Ratings table ....................................................................... 2

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Product Folder Link(s): OPA615

 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

OPA615ID ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA615ID
& no Sb/Br)
OPA615IDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 BJT
& no Sb/Br)
OPA615IDGST ACTIVE VSSOP DGS 10 250 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 BJT
& no Sb/Br)
OPA615IDR ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA615ID
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-May-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA615IDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA615IDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA615IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 1-May-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA615IDGSR VSSOP DGS 10 2500 367.0 367.0 35.0
OPA615IDGST VSSOP DGS 10 250 210.0 185.0 35.0
OPA615IDR SOIC D 14 2500 367.0 367.0 38.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DGS0010A SCALE 3.200
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
TYP SEATING PLANE
4.75

A PIN 1 ID 0.1 C
AREA

8X 0.5
10
1

3.1
2.9 2X
NOTE 3 2

5
6
0.27
10X
0.17
3.1 0.1 C A B 1.1 MAX
B
2.9
NOTE 4

0.23
TYP
SEE DETAIL A 0.13

0.25
GAGE PLANE

0.7 0.15
0 -8 0.05
0.4

DETAIL A
TYPICAL

4221984/A 05/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.

www.ti.com
 EXAMPLE BOARD LAYOUT
DGS0010A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

10X (1.45)
10X (0.3) SYMM (R0.05)
1 TYP
10

SYMM

8X (0.5) 5 6

(4.4)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221984/A 05/2015
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
DGS0010A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

10X (1.45)
SYMM (R0.05) TYP
10X (0.3)
1
10

SYMM
8X (0.5)

5 6

(4.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:10X

4221984/A 05/2015
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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