Balanced Amplifier Layout

BALANCED AMPLIFIER LAYOUT
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DESIGN OVERVIEW
The purpose of this example is to demonstrate the many features of the Micro-
wave Office layout tool. The example will start with a circuit already designed
electrically and then go through the process to create the finalized layout. Since
practical circuit design is not a process where all of the electrical modeling is
done before any of the layout, the intermediate layout steps will be demon-
strated. This example will emphasize how to set up the tool to efficiently create
the layout. This document will describe a basic reasoning for each step and then
show the exact commands to perform the step. This example assumes that the
user has a basic understanding of how Microwave Office works. If you do not
have a working knowledge of Microwave Office, please refer to the Quick Start
Guide before going through this application note. Additionally, AWR projects
are included with this application note with the progress saved at various points.
Ideally, you will build this design as you go, but if you need to get to a known
good point, you can use the provided examples.
The design to be implemented is a balanced amplifier from 8 to 10 GHz. The
technology being used is NEC 76038 packaged devices assembled on a 25 mil
alumina substrate. The resolution of the masking process for the alumina is 0.1
mil. The alumina process chosen allows thin-film resistors with a sheet resis-
tance of 100 Ω/square. The metal deposition is 0.15 mil gold. Vias are created
with a fixed diameter of 25 mils with the sidewalls of the vias covered with 0.15
mils of gold. ATC 500 and ATC 700B series capacitors are available for this
design. The entire circuit area is limited to one square inch.
Microwave Office 1
Electrical Performance of the Balanced Amplifier
ELECTRICAL PERFORMANCE OF THE BALANCED

AMPLIFIER
The simulated performance for the balanced amplifier is shown in Figure 1.
This graph is used for the sole purpose of demonstrating that the example about
to be demonstrated is for a circuit that has reasonable performance. The gain is
approximately 7 dB and the return loss is less than -10 dB across the band for
the completed circuit.
Balanced Amplifier Response

10
-10
-20
-30
6 8 10 12
Frequency (GHz)
Gain Input Return Loss Output Return Loss
Figure 1. Circuit Gain and Return Loss
LAYOUT SETUP
Before beginning any sort of layout with Microwave Office, a little time spent
setting up for layout will save time and eliminate confusion as the layout gets
more complicated. This involves configuring the layout units, the layout grid,
the draw layers, the layer mapping, the 3D properties, and the line types to be
used in the layout. Once this setup is done for a particular process, the process
2 Microwave Office
Layout Setup
information can be saved and applied to other designs. Therefore, this setup
process only needs to be done once for a particular process.
Layout Units
The first step when creating a layout is to specify the drawing units to be used.
Metric or english units can be used. Since this design will be implemented on a
thick substrate, it will be easier to do all the layout in mils (0.001 inches), espe-
cially since 50 ohm transmission lines on 25 mil alumina are 25 mils wide.
To set the drawing units:
1. Choose Options > Project Options and click the Global Units tab.
2. Clear the Metric Units check box and set the Length type to mils, then
click OK.
These settings are shown in Figure 2.
Figure 2. Project Options dialog box / Global Units
Grid Setup
For the Balanced Amplifier circuit, the drawing units are set to mils and the pro-
cess being used can resolve down to 0.1 mils. Therefore, the database unit size is
Application Notes 3
Layout Setup
set to 0.1 mils and the grid spacing is set to 1 mil. By using the grid snap multi-
ple, the grid spacing can be adjusted down to 0.1 mils or up to 10 mils.
To specify the grid settings,
1. Choose Options > Layout Options and click the Layout tab.
2. Change the Grid spacing to be 1 mil and the Database unit size to be 0.1
mil and click OK.
These settings are shown in Figure 3.
Figure 3. Layout Options dialog box / Layout
Draw Layers
Microwave Office has several default draw layers required to display various fea-
tures of the layout tool. These default layers are shown in Figure 4.
The rest of the draw layers necessary for this layout need to be added to the
draw layers list. For this process, the following layers are needed to complete
the layout: Tline (gold lines on the substrate), Via (via hole location to the back-
side of the substrate), TFR (thin-film resistor on the substrate), Substrate (out-
line of the substrate dimensions), Device Package (outline of the package for the
device), Device Leads (connections leading into the device package), Chip Foot-
print (outline of the chip components, capacitors for this design), and Chip
Connections (metal connections on the chip components).
4 Microwave Office
Layout Setup
Figure 4. Default Drawing Layers
Default settings are loaded when you first open Microwave Office, so there will
most likely be many layers besides the default layers already set up. The simplest
way to create the layers for a new process is import a Layout Process File (LPF)
that has the minimal layers configured and then add layers. This file is the
Blank.lpf shipped with AWR software.
To import the Blank.lpf:
1. Choose Project > Process Library > Import LPF.
2. Browse to the root AWR directory (the directory where AWR was installed).
3. Select the Blank.lpf file and select Open.
To delete and add draw layers:
1. Make the Layout Manager visible by clicking the Layout tab in the bottom
left of the project.
2. Double-click on the name of the LPF file under the Layer Setup box in the
top of the Layout Manager or choose Options > Drawing Layers and click the
Drawing Layer 2D node under the General folder.
Application Notes 5
Layout Setup
3. To delete a layer, click on the name of the layer to delete and click the Delete
button.
4. To add a layer, click the New Layer button. A new layer will appear below
the selected layer.
5. Once a new layer is created, all of the properties are changed by clicking on
the property column. The Drawing Layer name can be typed to change the
name. Clicking over the Line or Fill boxes will allow a new color and line type
of fill pattern to be chosen. Clicking over the Visible, Cloak, Show Fill, or
Freeze box will toggle the setting.
Figure 5. Added Draw Layers
The necessary draw layers needed for the balanced amplifier layout are shown
set up in Figure 5. The new layers are added below the default layers.
Note that the substrate layer has it’s fill turned off. This is so that the fill pattern
will not cover up all the layout objects inside the substrate layer in the finished
layout.
Also the system layers are Cloaked which means they will draw in a layout the
layers will not be available to select when editing layout.
You can export these settings to keep for future reference or to apply them to a
different design. In Microwave Office, the process definitions are stored in a
Layout Process File (LPF) and use the .lpf extension.
6 Microwave Office
Layout Setup
To export the LPF choose Project > Process Library > Export LPF, specify
the name and location, and then click Save.
Layer Mapping
Layer Mapping is used to allow all the drawing in Microwave Office to be done
with the draw layers defined in the previous section. Model layers are used to
store the layer information for files imported into the tool. When an layout file
(GDSII or DXF) file is imported, a new model layer is created for every layer in
the layout file that does not already have a model layer defined. The layer map-
ping is used to assign any draw layer to every model layer. For a given layer
mapping table, each model layer will be assigned one draw layer. The draw lay-
ers can be assigned to zero, one, or multiple model layers. This mapping allows
all imported layout files, that can have any layer names (DXF) or numbers
(GDSII), to be displayed Microwave Office with the user-defined draw layers.
For more information on model layers and layer mapping, please see the layout
chapter of the Microwave Office User Guide. Also, the steps below will make these
concepts more clear.
The default settings loaded when you first open Microwave Office will also have
pre-existing layer mapping tables. The best way to create the tables you want is
to delete existing tables and create your own.
To delete and add layer mapping tables:
1. Double-click on the LPF name under the Layer Setup node in the top of the
Layout Manager.
2. Find the mapping tables under the Model Layer Mappings folder.
3. To delete a mapping table, right click on the mapping table and select Delete
<name>, where <name> is the name of the file.
4. To add a mapping table, right click on the Model Layer Mappings folder
and select New Model Layer Mapping.
5. To change the draw layer assigned to each model layer, click in the Drawing
Layers column, and select the draw layer from the drop down list.
When creating a new layer mapping file, a model layer is created for each draw
layer defined and each layer that is present in the imported layout files. For this
example, the layer mapping generated from the new mapping command is all
that is needed for now. The user could add model layers and assign draw layers
for all of the layers in the files that are planned on being imported, if the
Application Notes 7
Layout Setup
imported layer names or numbers are known. Another technique is to adjust the
draw layers and layer mapping after artwork files are imported. This example
will demonstrate both techniques in later sections.
The initial layer mapping is shown in Figure 6 in a file mapping called “NEC
Package”. This figure shows that mapping is necessary for the default layers as
well as the user-defined layers. It is possible to set up multiple file mappings if
necessary. The draw layer and file mapping will be re-visited when layout files
are imported.
Figure 6. Initial File Mapping Entries
3D Properties
In order to properly view a 3D layout in Microwave Office, the 3D properties
of the layout must first be setup. All this entails is setting how thick each layer is
and where along the z axis the layer starts for each draw layer. This should only
be done for the draw layers that will have physical meaning in the circuit (do not
setup default layers). For this example, the reference height will be the top of
the substrate. The Via and the Board Outline draw layers will have a z-position
of -25 and a thickness of 25. The Board Outline is set to draw as opaque (fill
turned off). Since the Board Outline layer covers the entire circuit, if is not
drawn as opaque, its drawing will cover the other drawing objects. The rest of
the layers will have a positive z-position and then the physical thickness of that
8 Microwave Office
Layout Setup
draw layer. Note that the units for the settings here are the global setting for
length (mils in this example).
To set the 3D properties:
Layout Manager and click the Drawing Layer 3D node under the General tab.
2. Enter the Thickness and Z-Position values in their corresponding boxes.
3. Toggle the Opaque option to be unchecked if you do not want that layer to
have a fill pattern. Note, the fill patterns in the Draw Layers section do not
apply for the 3D layout, the 3D fills are solid.
Figure 7. 3D Properties Entries
The completed setup is shown in Figure 7.

It is important to get the z-position correct to eliminate gaps in the 3D layout.
For example, the z-position of the Chip Footprint is set to 1.15 because it will be
sitting on top of the Tline (0.15 mils thick) and the Chip Connections (1 mil
thick).
EM Layer Mapping
Microwave Office provides its own integrated EM solver in the design environ-
ment. To enable copying and pasting between an EM layout and a circuit layout,
Application Notes 9
Layout Setup
the EM Layer Mapping must be set up. This mapping table specifies how to
map draw layers to the proper dielectric layer in the dielectric stack, which mate-
rial to create the layer with (gold, resistor, etc.) and whether or not the layer is a
via. This mapping is also used to display an EM layout on the proper draw layers
in a layout that has an EM structure as a subcircuit.
For this example, only the Tline, TFR, and the Via draw layers need to be
mapped to the EM simulator since these will be the only layers that need any
sort of EM simulation. The proper material types need to be set up for the
mapping to go smoothly, one for the Tline as 0.15 mil gold, and one for the
resistor, 100 Ω/square.
These material types will be added when an EM structure is generated. For now,
lets assume we have already decided the EM material types to be gold and
resistor.
To set the EM sight mapping:
Layout Manager.
2. Find EM Layer Mapping folder to see the EM mapping tables configured.
3. Enter the EM dielectric layer number for each draw layer that will be copied
into the EM simulator. Click the Is Via box if the layer should be modeled as a
via. Type in the name of the material the draw layer will be mapped to. If left
blank, the material will be perfect conductor.
Remember that the top layer of the EM structure is layer 1. So for a microstrip
configuration, like this example, with no other dielectric layers, the microstrip
elements and vias to ground will map to layer 2. The EMSight mapping is
shown in Figure 8.
In later sections when layout is copied from a schematic layout to the EM editor,
the shapes in EM will be correct due to the mapping created here.
10 Microwave Office
Layout Setup
Figure 8. EM Sight Mapping Setup
The LPF file should be exported after all the mapping is done to make some
final changes that can only be made by editing the LPF file in a text editor.
To export the LPF choose Project > Process Library > Export LPF, specify
the name and location, and then click Save.
Line Type Setup

When Microwave Office draws parameterized elements, such as microstrip,
stripline or coplanar lines, the user can specify what layers are used to draw these
elements. This is done by editing the .lpf file using any text editor. If changes are
made using the Layer Setup dialog box (all the layer steps above used this), the
.lpf file must be exported before any editing to this file is done. A block is
added to the .lpf file for each line type the user wants to define. See the Micro-
wave Office User Guide for more information on setting up the .lpf file. For the
balanced amplifier circuit, only one line type is needed and it will be drawn on
Application Notes 11
Layout Setup
the TLine layer and the line type will be called “Gold Line”. The entries in the
.lpf file are shown in Figure 9.
Figure 9. Line Type for Transmission Line called “Gold Line”
After this change is made, the .lpf will need to be imported back into the design
for the changes to take effect.
To import a .lpf file choose Project > Process Library > Import LPF, locate
the .lpf file to import, and then click Open .
Via Drawing Setup

A via is a special type of parameterized element when it comes to creating its
layout cell. The layout for the via electrical model has it’s own definition area in
the .lpf file and only one via type is currently allowed. Note that when the lpf is
imported with a change to the via definition, all vias in layout will reflect the
changes. The same is true for any other layout objects that reference the lpf file.
For the balanced amplifier circuit, the via will be a 25 mil circle with a square
pad extended 5 mils (.000127 meters) from the center circle. The connection
faces will be set to the outer edge of the via. The diameter will be set in the elec-
trical model but the multi-layer drawing is set up in the .lpf file. The entries in
the .lpf file are shown in Figure 10
Figure 10. Via Drawing Definition
The flags settings specify that the drawing on the “Via” layer will be a circle with
cell ports (location where other elements connect to the via) at the outside edge
of the structure (different flag setting could set the cell ports to the center of the
via). The settings for the “TLine” specify a square drawing with the cell ports
at the outside edge of the structure. Again, the .lpf will need to be imported
back into the design for the changes to take effect. Please see the layout chapter
of the Microwave Office User Guide for more information on setting up the via
definition.
12 Microwave Office
Circuit Layout
The progress this far is saved in a project called After_setup.emp.
CIRCUIT LAYOUT
At this point the project is setup properly for layout in this particular process. It
is now time to bring in the necessary layout files that will be needed. Then the
circuit will be ready to bring the layout together.
Import Device Package Artwork

The device for this design is the NEC 76038. The design uses a provided s-
parameter data file for the device electrical performance (file called
“N76038a.s2p”). Along with the s-parameters is a GDSII layout file containing
the physical dimensions of the device package (file called “nec_packages.gds”).
This step will bring in the artwork for the packaged device, adjust the draw lay-
ers and mapping files so this imported file will be consistent with the pre-
defined draw layers, and add cell ports to the layout.
To import a GDSII library:
1. Make the Layout Manager visible by clicking the Layout tab in the bottom
left of the project.
2. Right-click on the Cell Libraries node in the Layout Manager and choose
Read GDSII Library.
3. Locate the GDSII cell library and click Open .

4. A dialog will open telling you there are unmapped layers that must be created,
click OK.
The imported artwork is shown in Figure 11.
For this GDSII cell library, the GDSII layers for the package were not known
before it was imported so no layer mapping was set up prior to the file import.
Therefore, new model layers and new draw layers were created by the software
for all the layers in the GDSII file. This can be seen in Figure 11 in the lower left
panel. It shows that both the model and draw layers are not names that were
previously defined. The format for imported GDSII files is to make model lay-
ers with the format “layer_datatype”. So this GDSII library had drawing shapes
on layer 1 and data type 0 (1_0) and layer 2 and data type 0 (2_0). Since these
Circuit Layout
model layers were not previously defined, they were automatically created as
model and draw layers.
Figure 11. Imported NEC 76038 Package Artwork

In the setup, draw layers have already been created to display the device, so the
layer mapping and draw layer sections need to be edited to make use of the
defined draw layers. The first step is to assign the new model layers (1_0, 2_0)
to the draw layers previously defined. Layer 1_0 is the device package and
should be mapped the “Device Package” draw layer. Layer 2_0 is the device
leads layer and should be mapped to the “Device Leads” draw layer. The sec-
ond step is to delete the new draw layers created since they won’t be needed
once the correct layer mapping is set up.
To edit layer mapping tables:
Layout Manager, click the mapping tables under the Model Layer Mappings
folder.
2. Find the model layer in the left column to change and click in the right col-
umn to activate a drop down list of available draw layers
14 Microwave Office
Circuit Layout
3. Select the appropriate draw layer from the drop down list.
4. Click OK when all the desired changes have been made.
Once the new model layers have been mapped to the correct draw layers, the
lower left panel of the Layout Manager will display these changes as seen in
Figure 12. Notice that the imported model layers now map to the proper draw
layers.
Now that the new model layers are correctly mapped to the desired draw layers,
the new draw layers created when the file was imported can be deleted.
To delete draw layers:
1. Double-click on the Layer Setup box in the top of the Layout Manager and
click the Draw Layers tab.
2. Click on the draw layer name and click Delete Layer.
3. When the desired layers are deleted, click OK.
Figure 12. Imported NEC 76038 package Artwork with Adjusted Model Layers
Circuit Layout
The final step to be able to use this artwork cell as the layout for a schematic ele-
ment is to add cell ports to the layout. Cell ports determine how layout cells
hook together. When changing the layout representation for a schematic ele-
ment, only layouts with the same number of cell ports as the element nodes can
be chosen. For example, a FET has three nodes (source, gate, and drain) so the
layout to be assigned to a FET can only have three numbered cell ports. It is
possible to draw four cell ports on a layout but only have three numbered cell
ports by assigning two of the drawn cell ports the same number. When doing
layout, the cell port number will correspond to the schematic element node
number. This concept will be demonstrated with this layout example.
For the NEC packaged device, the package has four leads. One is for the gate,
one is for the drain, and two are for the source. For this device to hook up cor-
rectly, the gate lead will have cell port 1, the drain will have cell port 2, and both
of the source leads will have cell port 3. The numbers were referenced off of
the FET symbol since the s-parameter file block used to model the device was
changed to have a FET symbol in the circuit schematics. For more information
on changing the symbol for schematic elements, please see the Microwave Office
User Guide. The s-parameter file for this device is referenced to the junction
between the leads and the package, so this is the location where the cell ports
should be drawn.
To add a cell port to a layout:
1. Open the artwork cell by double-clicking on the cell in the top left pane of the
Layout Manager.
2. Choose Draw > Cell Port or click the Cell Port drawing tool on the Cell Edit
Draw Tools toolbar.
3. If your Draw Tools toolbar is not visible, right click over the toolbars in the
environment, and click next to the Cell Edit Draw Tools.
4. Right-click and hold at the first location of the cell port. Holding down the
Ctrl key will snap the curser to shape edges or intersections to help align the
port locations.
5. Drag the curser to the final port location. Holding down the Ctrl key will
help snap to the final location of the cell port.
16 Microwave Office
Circuit Layout
6. Note, the arrow direction for the cell port will always be in a “right-hand
rule” direction. Put your right hand in the direction that the line is drawn with
your thumb on top, then the way you can curl your fingers is the side the cell
port arrow will be placed.
The direction that the cell port arrow is facing is important since it specifies
how adjacent components attach to the cell port. Most likely, the cell port
arrow should face away from the center of the artwork cell. You may have to
zoom in to see the direction of the cell port.
For the NEC package, the first step is to draw the cell ports on all of the leads of
the device with all the cell port arrows facing outwards and located at the junc-
tion of the package and the leads. Figure 13 shows the device package artwork
cell after the cell ports were added. The fill has been turned off for the device
leads to better show the cell ports. Text is added to show the cell port numbers
for each port.
Figure 13. Initial Cell Port Locations and Numbers
Note that the port numbers were added sequentially starting on the left. The
cell ports are not numbered correctly as placed. Cell port 1 is correct since it is
the gate of the device. Cell port 3 needs to be changed to cell port 2 for the
drain of the device. Cell ports 2 and 4 need to be changed to 3 for the source of
the device.
Circuit Layout
To change cell port numbers:

1. Click on cell port in the artwork cell editor.
2. Right-click and choose Shape Properties and select the Cell Port tab.
3. Enter the correct number in the Port Number box and click OK.
Note that the cell port numbers must be numbered sequentially starting with 1.
Figure 14 shows the device package with the cell ports numbered correctly.
Figure 14. Final Cell Port Locations and Numbers
Bringing in Chip Capacitor Artwork

One of the chip capacitors needed for this design is a 500 series surface mount
capacitor from ATC. At the time of this design, this capacitor series was not
available as a library element in Microwave Office. The s-parameters for the
chip capacitor and the artwork file were available from ATC. The s-parameter
file is used to model the capacitor (file called “500S100.S2P”) and the GDSII
artwork (file called “atc_500_footprint.gds”) is used as the layout representation
for the capacitor. Only a 10 pF capacitor is used from this line of capacitors.
The artwork cell needs to be imported into the project to be used in the layout.
This is done in the same manner as the NEC device package was done. The
only difference is that this time, the GDSII layers are known and will be setup
18 Microwave Office
Circuit Layout
before import. This will eliminate the editing to the model and draw layers after
the file import. For this GDSII file, the chip capacitor gold connections are on
layer 1 and the footprint for the capacitor is on layer 3. A new layer mapping
table will be required to properly display these capacitors since layer 1 in the 500
ATC GDSII file is the chip connection and layer 1 in the NEC file was the
device package. If the NEC Package mapping is used, the chip connections for
the capacitors would improperly be displayed on the device package draw layer.
The first step is to create a new mapping table for the 500 series ATC capaci-
tors.
To create a new layer mapping table:
1. Open the layer setup dialog and click the Model Layer Mappings folder.
2. Right click the Model Layer Mappings folder and select New Model Layer
Mapping, and type in the name of the new map
3. When a new layer mapping is created, a copy of the first mapping table is cre-
ated.
4. Make changes to the model layers and the assigned draw layers in the new
layer mapping and click OK.
Now that the new layer mapping has been created, the proper model layers must
be created (if not already available) and assigned to the proper draw layers. A
model layer 1_0 was already established in the “NEC Package” layer mapping.
For the 500 ATC capacitor layout, this model layer needs to be mapped to the
“Chip Connections” layer, not the “Device Package” layer. The outline of the
chip capacitor is drawn on layer 3 with data type 0. Therefore a new model layer
called 3_0 needs to be created.
To create a new model layer:
1. On the layer mapping you are editing.
2. Click the New Layer button on the right.
3. Type in the name of the new model layer created.
Once model layer 3_0 is created it needs to be assigned to the “Chip Footprint”
draw layer.
The new mapping table, called "ATC 500", has the ATC GDSII layers mapped
to the proper draw tables as is shown in Figure 15. The only change from "NEC
Package" mapping is that model layer "1_0" is mapped to draw layer "Chip Con-
nections" rather than "Device Package".
Circuit Layout
Figure 15. Mapping Table for ATC 500 Capacitors
The layer mapping property for the 500 series ATC capacitor layout cell will be
set later when a layout is created from a schematic with the ATC capacitor.
Now that all the layer mapping is set up, the next step is to import the GDSII
library. The steps to do this were covered for the NEC package and won’t be
covered here again.
Cell ports must again be assigned to the chip capacitor as was done for the NEC
package layout. The chip capacitor with the cell ports is shown in Figure 16.
One thing to note when editing the capacitor layout in the artwork editor, the
layer mapping used is always the first layer mapping if there are multiple layer
mappings defined. Since these artwork files are stored in their original format
(GDSII or DXF), please pay attention to the model layers when editing cells.
Note from this figure that the "NEC Package" layer mapping is used by the pro-
gram when editing this layout cell because layer 1_0>Device Package,
2_0>Device Leads, and 3_0>Chip Footprint, are visible in the lower left win-
dow of the Layout Manager. It is VERY important to realize that this is only
while editing the layout cell. The draw layers will be viewed correctly when the
circuit is viewed in the layout editor and the correct file mapping is set for the
ATC capacitor. This will be properly demonstrated in later sections.
20 Microwave Office
Circuit Layout
Figure 16. ATC 500 Series Capacitor with Cell Ports Attached for 10 pF Capacitor
The second type of chip capacitors needed for this design is a 700B series sur-
face mount capacitor from ATC. Microwave Office has a library for these
capacitors but the discussion of the libraries will be skipped for this example.
This capacitor will be modeled with the ‘Chipcap” model with the proper
parameter values. In this design, only a 100 pF capacitor is used, so the proper
“Chipcap” settings are: C=100 pF, Q=292, FQ=0.15 GHz, FR=0.62 GHz, and
Alpha=1. Please see the help pages for a description of each parameter value.
The layout for this capacitor is again stored in a GDSII (file called “atc.gds”) for
the standard ATC parts.
For the GDSII file for the 700B series capacitors, the chip footprint is located
on layer 10 and the chip connections are on layer 11. There is other information
in this file on layer 1, 12 and 13. The first step again is to create new model lay-
ers for these layers. The new model layers will be 10_0, 11_0, 12_0, and 13_0.
These model layers can be added in either layer mapping already created since a
new model layer is added to all mapping tables. Also, since layers 1,12 and 13
Circuit Layout
won't be used, a new draw layer called “unused” is created and is set up to not
display objects drawn on this layer.
Once the new layers are set up, a new mapping table called "ATC 700B" is cre-
ated. The only layers that will need new mapping entries for this mapping table
are the layers in this GDSII file (layer 1,10,11,12, and 13). Layer 1_0, 12_0, and
13_0 are mapped to the “unused” layer since this information is not needed.
Layer 10_0 is mapped to the “Chip Footprint” draw layer and layer 11_0 is
mapped to the “Chip Connections” draw layer. Layers 2_0 and 3_0 can remain
mapped to any layer since these layers are not used in the ATC 700B layout
library. This new layer mapping table is shown in Figure 17.
For these cells, the cell ports are already drawn so they do not need to be added.
When the “Chipcap” model is used in a schematic, its layout cell will need to be
assigned to the cell called “B” which is located in the “atc.gds” library. A view of
this cell is located in Figure 18.
Figure 17. Layer Mapping for ATC 700B Capacitors
22 Microwave Office
Circuit Layout
1 2
Figure 18. Layout for ATC 700B 100 pF Capacitor
Again, the correct layer mapping will be applied to this layout cell when a layout
is created from a schematic with an ATC 700B capacitor in the schematic.
GDSII Cell Stretcher for Thin Film Resistor

For the layout of the thin film resistor, there are several options that could be
used. The TFR element in Microwave Office has a layout created for it but the
model layers are programed into the code. It would be possible to create the
correct model layers and map to the current draw layers. The only problem with
this is that the overlaps are set for a MMIC process which not work for this pro-
cess. The second option is to create a custom parameterized layout cell for this
element using C++ as the source code. This is a very powerful technique but
can take some time to get up and running. The third option is to create a
GDSII cell that will change its shape based on the parameters of the TFR ele-
ment. This technique is simple to set up and will create the needed layout for
the TFR element for the chosen process.
The TFR element has two geometry parameters, the length (L) and the width
(W). The layout cell for this element will need to adjust its geometry based on
the L and W parameters of the TFR element. The design rules in this process
say that the transmission line metal must overlap the resistor material by 2 mils
Circuit Layout
to get a good connection. The GDSII cell stretcher can be configured to take
care of this overlap and adjust to the proper size.
The first step to drawing this layout cell is to create a new model layer for the
GDSII cell. When editing or creating GDSII cells, the only layers that can be
drawn on are the layers with GDSII formatting (i.e. 1_0) in the first layer map-
ping table. Therefore a new model layer in our “NEC Package” layer mapping
is created. The layer number doesn’t matter as long as it is a layer not already in
use. For this example, the new layer will be on layer 4, so the new model layer is
4_0 and it is mapped to the TFR draw layer. The next step is to create a new
GDSII cell library called “thin_film_resistor” and a new cell called “resistor”.
To create a new GDSII cell and library:
1. In the Layout Manager, right-click on Cell Libraries and choose New
GDSII Library. Enter the new library name and click OK.
2. Right-click on the new cell library and choose New Layout Cell. Enter the
new cell name and click OK.
3. A new artwork cell editor window will open. Draw the layout cell and save to
have it updated in the project.
The next step is to draw the base artwork for the cell stretcher. The initial
geometry can be anything because the cell stretcher can adjust the initial layout
to match the TFR model parameters. The first step is to add a rectangle on the
4_0>TFR layer.
To add a rectangle in an artwork cell:
1. Make the artwork cell the top level window.
2. Select the layer that the rectangle should be drawn on, from the layers avail-
able in the lower left window.
3. Click the Rectangle tool on the Draw Tools toolbar or choose Draw >
Rectangle.
4. Click on the initial rectangle point or type the Tab to enter the coordinates of
the initial point.
5. Hold down the mouse and drag to the final rectangle point or type the Tab
key to enter the coordinate in absolute or relative terms for the final point.
24 Microwave Office
Circuit Layout
For this artwork cell, the length is made to be 8 mils, this will make the 2 mil
overlap on each side easy to implement. The width is made to 4 mils. The next
step is to add the cell stretchers for the width and height of this cell. A cell
stretcher will adjust the geometry of a GDSII cell based on a model parameter.
To add the cell stretcher to a layout cell:
1. Make the artwork cell the top level window.
2. Choose Draw> Cell Stretcher.
3. Click and drag to draw the cell stretcher. Once initially placed move the
mouse to adjust the cell stretch direction and left click to finalize the placement.
Arrows will appear showing the stretch direction. If the cell should stretch in
both a positive and negative direction in reference to the stretcher, put the
mouse above the stretcher and click the mouse button again. If the cell should
only stretch on one side of the stretcher, put the mouse to that side and click
again. Draw the stretcher perpendicular to the direction that the polygon should
stretch.
4. Edit the stretcher properties by selecting the stretcher drawing, right-clicking,
and choosing Shape Properties.
The first stretcher added to the resistor cell is for the length of the resistor. The
stretcher is placed at the midpoint of the length of the drawing and is setup to
stretch in both a positive and negative direction as indicated by the arrows as
shown in Figure 19. The fill pattern for the resistor layer is turned off to better
see the stretcher.
Figure 19. Placement of the first cell stretcher to adjust the length of the resistor
Circuit Layout
Figure 20. Settings for 1st Cell Stretcher to Adjust the Length of the Resistor
The settings for the stretcher are shown in Figure 20.

The Multiplier is set to 0.5 since the cell is stretching both ways. The Parame-
ter is set to L since this direction will stretch based on the value for the parame-
ter L in the schematic element that will use this cell for layout. The Offset is set
to -5.06e-5 which is the equivalent in meters of 2 mils. The resistor layer should
have 2 mils of extra length on each side to satisfy the process design rules. This
offset takes off 2 mils from each side and leaves 2 mils on each side for the over-
lap. So now when a TFR component has this layout, when L is set to 100 mils,
the layout will draw 104 mils to satisfy the 2 mil overlap requirement on each
side of the resistor.
The second stretcher added to the resistor cell is for the width of the resistor.
The stretcher is placed at the midpoint of the width of the drawing as shown in
Figure 21.
Figure 21. Placement of the Second Cell Stretcher to Adjust the Width of the Resistor
26 Microwave Office
Circuit Layout
The properties of the width cell stretcher are the same as those in Figure 20 with
the exception that the Parameter is set to W. The offset is the same even
though the original drawing width was 4 mils instead of 8 mils. There is no extra
width needed for the resistor. Therefore, if a width of 0 is entered for the resis-
tor, the layout will have 0 width.
The final step is to draw the cell ports 2 mils from each edge of the cell, as is
shown in Figure 22.
The cell ports are set 2 mils from the edge of the resistor artwork as a final step
to have the 2 mil overlap be set automatically. Now when transmission line is
attached to this object, the edge of the transmission line will attach at the cell
port locations, which will be 2 mils beyond the edge of the resistor material.
Now anytime a TFR resistor is used in a schematic, the layout should be set to
this GDSII cell and it will draw correctly for this process.
0.0
0.0
2.0
2.0
4.0
1 2
0.0
0.0
8.0
Figure 22. Placement of Cell Ports and Cell Stretchers Shown with Dimensions
The progress this far is saved in a project called

After_setup_and_import.emp.
Adding Vias to the Device Source Leads

The starting point for this section is saved in a project called
Start_device_with_vias.emp.
Circuit Layout
For the balanced amplifier design, the effect of the via inductance was consid-
ered from the beginning of the design. It will also be necessary to know the
physical placement of the vias as the entire layout is pieced together. Therefore,
the layout with the device and vias is the next step in completing the layout. This
will be the footprint for the device as the circuit is completed.
The schematic for the device, the via feed lines, and the vias is shown in
Figure 23.
There is a transmission lines leading to each via since they must be spaced some
distance from the device. There are three components connected to the source
node of the device (the device and the via feed lines). There is no general way to
know how to connect all these schematic elements together in the layout. Each
layout cell has face properties that help take care of this situation. There is a face
number assigned to each cell port of the layout that maps to the node number of
the schematic element. If there are two or more cell ports assigned the same
node number, as was done for the NEC device previously,
SUBCKT
1 ID=S1
NET="N76038a"
MLIN
ID=TL1 MLIN
W =25 mil ID=TL2
L=38 mil W=25 mil
L=38 mil
VIA VIA
ID=V2 ID= V1
D= 25 mil
D=25 mil
H= 25 mil H=25 mil
T=.15 mil T=.15 mil
RHO=1 RHO=1
Figure 23. Schematic for Device, Via Feed LInes and Vias
then the faces will be designated by the cell port number and then have a letter
assigned to it. So for the source of the NEC device, there will be a face 3a and
3b. The proper connection of layout items is handled by setting up the proper
face properties for each layout cell.
To change a layout cell's face properties:
28 Microwave Office
Circuit Layout
1. Select the layout cell, right-click, choose Shape Properties, and click on the
Faces tab. Figure 24 displays the resulting dialog box.
Figure 24. Cell Options Dialog Box / Faces
2. Select the proper face from the Face list. When you select a face from the
list, the cell port on the layout will turn blue with a small line showing the direc-
tion of the cell port arrow.
3. Select the proper item that should connect to this face from the Snap to box.
This box will only list elements connected to the node selected in the Face list.
This connection face will turn red with a small line showing the direction of the
cell port.
4. By default, both faces will snap together centered. To change how the faces
snap together, change the settings in the Face Justification section. See the
layout chapter of the Microwave Office User Guide for more information on these
settings.
5. When done, click OK.
For the connection between the device and the via feed lines, the face properties
for the device ground leads and the via feed lines need to be set. The initial lay-
out for the schematic in Figure 23 is shown in Figure 25.
Note, that the node number for components will be important through out the
rest of this example. For a model that has two nodes, node one will have a diag-
Circuit Layout
onal slash in the line feeding up to the node. In Figure 23, both microstrip lines
have node one hooked to the vias. If there are more that two nodes, the node
numbers will be numbered in the schematic. If attempting to recreate this exam-
ple, please pay close attention to how elements are connected.
Figure 25. Initial Layout for Device, Via Feed Lines and Vias
To view a layout of a schematic:

1. Choose Schematic > View Layout, or click on the View Layout button
from the Main toolbar.
Since no face properties have been set, the layout is not configured properly.
The first step to correct this is to set the face properties for the device ground
connections. This is done by opening up the face properties for the device,
selecting Face 3a and assigning the Snap to to MLIN.TL1:2. Face 3a will now
snap to node 2 of the MLIN element called TL1. [Note, this step above assumes
that the lines were attached between the device and the vias in the schematic the
exact way Figure 23 is shown. The above Snap to command is snapping to port
2 of MLIN.TL1. If the line was switched in the schematic, then the Snap to
30 Microwave Office
Circuit Layout
would be MLINE:TL1:1.] The via feed lines need to be pulled back from the
device by 5 mils to give the assembler some room to place the device. This set-
ting is done in the Face Justification settings. The results of these settings are
displayed by port 3a on the device spaced by 5 mils from the original drawn
location of the cell port.
Figure 26. Face Settings for Bottom Ground Lead of Device
Figure 26 shows these settings with a view of the face property settings. The
lines are pulled away from the device to more clearly shown the face value set-
tings. Also notice that the layout is still trying to connect all the elements to the
same location as is shown by the connection traces.
Circuit Layout
Figure 27. Face Settings for Top Ground Lead of Device
Then Face 3b is assigned its Snap to property to MLIN.TL2:2 with the 5 mil
offset. These settings are shown in Figure 27 with the view of the faces. When
the new face properties are set the layout will look like Figure 28.
32 Microwave Office
Circuit Layout
Figure 28. Device Ground Connections with Face Connections Properly Set
Note that the two via feed lines are no longer hooked together as is shown by
the connection traces. When the layout is snapped together it will look like
Figure 29. This shows the proper configuration for the device and the vias.
To snap a layout together:
1. Choose Edit > Snap Together or click the Snap Together button from the
Main toolbar.
Figure 29. Device with Via Feed Lines and Vias when Snapped Together
The progress this far is saved in a project called

After_setup_and_import.emp.
Pre-Matched Device Layout

Start_prematch.emp
The layout is finally ready to piece together. All the setup is complete and all the
required artwork is either imported or setup to draw all the components for this
Circuit Layout
layout. In this balanced amplifier circuit, the device has matching elements
between the device and the balanced feedline lines coming from the Wilkinson
coupler. This pre-matched device schematic is shown in Figure 30. The device
with the via feeds set up previously is used in this schematic so the vias are
already set up properly.
The layout view for this schematic is shown in Figure 31.
MLIN
ID=TL18
W=35 mil SUBCKT
L=25 mil ID=S2
NET="500S100"
MLIN
PORT ID= TL16
P=3 W= 5 mil 1 VIA
MLIN
Z= 50 Ohm L=0 mil ID=TL17 I D=V3
W=35 mil D=25 mil
3 MTEE$ L= 25 mil H=25 mil
ID=TL15 T=. 15 mil
2 RHO= 1
MTRACE
I D= TL4
W= 10 mil MLIN MLIN
L=200 mil ID=TL5 ID=TL10
BType= 2 W=25 mil MTEE$ W=25 mil
M=0.6 L= 101 mil ID=TL11 L= 0 mil
MLIN MLIN MLIN 1 2

PORT ID=TL14 2 ID= TL8 I D= TL6 2
P=1 W=25 mil MCROSS$ W= 10 mil W= 30 mil
ID=TL1 MTEE$ 3 PORT
Z= 50 Ohm L=0 mil L=45 mil ID=TL12 L=51.39 mil P=2
SUBCKT Z= 50 Ohm
1 3 1 ID= S1
1 2
NET="N76038a"
3
MLEF
4 3 ID=TL9
W=25 mil
L=64.5 mil
MLEF MSUB
ID=TL13 MLIN Er= 9.9
MLEF I D= TL2 MLIN
W=39.5 mil ID=TL7 H=25 mil
W= 25 mil ID=TL3 T= 0.15 mil
L=7.5 mil W=25 mil W=25 mil
L=77 mil L=38 mil Rho= 1
L=38 mil Tand=0.0001
ErNom= 12.9
Name=SUB1
VIA
ID=V2 VIA
ID=V1
D= 25 mil D= 25 mil
H= 25 mil
H= 25 mil
T=0.15 mil T= 0.15 mil
RHO=1
RHO=1
34 Microwave Office
Circuit Layout
Figure 30. Schematic for the Pre-matched Amplifier
Figure 31. Initial Layout for Pre-matched Device
The first step when working with a layout is to anchor some part of the layout.
The layout tool knows how to attach all the pieces but it needs some reference
point. For this circuit, the device will be used as the anchor point. If nothing is
anchored, the layout can move and rotate when snapped together.
To make a layout an anchor point:
1. Select the item, right-click and choose Shape Properties from the menu.
2. Click the Layout tab, select the Use for Anchor box and click OK.
This setting is shown in Figure 32.
Circuit Layout
Figure 32. Setting to Anchor a Layout Item
The anchored item will now display with a red circle with a cross through it as is
shown in Figure 33.
Figure 33. Pre-matched Layout with Device Package Anchored
36 Microwave Office
Circuit Layout
Notice that there is no artwork for the chip capacitor by the blue color of the
schematic element and no layout in the layout view. The layout cell for the
capacitor must be changed to be the ATC 500 series footprint that was
imported earlier.
To change an elements layout cell:
1. Double-click on the schematic element and click the Layout tab.
2. Choose the layout from the Compatible Cells list on the right and click OK.
The capacitor in the schematic needs its layout changed to “cap” since this is the
name of the cell in the GDSII library for the 500 series capacitor. The dialog
box for his assignment is shown in Figure 34.
Now the layout for the capacitor should be seen and the connections to the
capacitor will all be snapped together as shown in Figure 35.
Figure 34. Dialog to Change Capacitor’s Artwork Cell
Circuit Layout
Figure 35. Pre-matched Layout with Capacitor Artwork Assigned
Now several properties for the chip capacitor must be set to have the layout
view properly. The first is to use the correct layer mapping for the capacitor.
To change the layer mapping for a layout item:
1. Select the item in the layout, right-click and choose Shape Properties.
2. Click the Layout tab and choose the proper layer mapping table from the
Layer Mapping list and click OK.
The layer mapping for the capacitor is changed to ATC 500 as is shown in
Figure 36.
38 Microwave Office
Circuit Layout
Figure 36. Layer Mapping Setting for Capacitor in Pre-match Schematic
The final thing to do with the chip capacitor is to change the face settings so
that the microstrip line leading up to the capacitor is sitting under the capacitor
mounting pads. This is done by setting an offset for the face settings of the
capacitor. Figure 37 shows the capacitor and the lines leading up to it before
the face setting changes.
Then, each face of the capacitor needs to be offset by 25 mils such that the Chip
Connection layer will overlap with the Tline layer. These face value settings are
shown in Figure 38
Circuit Layout
Figure 37. Initial Capacitor Connections to Adjacent Microstrip
Figure 38. Face Settings for Chip Capacitor in Pre-match Schematic
Note that for the offset settings, the positive y direction is the direction that the
cell port arrow is facing, not the orientation of the cell in the layout view. That is
40 Microwave Office
Circuit Layout
why the Delta Y is set to -25 mils. If the capacitor was rotated 90 degrees to the
right, the setting would still by -25 mils. The same setting is applied to face 2 for
the capacitor. When the face settings are done and the layout is snapped
together, the capacitor with the feed lines looks like Figure 39.
Figure 39. Finalized Layout of Chip Capacitor with Feed Lines
The next step in getting the pre-match layout correct is to adjust the gate and
drain face values for the packaged device. The via feed lines were pulled away
from the package by 5 mils. The gate and drain feeds need to also be pulled away
by 5 mils. Figure 40 shows the initial view of the device package with the gate
and drain lines directly against the package.
Now the face settings for the device node 1 and node 2 have a delta Y of 5 mils.
The fixed layout is shown in Figure 41.
Circuit Layout
Figure 40. Initial Gate and Drain Feeds Touching the Device Package
Figure 41. Final Gate and Drain Feeds Pulled Away from the Device Package
42 Microwave Office
Circuit Layout
Now that all the face properties are set for the components in this layout, the
final adjustment is to get all the lines properly oriented. Since there will be two
paths in the circuit with this pre-match cell, all of the long lines should point to
the outside of the circuit. In the pre-match cell, all of the long lines need to be
on the same side of the input and output lines. This means that the shunt
microstrip line with the capacitor in Figure 35 needs to be flipped about the x
axis. This can be done by changing the properties of the cross that feeds this
line. This cross needs to be flipped.
To flip a layout element:
1. Select the item with the mouse, right-click and choose Shape Properties.
2. In the dialog that displays, click the Layout tab, select the Flipped check box
in the Orientation area and click OK.
Once this command is done and the layout is snapped together the layout will
look like Figure 42.
Figure 42. Prematch Layout with Shunt Line Flipped about the X Axis
Circuit Layout
The shunt microstrip line with capacitor will fit better in the final layout if the
line is bent. This is done easily without changing the schematic since the this
shunt line was modeled using the MTRACE element. This element has the
same electrical model as a MLINE element except that its layout properties can
be changed in the layout view. The first thing to do is to make a bend in the
line. Please see the layout section in the Microwave Office User Guide for more
information on editing MTRACE elements.
To make a bend in an MTRACE element:
1. Select the line for editing by double-clicking on the line.
2. Put the mouse over the middle diamond. When the curser changes from
having 4 arrow to only having 2 arrows, click and hold on the line.
3. Drag the mouse in the direction of the bend. A shadow of the line will appear
showing what the line will look like when done.
4. Release the mouse button to finish the bend.
This MTRACE element is going to have a bend to the left. The bend shown
being made is in Figure 43.
Figure 43. Outline of MTRACE Bend Edit
44 Microwave Office
Circuit Layout
When executing this command, the length of the trace does not change and the
end of the line always faces in the same direction as the original line. Figure 44
shows the layout when the mouse is released.
Figure 44. MTRACE after Bend is Finished
The end of this line needs to be rotated so it faces to the left.

To rotate the end of a MTRACE element:
1. Select the line for editing by double-clicking on the line.
2. Put the mouse over the diamond on the end to be rotated. When the cursor
changes from having 4 arrows to only having 2 arrows, click and hold on the
line.
3. Hold down the ctrl key and drag the mouse in the direction the end of the
line should point. A shadow of the line will appear showing what the line will
look like when done.
4. Release the mouse button to finish changing the orientation of the end of the
line.
Circuit Layout
Changing the end orientation of the line is shown in the editing phase in
Figure 45.
Figure 45. Outline of MTRACE End Edit
The layout when the mouse is released is shown in Figure 46.
Figure 46. MTRACE After End Orientation Change is Finished
At this point the layout for the pre-matched cell is complete. A 3D view of the
layout can be viewed at any time.
46 Microwave Office
Circuit Layout
To view a 3D layout view:

1. Make either the schematic or the 2D layout the active window.
2. Choose Layout > View 3D Layout or click the View 3D Layout button on
the Main toolbar.
The 3D layout for the pre-matched device is shown in Figure 47.
Figure 47. 3D Layout of the Pre-matched Device
The progress this far is saved in a project called After_prematch.emp
Wilkinson Divider Layout

Start_Wilkinson.emp
A critical part of the balanced amplifier design is a power divider to split the RF
between the two paths of the amplifier. A Wilkinson divider is chosen for this
Circuit Layout
component. The Wilkinson is realized using microstrip elements and a thin film
resistor. Figure 48 shows the circuit schematic for this divider centered at 9
GHz.
MTEE
ID=TL4
W 1=12 mil
W 2=25 mil
W 3=10 mil
1 2 PORT
P=2
Z= 50 Ohm
L_wilk=156 3 MLIN
ID= TL6
W= 25 mil
L= 0 mil
MTRACE
ID= X1 MLIN
W= 12 mil ID=TL8
L= L_wilk mil W =10 mil
BType=2 L=22.5 mil
M=0.6 MSUB
Er=9.9
H= 25 mil
T= 0.15 mil
PORT Rho= 1
P= 1 1 TFR Tand=0.0001
Z=50 Ohm ID=TL5 ErNom=12.9
MTEE$ W =10 mil Name= SUB1
3 ID=TL2 L= 10 mil
RS= 100
2 F=0 GHz
MLIN
ID=TL1
W =25 mil
L= 0 mil
MTRACE
ID=X2
W=12 mil
L=L_wilk mil
BType= 2 MLIN
M= 0.6 ID=TL9
W =10 mil
L= 22.5 mil
3
PORT
2 1 P=3
Z= 50 Ohm
MTEE MLIN
ID= TL3 ID=TL7
W1= 25 mil W=25 mil
W2= 12 mil L=0 mil
W3= 10 mil
Figure 48. Schematic for the Wilkinson Divider
The layout for the resistor was assigned to the cell stretcher layout cell set up in
earlier steps. The initial layout for this element is shown in Figure 49, with the
resistor chosen as the anchor point as shown by the red circle in the resistor art-
work.
48 Microwave Office
Circuit Layout
Figure 49. Initial Wilkinson Layout
The initial layout is obviously not in the proper format even though the electri-
cal model is complete. The feed line to the resistor on the output side of the
divider is correct. The feed lines were chosen such that the lines coming out of
the divider will be spaced by two substrate thicknesses.
The microstrip lines of the divider need to be bent to make the layout piece
together. There are several approaches to accomplish this. The most obvious
approach is to model all the lines and bends to get the proper shape. In this
case, the layout is determining what the schematic will look like. This technique
will require the user to keep track of how much line length is used in each sec-
tion of bent line. Equations could be used to keep the length of both sides the
same. A much more elegant approach is to take advantage of MTRACE ele-
ments and the symmetry of this structure. Using the MTRACE elements for
these lines allow the layout to be adjusted while not affecting the schematic.
Additionally, it is possible to assign the bend and length properties of one
MTRACE (the slave) to another MTRACE (the master) such that any changes
made to the master will automatically be made to the slave, effectively creating a
symmetric structure. Changes to the master will be reflected in the slave, but not
vice-versa. For both MTRACE elements in this schematic, the length was previ-
ously made identical by assigning their value to the same variable. The bend
properties of one of these elements need to be assigned to the bend properties
of the other to make this work.
To make the bend properties of a MTRACE element (the slave) the same as
another MTRACE element (the master):
Circuit Layout
1. Double-click on the slave MTRACE in the schematic and click on the

Parameters tab.
2. Click on the Show Secondary box in the lower right corner to display the
DB and RB parameters.
3. Type a line with the syntax of “parameter@element.instance” where param-
eter is the model parameter of the referenced element, element is the type of
element and instance is the instance number of the referenced element.
4. Click OK.
For the Wilikinson, X1 is chosen to be the master and X2 is chosen to be the
slave. The settings for X2 are shown in Figure 50.
Figure 50. Slave MTRACE Settings
Now when the master MTRACE is changed the slave will follow. Figure 51
shows the MTRACE change being made to the master MTRACE.
50 Microwave Office
Circuit Layout
Figure 51. Master Bend for Wilkinson Combiner
Figure 52. Wilkinson Layout after Master Bend is Complete
Circuit Layout
Once the mouse is released, the resulting symmetric layout is shown in

Figure 52.
These steps were continued for the master MTRACE until the Wilkinson com-
biner looks like it should. The finalized Wilkinson layout is shown in Figure 53.
Due to the potential coupling in the lines of the Wilkinson, an electromagnetic
simulation will be done to verify the performance of the coupler in the present
configuration. To do this, the coupler can be copied and pasted into the EM
simulator. The first step is to set up the proper size of the EM simulation area.
Currently the Wilkinson divider is approximately 100 mils in the x direction by
140 mils in the y direction. Therefore a new EM structure must be created with
a work area that is 200 mils by 240 mils. 100 mils was added to each dimension
to leave room for feed lines and spacing to the sidewalls. Please see the Micro-
wave Office User Guide. for a detailed explanation on using the EM simulator.
Figure 53. Finalized Wilkinson Layout.
To create a new EM structure:

1. In the Project Browser, right-click on the EM Structures node, and choose
New EM Structure.
52 Microwave Office
Circuit Layout
2. Enter the name for the structure, select AWR EMSight Simulator and click
Create.
A new EM structure is created in the schematic called “wilkinson”. The proper
set up of the EM simulator will be left to the user to understand since it is out of
the scope of this example. The structure size is set to be 200 mils by 240 mils
with 2 mil cell sizes in both x and y. The dielectric layers are set up for a 25 mil
alumina substrate and both bottom and top enclosures are set to perfect con-
ductor. Now that the EM enclosure has been properly set up, it is time to copy
and paste the Wilkinson layout into the EM simulator. Since the EM material
properties and the EM layer mapping were previously set up, this process is
quite simple.
To copy a layout into the EM simulator:
1. Make the layout window the active window and select all the layout structures
by choosing Edit > Select All, by clicking and dragging the mouse over all the
layout elements, or typing Ctrl+A.
2. Copy the selected elements by choosing Edit > Copy or typing Ctrl+C.
3. Make the EM structure the active window and paste in the selected elements
by choosing Edit > Paste or typing Ctrl+V
4. Use the mouse to place the items in the EM structure.
Once the selected items are centered in the EM structure, feedlines and ports
must be added to the input and two output connections. De-embedding is then
set to reference the port parameters back to the original pasted layout elements.
The finalized EM structure is shown in Figure 54.
Circuit Layout
Figure 54. Final EM Layout for the Wilkinson Divider
In the view of the EM simulation for the wilkinson divider, the yellow diago-
nally hatched line is the 0.15 mil thick gold, the purple is the thin film resistor
material and the yellow square hatched lines are perfect conductor that is used
as the feedline which gets deembedded from the results. After this simulation is
run, the EM simulation can be brought into a schematic as a subcircuit to model
the electrical performance of this component. Also, since all the EM layer map-
ping is complete, the layout will display properly for this subcircuit. This will be
seen when the overall circuit layout is put together. However, you will want to
verify a setting. Select Options > Layout Options and select the Export/LPF
tab. Make sure the option Use Parent LPF for EM subcircuits. This setting
sets the EM mapping setup to be used when using an EM subcircuit in a sche-
matic. This will make sure the shapes in EM are displayed on the proper draw-
ing layers.
The progress this far is saved in a project called After_Wilkinson.emp
54 Microwave Office
Circuit Layout
Preliminary Balanced Amplifier

The starting point for this section is saved in a project called Start_Circuit.emp
At this point, all the layout for the individual pieces is complete so it is time to
put together the final layout. The schematic used to put the circuit together
minus the bias networks is shown in Figure 55.
MTEE$
ID=TL10 3
2 1
MLEF
ID=TL8 MTRACE
W=5 mil MTRACE ID=TL7
MTRACE ID=TL4
ID=TL11 L=0 mil W=25 mil
W=25 mil l_long=250 l_adj1 = .25
MLIN W=25 mil SUBCKT MLIN SUBCKT L=l_long*l_adj2 mil
ID=TL22 L=66.4 mil ID=S6 ID=TL9 ID=S3 MLIN L=l_long*l_adj1 mil BType=2
PORT ID=TL2 BType=2 delta=132.5 l_adj2 = 1-l_adj1
P=1 W=25 mil BType=2 NET="500S100" W=25 mil NET="wilkinson" 3 M=0.6
Z=50 Ohm L=25 mil M=0.6 L=30 mil W=25 mil M=0.6
L=l_short mil l_short=l_long-delta
1 2 SUBCKT
1 ID=S1 2
NET="prematch"
3 3
1 SUB CKT
ID=S2 2
MTRACE NET="prematch" 2 1
ID=TL6
W=25 mil MTRACE MLIN MLIN MTRACE MLIN
MSUB ID=TL3 3 ID=TL12 ID=TL13 ID=TL23
Er=9.9 L=L@MTRACE.TL4 mil ID=TL5 SUBCKT SUBCKT PORT
BType=2 W=25 mil ID=S4 W=25 mil ID=S5 W=25 mil W=25 mil P=2
H=25 mil W=25 mil
T=0.15 mil M=0.6 L=L@MTRACE.TL7 mil L=l_short mil NET="wilkinson" L=30 mil NET="500S100" L=66.4 mil L=25 mil Z=50 Ohm
BType=2 BType=2
Rho=1
M=0.6 M=0.6
Tand=0.0001
ErNom=12.9
Name=SUB1
MLIN
ID=TL1
W=25 mil
L=5 mil
Figure 55. Schematic for Preliminary Balanced Amplifier
For this schematic, the necessary components are added to the pre-matched
device to create the balanced amplifier. DC blocking capacitors are added with
the lines needed for connection. A subcircuit for the EM wilkinson combiner is
added at the input and output of the circuit. The pre-matched device is also
brought in as a subcircuit. Note that this is a three port subcircuit since a node
for the bias connection was added in the pre-matched device schematic. In the
balanced amp schematic one of these nodes is terminated with a zero length
open stub since only one gate bias connection is necessary. Finally the length of
line feeding up to the pre-matched device is added.
An amplifier is made balanced by having different length of line feeding the
input and output of the pre-matched devices. The difference in line is typically a
quarter wave. This means that any reflection from the pre-matched devices will
be 180 degrees out of phase back at the Wilkinson combiner and cancel each
other. The total length through each path is the same so the transmitted RF sig-
nal will be in phase at the output of the circuit. In the schematic, this is realized
using equations. Three equations are used to set the different line lengths.
“l_long” is the longer length of line feeding the input of one pre-matched cell
and the output of the other “delta” is the difference between the longer length
and the shorter length. “l_short” is the shorter length of line feeding the input
Circuit Layout
of one pre-matched cell and the output of the other and is equal to “l_long -
delta”. These were set up this way to set the difference between line lengths
which should be around a quarter wavelength. In the schematic, there are three
sections of line shown for the longer section of line. This is because a bias con-
nection must be made at the drain of the devices at some location. The bias for
the gates of the devices is included in the matching of the pre-matched device.
The bias will be brought in on the long line at the output of the top device.
Therefore, the long length of line is broken up into two section with a TEE ele-
ment for the bias connection. For the input of the bottom device, the line is
broken up the same way and a line of the same length as the TEE is used to
replace the TEE since a bias connection will not be made here. Finally, the loca-
tion of the TEE along the line is not yet determined. Therefore two more equa-
tions are used to help change this location easily. “l_adj1” is a multiplier for the
first long line length and “l_adj2” is the multiplier for the second long line
lengths. “l_adj1” will be less than 1 and “l_adj2” is equal to “1 - l_adj1” so the
entire length of this line will be constant. For example if the total length of line
is 1000 mils, and “l_adj1” is set to 0.25 then the first section of this total line
length will be 250 mils and the second section will be 750 mils.
To make the layout of this circuit even more simplified, the symmetry concepts
discussed in the Wilkinson combiner are also applied. The long line length seg-
ments on the output of the top pre-matched device are set at the masters and
the long line length segments on the input of the bottom pre-matched device
are set as the slaves. The Length, DB, and RB elements for the MTRACE slave
elements are all assigned to their corresponding master elements. So now only
changes to the “l_adj1” variable and the bends in the two master MTRACE ele-
ments will be needed to fully complete the layout for this part of the circuit.
The initial layout is shown in Figure 56 with the left most piece of transmission
line set as the anchor.
Anchor
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Circuit Layout
Figure 56. Initial Layout for the Preliminary Balanced Amplifier Circuit
The first step needed is to adjust the layer mapping for the chip capacitors and
the offset of the face values so the transmission line will sit underneath the chip
component. These are the exact same steps take for the chip capacitors in the
pre-matched device circuit since the ATC 500 series capacitor is used here.
When these settings are done, the new layout is shown in Figure 57.
Figure 57. Layout with DC Blocking Capacitors Changes
Notice the distance from the combiner to the blocking capacitors has changed.
Next, notice that the vias for the device are overlapping transmission lines.
Physically, this does not work, so the long feed lines need to be bent so that the
devices will be spaced properly from the transmission line. This is done with the
master MTRACE elements located on the output of the top device. Both of
these elements need a bend added in the middle and the end rotated 90 degrees
such that there is only one bend in each line. The slave elements automatically
mirror these changes. The technique to do this was shown for the Wilkinson
Circuit Layout
combiner so they will not be repeated here. The resulting layout is shown in
Figure 58.
Bias Connection
Figure 58. Layout after MTRACE Changes
The location of the bias connection on the long line on the output of the top
device should be closer to the bend. To make this change the MTRACE imme-
diately following the pre-matched cell is adjusted so that the bend occurs as
close to the pre-matched device (notice the pre-matched layout is a subcircuit so
it is shown surrounded by a square) as possible and the variable “l_adj1” is
changed to be 0.25. Also, the bend on the MTRACE next to the wilkinson com-
biner is adjusted so that the bend is as close to the wilkinson as possible. The
new layout is shown in Figure 59.
Now the physical spacing of the devices look good. The work needed to the get
the layout to this point was pretty simple resulting from taking advantage of the
symmetry of the circuit.
Now that the layout of the circuit is complete, it is time to get the circuit to fit in
the allocated space. The first step is to draw the size of the substrate for this cir-
cuit. This will be done by drawing a layout shape unassociated with a schematic
element.
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Circuit Layout
Bias Connection
Figure 59. Layout with

Variable and MTRACE Changes
To draw an unassociated
layout object:
1. Create the layout view of the circuit from the schematic.
2. Click on draw layer the shape will be drawn on in the lower left window of the
Layout Manager.
3. Choose the desired drawing shape (Rectangle, Circle, etc.) from the Layout
menu or click the buttons from the Draw Tools toolbar.
4. Use the mouse or the coordinate entry boxes to draw the shape and click OK.
For this circuit, there needs to be a substrate definition drawn that is 1000 mils
by 1000 mils. It will be placed such that the range in x values is from 0 to 1000
mils and the range in y values are from -500 to 500 mils since this is a symmetric
circuit.
A rectangle is drawn on the layout on the substrate layer. Since the coordinates
of the substrate are known, the drawing of this rectangle can easily be done
using the coordinate entry feature.
Circuit Layout
To use coordinate entry:

1. Select the desired drawing command and press the Tab key instead of clicking
the mouse for an entry point. The following window displays:
2. Enter the initial drawing point in absolute coordinates and click OK.
3. For subsequent drawing points, type the Tab key again. After the initial
drawing point, the coordinates can be set in absolute or relative terms. Enter
the next coordinate and click OK
4. Continue until the shape is drawn and double left click with the mouse to fin-
ish the drawing.
To draw the substrate definition, the substrate layer is chosen and then a rectan-
gle drawing is selected. Coordinate entry is used to draw the object. X is set to 0
Figure 60. Layout with Substrate Outline Added
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Circuit Layout
and Y is set to -500 for the first point. The second point is set to relative coordi-
nates and X is set to 1000 and Y is set to 1000. The resulting layout is shown in
Figure 60.
In the layer setup and draw layers tab, the substrate layer was selected to be fro-
zen. If this layer needs to be edited, the layer needs to be unfrozen. It is frozen
since it covers the entire layout area and editing objects in this area will require
that the substrate layer does not get edited. As you can see, the layout needs to
be centered in the substrate outline. This is easily changed by pressing Ctrl+A
and dragging the objects into the substrate area. Notice that the substrate out-
line was not selected since it was frozen. The resulting layout is shown in
Figure 61.
Figure 61. Layout with Circuit Moved Inside Substrate Outline
The next step is to center the circuit in the substrate area. The first step in cen-
tering is to measure the distance between the lower edge of the input transmis-
sion line and the upper edge of the output transmission line using the measure
tool.
Circuit Layout
To use the measure tool:

1. Choose Layout > Measure or click the Measure button on the Main tool-
bar.
Click and drag the mouse between locations to measure. A display will shown
the delta x, delta y, and the total distance between points. The cursor will auto-
matically snap to layout features such as polygon verticies.
The space in the y direction between the input and output lines is 178 mils.
Since the limits of the substrate in the y direction range from -500 mils to 500
mils, the center is at 0 mils. Therefore, to center the layout the bottom of the
input transmission line needs to be at 89 mils (178/2) and the top of the output
transmission line needs to be at -89 mils.
Now that the distance is known, it is time to move the left-most piece of trans-
mission line in the circuit to the correct location. This location is such that the
left edge of the transmission line is at the edge of the substrate outline and the
bottom edge is at 89 mils. To do this, the grid snap multiple must be changed to
0.1 since the input line is not on an even 1 mil grid.
To change the grid snap multiple:
1. Select the proper grid snap multiple from the Grid Snap Multiple box on the
Main toolbar.
This multiple will multiply the grid spacing setting in the layout options.
Now the first piece of transmission line can be moved to the correct location as
shown in Figure 62.
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Circuit Layout
Figure 62. Layout with First Input Line Placed Properly
Now when the layout is snapped together, it will be centered in the y direction.
The new layout is shown in Figure 63.
Circuit Layout
Figure 63. Layout Centered in the Y Direction
Now the output transmission line (the right most line) needs to be brought to
the right edge of the substrate outline. The top edge of this line was properly
aligned when the layout was snapped together so it only needs to be dragged to
the right and then this piece should also be anchored. The results of these steps
are shown in Figure 64.
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Circuit Layout
Figure 64. Layout with Output Line Properly Placed
Now to center the layout in the x direction the distance between the output
anchored line and its connection line is measured to be 65 mils. The entire lay-
out except for the substrate outline, the input line and the output line need to be
moved right by half this amount, or 32.5 mils. This exact amount is easily done
by using the relative coordinate entry for moving these objects. The resulting
layout is shown in Figure 65.
Circuit Layout
Figure 65. Layout Centered in the X and Y Direction
Now the input and output need to be connected together. This could easily be
done in the layout by selecting the lines next the anchored lines and stretching
them until the lines are connected. An alternate way to do this is to allow these
lines to stretch to fit.
To allow a line to stretch to fit:
1. Select the layout object, right-click and choose Shape Properties.
2. Select the Layout tab, select the Stretch to fit box and click OK.
This property is set for the line between the first input line and the input chip
capacitor and the line between the last output line and the output chip capacitor.
Now when the layout is snapped together, these lines will stretch to meet the
adjacent layout objects. The new line length will also be updated in the sche-
matic.
The connected layout that is centered is shown in Figure 66.
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Circuit Layout
Figure 66. Completed Preliminary Layout that is Connected and Centered
The 3D layout for the preliminary circuit layout is shown in Figure 67.
Circuit Layout
Figure 67. 3D Layout of the Preliminary Layout
Finalize Layout
The finalizing steps for this layout are to add the bias networks with bonding
pads and to add text on the substrate for descriptive purposes.
The output bias network will be constructed first. Since there was not a
grounded shunt stub in the matching network, a quarter wavelength stub with a
capacitive ground connection is used to bring in the drain bias. The 10 pF ATC
500 capacitor is used at the end of the stub. The line is made with an MTRACE
element so it can be traced properly while maintaining its length. All of the
capacitor values, face settings, and the layer mapping were set for this capacitor
in the pre-matched device subcircuit. These elements are copied from the pre-
matched device subcircuit and pasted to the end of this bias line. Therefore all
of the proper face values and layer mapping are already set for these elements.
The line length is adjusted so that the it is effectively quarter wavelength. This is
done by tuning the length until the simulation results are the same as before the
elements were added. The added bias line can be seen in Figure 68.
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Circuit Layout
Figure 68. Layout with the Output Bias Line Added
Now the line needs to be bent so that the via is not on the edge of the substrate.
The result is shown in Figure 69.
Circuit Layout
Figure 69. Layout with the Output Bias Line Bent to Fit on the Substrate
To help with stability, a 100 pF capacitor in series with a 50 Ω resistor are con-
nected in shunt with the bias line. The 100 pF capacitor is from the ATC 700B
library. The length of line feeding the capacitor does not affect the fundamental
match of the circuit, so the length is allowed to vary to help wire the circuit
together. Also, the pads for the capacitor are modeled as transmission line with
the face values offset so the transmission line sits underneath the chip capacitor
connections in the exact same manner as was done for the previous chip capac-
itors. The resistor modeling is the same as was done in the Wilkinson combiner
using the TFR resistor model and the layout using the GDSII cell stretcher.
The line feeding up to the shunt RC element is an MTRACE element in the
schematic. The initial layout with the shunt RC is shown in Figure 70.
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Circuit Layout
Figure 70. Layout with Line Feeding a Shunt RC Element Initially Placed
In this figure the layout mapping for the capacitor is set to the ATC 700 layer
mapping, the face offsets are adjusted for the capacitor and the lines feeding up
to it, and the resistor layout is assigned to the “resistor” cell in layout library.
Obviously, this initial placement won’t work, so the next step is to adjust the
MTRACE element to place the capacitor in the correct place. Since the line
length is not important, the trace routing feature can be used. The trace routing
feature allows the user to draw the center path for the MTRACE element and
then the electrical line length updates in the schematic when the trace routing is
done.
To trace route a MTRACE line:
1. Double-click on the line so that the editing diamonds are shown
2. Double-click on the diamond on the end of the line where the trace should
start.
Circuit Layout
3. Now a cursor will display the trace tool with the total length of the line and
the delta x and delta y values of the current leg being drawn.
4. Draw the center line for the trace using mouse clicks or coordinate entry.
5. Double right-click to end the trace routing, the length of the MTRACE ele-
ment will now update in the schematic.
The MTRACE element leading up to the shunt RC line is selected for trace
routing. The trace is run such that the shunt RC sits above and to the left of the
first chip capacitor on this bias line. Figure 71 shows a zoomed in view of the
line during the trace routing.
Figure 71. Trace Routing of the Output Bias Line
Figure 72 shows the line when the routing is done and some final adjustments
are made to the line.
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Circuit Layout
Figure 72. Finished Trace Routing of the Output Bias Line
Now, the bias network needs a large bond pad to bring the DC into the circuit.
Another large pad will be placed adjacent to the DC line and grounded so addi-
tional chip capacitors can be added at the DC connection point. In the sche-
matic, this connection is initially modeled with an open stub of some length.
The designer tuned this length over a very large range and saw little effect in the
circuit. Therefore the pad and line feeding up to it can be drawn in the layout
without having a schematic element to model it.
A 100 mil by 100 mil pad is placed at the top of the substrate on the Tline layer
using the rectangle draw command. A copy of this pad is placed directly to the
left of this pad and two vias are added to the ground pad. The vias were copied
and pasted from another location in the layout. These layout additions are
shown in Figure 73.
Circuit Layout
Figure 73. Layout with Bias Pads Added
Now the bias line needs to be connected from the shunt RC element to the
bonding pad. The easiest way to do this is to use the path drawing feature.
To draw a path in the layout:
1. Make the layout window the active window.
2. Select the desired draw layer from the bottom left window in the Layout Man-
ager.
3. Choose Layout > Path or click the Path drawing tool on the Draw Tools
toolbar.
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Circuit Layout
4. Use the mouse or coordinate entry to enter the center line coordinates for
the path. Note, holding down the shift key while drawing the path will only
allow each leg of the path to be drawn orthogonally in the x or the y direction.
5. Double left click to end the path drawing.
Most likely, the path drawn will not have the correct properties unless they were
initially set in Options > Layout Options in the Paths tab. These options can
be easily changed for each path.
To change a path’s properties:
1. Select the path to be edited, right-click and choose Shape Properties, then
click the Path tab.
2. Enter the proper path properties for the path width, the end type, and the
miter type and click OK.
A path is drawn from the center of the line at the shunt RC element to the bond
pad. The initial drawing is shown in Figure 74.
Figure 74. Initial Path Drawing with the Default Path Settings
Circuit Layout
After the path width is changed to 5 mils and the miter type is set to mitered, the
layout looks like Figure 75.
Figure 75. Final Path Drawing with the Correct Path Settings
Now that the output bias network is done, the same steps are repeated for the
input bias network starting from wiring the shunt RC element since the first
stub and capacitor are already placed. With all of these steps done, the layout
with the input bias network is shown in Figure 76.
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Circuit Layout
Figure 76. Layout with Finalized Bias Networks
Now all the circuit components are properly placed for this layout. The last step
is to add text to the circuit for descriptive purposes.
To add text to a layout:
1. Make the layout view the active window.
2. Choose Layout > Text or click the Text tool button on the Draw Tools tool-
bar.
3. Select the location for the text in the layout.

4. Type the text and press Enter.
Circuit Layout
Most likely, the text drawn will not have the correct properties unless they were
initially set in Options > Layout Options in the Layout Font tab. These
options can be easily changed for each text string.
To change a text string’s properties:
1. Select the text to be edited, right-click and choose Shape Properties, then
click the Font tab.
2. Enter the proper text properties for the text font, height, and drawing prop-
erties and click OK.
The most important text property is the Draw as polygons property. With this
option selected, the text will be drawn on a drawing layer as any other layout
polygon and will be exported on the selected layer. If not selected, it will drawn
as a text object that will not be associated with any layer.
Figure 77. Layout with Text Added
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Circuit Layout
For this layout, the type of circuit will be placed in the open space on the bot-
tom right of the substrate. The text “Balanced Amplifier” will be added.
Figure 77 shows the text with the layer set to the Tline layer, the text to draw as
polygons, and the size to be 40 mils.
Some additional text is added to shown the frequency range of the circuit and to
label the gate and drain bias. These additions are shown in Figure 78.
Figure 78. Final Layout with All Text Added
A final 3D view of the finished circuit is shown in Figure 79.
Circuit Layout
Figure 79. 3D Layout of Finalized Layout
The finished amplifier is in Balanced_Amp.emp.
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Balanced Amplifier Layout

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Balanced Amplifier Layout

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BALANCED AMPLIFIER LAYOUT

ELECTRICAL PERFORMANCE OF THE BALANCED

Balanced Amplifier Response

Gain Input Return Loss Output Return Loss

Figure 1. Circuit Gain and Return Loss

Figure 2. Project Options dialog box / Global Units

Figure 3. Layout Options dialog box / Layout

Figure 4. Default Drawing Layers

Figure 5. Added Draw Layers

Figure 6. Initial File Mapping Entries

Figure 7. 3D Properties Entries

The completed setup is shown in Figure 7.

Figure 8. EM Sight Mapping Setup

Line Type Setup

Figure 9. Line Type for Transmission Line called “Gold Line”

Via Drawing Setup

Figure 10. Via Drawing Definition

The progress this far is saved in a project called After_setup.emp.

Import Device Package Artwork

3. Locate the GDSII cell library and click Open .

Figure 11. Imported NEC 76038 Package Artwork

Figure 13. Initial Cell Port Locations and Numbers

To change cell port numbers:

Figure 14. Final Cell Port Locations and Numbers

Bringing in Chip Capacitor Artwork

Figure 15. Mapping Table for ATC 500 Capacitors

Figure 17. Layer Mapping for ATC 700B Capacitors

Figure 18. Layout for ATC 700B 100 pF Capacitor

GDSII Cell Stretcher for Thin Film Resistor

The settings for the stretcher are shown in Figure 20.

The progress this far is saved in a project called

Adding Vias to the Device Source Leads

Figure 24. Cell Options Dialog Box / Faces

To view a layout of a schematic:

Figure 26. Face Settings for Bottom Ground Lead of Device

Figure 27. Face Settings for Top Ground Lead of Device

The progress this far is saved in a project called

Pre-Matched Device Layout

MLIN MLIN MLIN 1 2

Figure 30. Schematic for the Pre-matched Amplifier

Figure 31. Initial Layout for Pre-matched Device

Figure 32. Setting to Anchor a Layout Item

Figure 33. Pre-matched Layout with Device Package Anchored

Figure 34. Dialog to Change Capacitor’s Artwork Cell

Figure 35. Pre-matched Layout with Capacitor Artwork Assigned

Figure 36. Layer Mapping Setting for Capacitor in Pre-match Schematic

Figure 37. Initial Capacitor Connections to Adjacent Microstrip

Figure 38. Face Settings for Chip Capacitor in Pre-match Schematic

Figure 39. Finalized Layout of Chip Capacitor with Feed Lines

Figure 43. Outline of MTRACE Bend Edit

Figure 44. MTRACE after Bend is Finished

The end of this line needs to be rotated so it faces to the left.

Figure 45. Outline of MTRACE End Edit

The layout when the mouse is released is shown in Figure 46.

Figure 46. MTRACE After End Orientation Change is Finished

To view a 3D layout view:

The 3D layout for the pre-matched device is shown in Figure 47.

Figure 47. 3D Layout of the Pre-matched Device

The progress this far is saved in a project called After_prematch.emp

Wilkinson Divider Layout

Figure 48. Schematic for the Wilkinson Divider

Figure 49. Initial Wilkinson Layout

1. Double-click on the slave MTRACE in the schematic and click on the