13-6

A 290MHz 50dB Programmable Gain Amplifier for

Wideband Communications
Hua-chin Lee, Chien-chih Lin, and Chorng-kuang Wang
Graduate Institute of Electronics Engineering and Department of Electrical
Engineering, National Taiwan University, Taipei, Taiwan

r------I
Abstract-This paper presents a CMOS programmable gain Baseband
PGA
) ~~~Mixer LPF I I
amplifier (PGA) with 3dB bandwidth greater than 290MHz. The
PGA can provide 50dB gain with 20dB gain control range, and gi tal~ ~ ~ ~ ~ ~ ~ ~ ~ ~i a
the gain step is ldB with -0.4 to +0.4dB gain error. The minimal I ~~~~baseband
acceptable input signal is -52dBm and the ldB compression point
is -6dBm. It consumes 4mA in core stage from 1V supply voltage. )Synthesizer
This PGA is fabricated in 90nm CMOS one-poly nine-metal
digital process and the core area is 0.2x0.15mm2.
Index Terms-Programmable gain amplifier, wideband com- Fig. 1. Block diagram of typical zero-IF architecture
munications, MB-OFDM, UWB, CMOS analog integrated cir-
cuits
RC filter is designed in this PGA. Fig.2 is the PGA architecture
with negative DC offset cancellation loop. Thereafter, the 3dB
I. INTRODUCTION bandwidth of the DC offset cancellation loop is designed in
More and more wireless data communication systems adopt 2KHz, and this makes large capacitor or resistor values. In
zero-IF architecture because it can reduce external compo- this design, the on-chip ploy resistor values is IOOKQ, and
nents. Fig.1 shows the block diagram of typical zero-IF the capacitor is 4.5nF which is connected externally. The
receiver architecture. In this architecture, the analog signal PGA composes of one subtractor stage, one buffer stage and
processing, such as filtering and amplifying, is perforned and three gain stages that provide 10dB, 5dB and 1dB-step gain
realized in baseband frequency. In addition, the DC offset of respectively. The subtractor stage provides 12dB fixed gain
the overall system should be notified and removed. In order and buffer stage provides 2dB gain with 50Q load. With the
to process appropriate signal level in the receiver chain, a gain control combinations of PGA shown in Fig.2, the gain
programmable gain amplifier (PGA) is often adopted. The control from 30dB to 50dB with 1dB step can be achieved.
PGA can adjust the received signal level so that the optimum The required output signal level is 300mV which is equivalent
output signal level can be processed in the digital baseband. to about -6dBm. Therefore, the minimal acceptable input
In recent years, most wireless wideband communication signal level is -56dBm.
systems utilize higher RF bands for data communication.
Therefore, more and more wireless wideband communication
systems, such as MB-OFDM UWB, are fabricated in advanced
CMOS technology. This paper presents the proposed PGA in
90nrm CMOS one-poly nine-metal digital process. Based on
negative resistive load [4] and exponential current control[5]
techniques, the measured gain of proposed PGA can be
programmed from 28 to 46dB in 1dB gain step with +0.4dB
gain error. Section II introduces the PGA architecture and gain Fixed Gain 10dB Gain 5dB Gain 1dB Gain
distribution of each gain stage. Section III A shows the circuit Stage Stage Stage Stage Buffer

design of fixed-gain subtractor stage, section III B discusses (+12dB) (+2, +12dB) (+7, +12dB) (+7 +12dB)-(+2dB)

the design of programmable gain stages, and section III C

describes the output stage designs. Section IV illustrates the Fig. 2. PGA architecture with DC offset cancellation
chip die photo, experimental results and performance summary
table.
III. CIRCUIT DESIGN
II. PGA ARCHITECTURE A. Subtractor Stage
The programmable gain amplifier (PGA) provides 30 50dB Fig.3 shows proposed subtractor stage with fixed gain.
gain range with 3dB bandwidth greater than 290MHz. Such The inputs of V0,+ and V,5 are DC terms from DC offset
a large AC gain will be suffered from small DC offset in any cancellation loop, and the DC offset can be subtracted in this
stages. Thus, the DC offset cancellation utilizing the passive stage. Transistors Ml, and M12 are the load of the stage, and

0-7803-9735-5/06/$20.00 ©2006 IEEE 379

this analysis will be discussed in next subsection. In 90nmM
CMOS technology, the output impedance of the NMOS/PMOS
is small. Therefore, there is a design issue to raise the output '1 = KP (VSG5- Vtp )2
impedance of each gain stage. Diode-connected M51M6 and +KP (VSG6 + VDD -VA_ Vtp )2 (3)
crossed-couple M7/M8 form a negative resistive load[4]. The '2 = Kp(VSG6 - )tp)
diode connected loads can produce internal common-mode +Kp(VSG5 + VDD VA_ Vtlp )2 (4)
voltage, and the common-mode feedback (CMFB) circuitry
is not needed. This negative resistive load can be controlled From Eq.3 and Eq.4, the difference of the two equations
by Vc, and then it can perform a higher output impedance shows I1 -2 = iR = 2Kp(VA -VDD)VOUt. For VA < VDD,
at the output. However, the stability criterion of the negative the negative resistor RN is shown as
resistive load should be discussed before the circuit design.
Vout = -1 -1
RN = tR 2KP(VDD -VA) gm8 -gM5
TVDD 1
gin7 -gn6 (5)
According to [4], the output resistance of the subtractor
can be represented as Rp,subt 1I . For

V5 7 M
w6
Rp = RN, the output impedance can then be cancelled.
Therefore, the stability criterion can be derived as

V0s+ oslVin+ ml Ml, 12 M2 n- OsM0

o-
VA >- VDD -2KIRp,5bt (6)
Eq.6 shows that the negative resistive load is stable under
this condition. Thus, the voltage controllable negative resistive
Mbl Mb2 Mb3 load yields high output impedance and wide bandwidth due
to no internal loads.

B. Programmable Gain Stage

Fig. 3. Subtractor with fixed gain stage The proposed programmable gain stages are shown in Fig.5
and Fig.6. The gain stage uses the same negative resistive load
concept to set the common-mode voltage and high output
Fig.4 presents the negative resistive load of the subtractor. impedance. From the previous work in [5], and the CMOS
Thus, the equation of the current can be represented as voltage controlled gain stage can vary exponentially. Fig.5
shows the 5dB/lOdB gain stage with two switch-controlled
loads. Transistors M1 and M2 form a source-coupled pair
input stage, and M1l, M12, M21, and M22 form the load
'1 KP (VSG5 Vtp )2 + Kp(VSG8 V)2 (1) stages. Therefore, the gain of each stage can be derived as
'2 KP (VSG6 Vtp )2 + Kp(VSG7 V)2 (2)
Av- gminput _ n(W/L)iIli
(9Tnlo.d)k VKn(W/L)1-l)k
(W/)i(Iinput) k-O I (7)
V((W/L)l)k (Iload) k
I

vc -
where gmiinput is the input transconductance value, and
gml1ad is load transconductance value. Eq.7 shows that
the small signal gain is proportional to the square root of
(W/L) ('bias) ratio between input stage and load stages. In
this proposed design, the input and load bias current are
fixed. Hence, the small signal gain is then proportional to the
square root of (W/L) ratio between input and load stages.
k denotes the digital controlled code by the switches on the
Fig. 4. Negative resistive load analysis
load transistors. In lOdB gain-step stage, when k = O, SW,
turns on and SW2 turns off. Therefore, gm1,ad changes and
Since VSG5 + VK = VA, VSG6 + VQ = VA, VSG7 + VK = A, equals to 2dB. When k = 1, SW1 turns off and SW2
VDD and VSG8 + VQ = VDD, Eq.1 and Eq.2 can be further turns on. Therefore, gm1,ad changes and A, equals to 12dB.
derived as In 5dB gain-step stage, the k changes gain of 7dB and 12dB.

380
 vn+l-1I Hvi.-

Fig. 5. 5dB/lOdB gain-step stage

Fig. 6. 1dB gain-step stage

In 1dB gain-step stage, there are six switch-controlled loads
so that it can be programmed from +7 to +12dB in 1dB step.
Fig.6 shows the 1dB gain-step stage circuit with the switch-
controlled loads. The gain of the 1dB gain-step stage can be
written as

AgTminput (WIL)
i/L)Ij
(gMlo.d)k VKn(W/L)1III)k
iWL (1input)
( (W/L)l)k('load) k = 0-5, k e N (8)

Eq.8 represents that the small signal gain varies if different

(W/L) ratio of the load applies. To perform 1dB gain step, Fig. 7. fT doubler output buffer
one of the six switches is turned on each time by different
digital controlled codes. Therefore, the 1dB gain-step stage
can vary gains from 7 to 12dB in 1dB step. Capacitors in the DC offset cancellation are connected exter-
nally by considering small chip area. The test chip is bonded
C. Output Buffer on the PCB with required external components. The input
Fig.7 presents the output buffer circuit design with fT impedance is a 50Q external resistor across the gate of input
doubler technique[6]. The voltage Vcm is chosen to be equal transistor, and the output impedance is a 50Q on-chip resistor.
to the common-mode voltage of Vin+ and Vin-. Hence, the As shown in Fig.9, the measured gain of the proposed PGA
two differential pairs operates without systematic offset, and is from 28dB to 46dB and the gain error is from -0.4dB to
the output can be derived as +0.4dB. The one-tone measurement is shown in Fig.10. The
measured output 1dB compression point is -OdBV, and is
Vout = gmn (Vin+ - Vin-) RL (9) isequivalent to -6dBm. Therefore, the maximum output level
around 300mV which is sufficient for the input signal level
From Eq.9, it shows that the overall gm is the same as the of ADC. According to [7], the output IP3 can be estimated
single source coupled pair type circuit. It can be deduced that as lOdBm greater than 1dB compression point. Thus, the
the input capacitance is Cgs/2, and then Eq.9 is valid under estimated output IP3 is 4dBm. This PGA consumes 4mA in
this configuration. This means the PGA gain stage can easily core circuit and lOmA in buffer stage. Tab.I summarizes the
drive the output buffer, and the buffer have the ability to drive measured performance of this chip and previous works.
output loads.
V. CONCLUSIONS
IV. EXPERIMENTAL RESULTS In this paper, a 290MHz 50dB programmable gain ampli-
Fig.8 shows the die photo of the PGA, and the active area fier for wideband communications is developed. With the volt-
is 0.2 x 0.15mm2. This design was fabricated in 90nm one- age controlled negative resistive load topology, the common-
poly nine-metal CMOS technology with IV power supply. mode feedback is not needed in the gain stages. By utilizing

381
 0-

-10 - EU-'

m -20 -
V N'
-F UZ-
00 -30 - N--
0
--

QL
-40 a- At

-50 -

-60 -
r
-80 -70 -60 -50 -40
Input Signal (dBV)

Fig. 8. PGA chip die photo

Fig. 10. Measurement of output 1dB compression point
TABLE I
46- -*-MeasuredGain SUMMARY OF CHIP PERFORMANCE AND PREVIOUS WORKS
44 - GainError,
42- ____________ ISSCC97[2] JSSC2005[3] This Work
40- Process 0.4,um CMOS 0.35,um CMOS 90nm CMOS
Chip size 1.2 x 1.35mm2 l 1.5 x 1.5mm2 0.2 x 0.15mm
38 - El Gain range -17 54dB -8 80dB 28-46dB
C5)
a) 36 - El,, Gain step 2dB ldB ldB
cn Gain step error -2.2-0.8dB -0.4-0.3dB -0.4-0.4dB
34-
Supply voltage 3.3V 1V
32 Current 2mA 13mA 4mA (core)
30 -E : lE consumption lOmA (buffer)
1dB CP(out) -3dBm OdBm -6dBm
28 IP3 (out) | 14.6dBm 4dBm (estimate)
3d1 bandwidth I2UIV Hz 112H1 z
LZ 29UlVlrHlz
-2 0 2 4 6 8 10 12 14 16 18 20 22
Gain Control Code
[3] C.-P. Wu, and H.-W. Tsao, "A 110-MHz 84-dB CMOS Programmable
Gain Amplifier With Integrated RSSI Function", IEEE Journal of Solid-
State Circuits, Vol. 40, No. 6, June 2005, pp.1249-1258.
Fig. 9. Measured gain and gain errors [4] S. Szczepanski, J. Jakusz, and R. Schaumann, "A Linear Fully Balanced
CMOS OTA for VHF Filtering Applications", IEEE Transactions on
Circuits and Systems-II: Analog and Digital Signal Processing, Vol.
44, No. 3, March 1997, pp.174-187
the switch controlled load, the programmable gain amplifier [5] Po-Chiun Huang; Li-Yu Chiou; Chorng-Kuang Wang,"A 3.3-V CMOS
can provide 28dB to 46dB gain in 1dB gain step with Wideband Exponential Control Variable-Gain-Amplifier", Proceedings of
+0.4dB accuracy. With the measured 1dB compression point the 1998 IEEE International Symposium on Circuits and Systems, 1998,
pp285 -288
of -6dBm, the minimal acceptable input signal is -52dBm. [6] B. Razavi; "Prospects of CMOS technology for high-speed optical com-
From the performance summary shown in Tab.I, the proposed munication circuits", IEEE Journal of Solid-State Circuits, Vol. 37, Issue
PGA is suitable for wideband communication systems, such 9, Sept. 2002, pp. 1135 1145 -

[7] B. Razavi, RF Microelectronics, Prentice Hall PTR, 1998

as MB-OFDM UWB systems.

VI. ACKNOWLEDGEMENT
The author would like to thank MediaTek Inc. for their
support on the integrated circuit development in National
Taiwan University and TSMC for chip implementation.

REFERENCES
[1] R. Schaumann, M. E. V. Valkenburg, Design of Analog Filters, Oxford
University Press, 2001
[2] F. Piazza et al., "A 2mA / 3V 71MHz IF Amplifier in 0.4m CMOS
programmable over 80 dB Range", IEEE ISSCC Dig. Tech. Papers, Feb.
1997, pp. 78-79.

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